CTNF 18/326,918 CTNF 99353 DETAILED ACTION This action is in response to the application filed 05/31/2023. Claims 1-20 are pending and have been fully examined. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Status of the Claims Claims 18-19 are rejected under 35 U.S.C. 112(b). Claim 1-2, 5, 7-12, 15-17, and 20 are rejected under 35 U.S.C. 102. Claims 3-4, 6, 13-14, and 18-19 are rejected under 35 U.S.C. 103. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 18 and Claim 19, by virtue of dependency, are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 18 recites, “individual of the second processor units comprises a second, the instructions…” on lines 3-4. It is unclear how the processor units may comprise a unit of time. A review of the disclosure (Claims 3, 13, and specification [0078, 0093, 0108]) reveals this limitation may be intended to recite “individual of the second processor units comprises a second buffer , the instructions…” For examination purposes, this line will be interpreted as “individual of the second processor units comprises a second buffer .” Claim 19 depends upon Claim 18. Claim 18 recites the limitation "store, in the second buffer…" in line 6. There is insufficient antecedent basis for this limitation’s recitation of “the second buffer” in the claim. Claim 19 depends upon Claim 18. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 5, 7-12, 15-17, and 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being unpatentable over Lewis (U.S. PGPub No. 20210256132). Regarding Claim 1 , Lewis teaches, A method comprising: storing, in a buffer of a processor unit, information indicating a plurality of register operations to cause the processor unit to enter into a management operating mode, the processor unit located in a computing system (where parameters are stored into a communication buffer or a set of CPU registers (another "buffer") [0029]; where parameters are indicative of an/ address(es) and are called in order to invoke firmware services, including triggering system management mode/management mode (SMM/MM) ("... to cause the processor unit to enter into a management operating mode") [0021]; where upon a CPU being placed in SMM/MM, it begins execution at a pre-defined entry point in SMRAM ("information indicating a plurality of register operations...") [0018]) ; and receiving, at the processor unit, information indicating that the processor unit is to enter the management operating mode (a CPU receives a system management interrupt (SMI) to be placed into SMM/MM ("information indicating") [0018]) ; and executing, by the processor unit, the register operations in response to receiving the information indicating that the processor unit is to enter the management operating mode (the CPU, upon being placed into SMM/MM, begins execution at a pre-defined entry point in the SMRAM ("the register operations") [0018]) . Regarding Claim 2 , Lewis teaches, The method of claim 1, further comprising the processor unit executing one or more management operating mode instructions while in the management operating mode (the CPU, upon being placed into SMM/MM, begins execution at a pre-defined entry point in the SMRAM ("the register operations") [0018]; the examiner notes that the execution of elements at the dedicated SMM/MM memory are "management operating mode instructions") . Regarding Claim 5 , Lewis teaches, The method of claim 1, the register operations to cause the processor unit to store a state of the processor unit (upon entering SMM/MM, some CPU registers are stored at a pre-defined memory location [0018]) . Regarding Claim 7 , Lewis teaches, The method of claim 1, wherein the information indicating that the processor unit is to enter the management operating mode comprises an interrupt (the information indicating the CPU entering SMM/MM is a system management interrupt [0018]) , wherein the information indicating the plurality of register operations to cause the processor unit to enter into the management operating mode are stored in the buffer prior to receiving the interrupt at the processor unit and the register operations are executed in response to receiving the interrupt at the processor unit (where parameters (examiner note: described above as "indicating the register operations," see [0018, 0021, and 0029]) may be stored in the communication buffer or [CPU] registers prior to the SMI being triggered [0034]; accessing the pre-defined entry point of the RAM begins executing upon entering SMM/MM) . Regarding Claim 8 , Lewis teaches, The method of claim 1, wherein storing the information indicating the register operations is performed during a startup sequence of the computing system (firmware may be executed during a boot ("startup") sequence [0034]; where firmware-provided services include using SMIs to trigger SMM/MM [0021]; where parameters (examiner note: described above as "indicating the register operations," see [0018, 0021, and 0029]) may be stored in the communication buffer or [CPU] registers prior to the SMI being triggered [0034]) . Regarding Claim 9 , Lewis teaches, The method of claim 1, wherein storing the information indicating register operations is performed out-of-band after completion of a startup sequence of the computing system (firmware may be executed during runtime ("after startup") [0034]; where the triggering of the SMI may occur by a firmware call made by an application or another calling entity ("out of band") [0028]) Regarding Claim 10 , Lewis teaches, The method of claim 1, wherein the buffer is dedicated for storing management operation mode register operations (the communication buffer or a set of CPU registers store the parameters ("dedicated") [0029]) . Claims 11-12 and 15 recite a shift in statutory category and are rejected under Lewis for the same reasons as Claims 1-2 and 8, above. Claims 16-17 and 20 recite a shift in statutory category and are rejected under Lewis for the same reasons as Claims 1-2, 8, and 10, above. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 3-4, 6, 13-14, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lewis in view of Zimmer et al. (U.S. PGPub No. 20080147945) . Regarding Claim 3, Lewis teaches, The method of claim 1, wherein the processor unit is a first processor unit, the buffer is a first buffer, ... individual of the ... processor units comprises a ... buffer, the method further comprising, for individual of the ... processor units: storing, in the ... buffer of the individual ... processor unit, the information indicating the register operations (where parameters are stored into a communication buffer or a set of CPU registers (another "buffer") [0029]; where parameters are indicative of an/ address(es) and are called in order to invoke firmware services, including triggering system management mode/management mode (SMM/MM) ("... to cause the processor unit to enter into a management operating mode") [0021]; where upon a CPU being placed in SMM/MM, it begins execution at a pre-defined entry point in SMRAM ("information indicating a plurality of register operations...") [0018]) ; and executing, by the individual ... processor unit the register operations (the CPU, upon being placed into SMM/MM, begins execution at a pre-defined entry point in the SMRAM ("the register operations") [0018]) . While Lewis discloses the use of a processor unit comprising a processor unit comprising a buffer employed for SMI-based SMM/MM triggering [0018, 0021, 0029], Lewis does not explicitly disclose the use of similarly arranged second processor units. Lewis does not explicitly disclose and Zimmer teaches, the computing system comprises one or more second processor units (in a multi-processor system, in response to an interrupt signal, all processors ("second") are activated into a management mode [0004]) It would have been obvious to one of ordinary skill in the art, before the filing date of the claimed invention, to modify the management mode process as disclosed by Lewis to incorporate one or more second processors as taught by Zimmer. The resulting combination allows for increased resources to be available in the computing system, as compared to only a single processor; advantages of increased resources include increased processing power and speed, and increased reliability in a situation where one of the plurality of processors may be unavailable. Regarding Claim 4 , Lewis does not appear to disclose and Zimmer teaches, The method of claim 3, the register operations to cause the second processor units to enter into an idle state (where implementations utilizing SMM capability include all processors being activated into a management mode, however only one processor services the request while the remaining processors wait ("second processor [in an] IDLE state") [0004]) . It would have been obvious to one of ordinary skill in the art, before the filing date of the claimed invention, to modify the management mode process as disclosed by Lewis to incorporate idling the one or more second processors as taught by Zimmer. The resulting combination prevents security vulnerabilities via the second processors being unable to access the SMRAM being accessed by the single processor in management mode; additionally, preventing auxiliary processor units from being active prevents other potential interference with the SMM execution. Regarding Claim 6 , Lewis does not appear to disclose and Zimmer teaches, The method of claim 5, the register operations to further cause the processor unit to exit the management operating mode, the register operations to cause the processor unit to exit the management operating mode cause the processor unit to restore the state of the processor unit (the processor is exited from management mode and control is returned to the prior processes [0047]) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the management mode process as disclosed by Lewis to include exiting the management mode as taught by Zimmer. The resulting combination allows for the processing to resume previous processing flow [Lewis; 0047] and prevent wasting potential execution power by processors sitting idle for a larger amount of time than necessary [Lewis; 0005] . 07-21-aia AIA Claim s 13-14 and 18-19 , individually, recite a shift in statutory category and are rejected under 35 U.S.C. 103 as being unpatentable over Lewis in view of Zimmer for the same reasons as Claims 3-4, above . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. (U.S. PGPub No. 20220206811) discloses a system including entering a management mode on a processor [0046]; where a SMI triggers management mode [0049]; where instructions are sent to a buffer of the processor [0054]; and processor state is stored [0076]. Tran (U.S. PGPub No. 20070204137) discloses system with replay circuits [0115]; where the queue acts as a buffer [0126]; where processor state is saved [0149]. McCoy (U.S. Patent No. 6584586) discloses a system employing SMI to indicate special conditions, where the system management mode includes a save state via capturing contents of the trace buffer and processor data structures. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUDREY E WHITESELL whose telephone number is (703)756-4767. The examiner can normally be reached 8:30am - 5:00pm MST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 5712723655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.E.W./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113 Application/Control Number: 18/326,918 Page 2 Art Unit: 2113 Application/Control Number: 18/326,918 Page 3 Art Unit: 2113 Application/Control Number: 18/326,918 Page 4 Art Unit: 2113 Application/Control Number: 18/326,918 Page 5 Art Unit: 2113 Application/Control Number: 18/326,918 Page 6 Art Unit: 2113 Application/Control Number: 18/326,918 Page 7 Art Unit: 2113 Application/Control Number: 18/326,918 Page 8 Art Unit: 2113 Application/Control Number: 18/326,918 Page 9 Art Unit: 2113
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