The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 8/14/2026.
Claims 1, 10 and 19 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 14, 2026 has been entered.
Response to Arguments
7. Applicant`s arguments filed August 14, 2026 have been fully considered but they are not persuasive with respect to prior art rejection.
8. As per the 103 rejection of claims 1, 10 and 19, Applicant argued Sharon fails to disclose or suggest the feature of " the critical operation including an operation identifier set by the host processor, the operation identifier designating the critical operation as requiring temperature-conditional processing, retrieve a temperature value of the memory array from the temperature sensor in response to identifying the operation as a critical operation”, where examiner relies on a newly cited reference Miyamoto to disclose the claimed limitation.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
US Patent 11,681,469
Instant Application 18/326,963
1. A device comprising: a memory array, the memory array comprising a plurality of addressable memory cells;
a temperature sensor positioned at a first location with respect to the memory array, the temperature sensor configured to record an average temperature of the memory array;
and a controller, the controller positioned at a second location with respect to the memory array, the controller configured to: receive an operation from a host processor, the operation accessing one or more of the memory cells of the memory array, identifying the operation as a critical operation or a non-critical operation based on one or more of a flag included in the operation, an address of the operation, or a data format of the operation,
when the operation is identified as a critical operation: retrieving a temperature value of the memory array from the temperature sensor
and conditionally processing the critical operation based on the temperature value,
and process the operation irrespective of the temperature value when the operation is identified a non-critical operation.
1. A device comprising: a memory array, the memory array comprising a plurality of addressable memory cells;
a temperature sensor positioned at a first location with respect to the memory array, the temperature sensor configured to record an average temperature of the memory array; and a controller,
the controller positioned at a second location with respect to the memory array, the controller configured to:
a critical operation from a host processor the critical operation including an operation identifier, identify the operation as a critical operation based on the operation identifier, identify the operation as a critical operation based on a property of the operation, retrieve a temperature value of the memory array from the temperature sensor,
and conditionally process the critical operation based on the temperature value.
2. The device of claim 1, wherein the critical operation comprises a critical read operation, the critical read operation including an address.
2. The device of claim 1, wherein the critical operation comprises a critical read operation, the critical read operation including an address.
3. The device of claim 2, the controller further configured to: query a critical access table using the address, the querying returning a plurality of addresses distributed among the plurality of addressable memory cells; read temperature data from the plurality of addresses; and process the critical read operation based on the temperature data and the temperature value returned by the temperature sensor.
3. The device of claim 2, the controller further configured to: query a critical access table using the address to identify a plurality of addresses distributed among the plurality of addressable memory cells; retrieve temperature data from the plurality of addresses; and process the critical read operation based on the temperature data and the temperature value returned by the temperature sensor.
4. The device of claim 3, wherein processing the critical read operation comprises executing a majority voter function on the temperature data, the majority voter function returning a selected temperature value from the temperature data.
4. The device of claim 3, wherein processing the critical read operation comprises executing a majority voter function on the temperature data, the majority voter function returning a selected temperature value from the temperature data.
5. The device of claim 4, wherein processing the critical read operation comprises determining that the temperature value is within a pre-configured range from the selected temperature value and reading data at the address included in the critical read operation.
5. The device of claim 4, wherein processing the critical read operation comprises determining that the temperature value is within a pre-configured range from the selected temperature value and reading data at the address included in the critical read operation.
6. The device of claim 5, wherein processing the critical read operation comprises determining that the temperature value is not within a pre-configured distance from the selected temperature value and returning an error.
6. The device of claim 5, wherein processing the critical read operation comprises determining that the temperature value is not within a pre-configured distance from the selected temperature value and returning an error.
7. The device of claim 1, the critical operation comprising a critical write operation.
7. The device of claim 1, the critical operation comprising a critical write operation.
8. The device of claim 7, wherein conditionally processing the critical operation comprises writing the temperature value to a plurality of locations in the memory array.
8. The device of claim 7, wherein conditionally processing the critical operation comprises writing the temperature value to a plurality of locations in the memory array.
9. The device of claim 8, wherein writing the temperature value to a plurality of locations in the memory array comprises writing the temperature value to a plurality of single-level cell (SLC) locations in the memory array.
9. The device of claim 8, wherein writing the temperature value to a plurality of locations in the memory array comprises writing the temperature value to a plurality of single-level cell (SLC) locations in the memory array.
10. A method comprising: receiving a first and a second operation from a host processor, the first and second operations accessing one or more of memory cells of a memory array, identifying the first operation as a critical operation based on one or more of a flag included in the operation, an address of the operation, or a data format of the operation, retrieving a temperature value of the memory array from a temperature sensor; and conditionally processing the critical operation based on the temperature value, and identifying the second operation as a non-critical operation based on one or more of a flag included in the operation, an address of the operation, or a data format of the operation, and processing the non-critical operation irrespective of the temperature value
10. A method comprising: receiving a critical operation from a host processor, retrieving a temperature value of a memory array from a temperature sensor, the temperature sensor positioned at a first location with respect to the memory array and configured to record an average temperature of the memory array; and conditionally processing the critical operation based on the temperature value.
20. A non-transitory computer readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining steps of: receiving an operation from a host processor, the operation accessing one or more of memory cells of a memory array, identifying the operation as a critical operation or a non-critical operation based on one or more of a flag included in the operation, an address of the operation, or a data format of the operation, when the operation is identified as a critical operation: retrieving a temperature value of the memory array from a temperature sensor; and, and conditionally processing the critical operation based on the temperature value, and processing the operation irrespective of the temperature value when the operation is identified a non-critical operation
19. A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining steps of: receiving a critical operation from a host processor, retrieving a temperature value of a memory array from a temperature sensor, the temperature sensor positioned at a first location with respect to the memory array and configured to record an average temperature of the memory array; and conditionally processing the critical operation based on the temperature value.
Claims 1-19 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-18 and 20 of U.S. Patent 11,681,469. Although the conflicting claims are not identical, they are not patentably distinct from each other because the method of claims 1-19 in the application 18/326,963 recites substantially all the limitations of the method of claims 1-18 and 20 in U.S. Patent 11,681,469 respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 rejected under 35 U.S.C. 103(a) as being unpatentable over Erez et al. (US PGPUB 2016/0162219 hereinafter referred to as Erez), in view of La Fratta et al. (US PGPUB 2022/0019533) (hereinafter ‘La Fratta’).
As per independent claim 1, Erez discloses a device comprising: a memory array, the memory array comprising a plurality of addressable memory cells [(Paragraphs 0020-0022) wherein Erez teaches where "one or more non-volatile memory die 104"; [0022] "If the host provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. (Alternatively, the host can provide the physical address.) to correspond to the claimed limitation]; a temperature sensor positioned at a first location with respect to the memory array, the temperature sensor configured to record an average temperature of the memory array [(Paragraphs 0020-0022) wherein Erez teaches where "In one embodiment, each of the memory dies 104 has its own temperature sensor 112"; as each die (array) has its own sensor, the sensor is positioned in respect to that die (array). As the single sensor is measuring the temperature of the die as a whole, it measures the average temperature as defined in [0022] of the supplied disclosure) to correspond to the claimed limitation]; and a controller, the controller positioned at a second location with respect to the memory array [(Paragraphs 0020-0022; FIG.1A) wherein Erez teaches where "Referring to FIG. 1A, non-volatile memory system 100 includes a controller 102"; as can be seen in Fig. 1A, the controller is in a second location with respect to the die (array) compared to the temperature sensor) to correspond to the claimed limitation], the controller configured to: receive a critical operation from a host processor [(Paragraphs 0020-0022; FIG.1A) wherein Erez teaches where "[0021] Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to nonvolatile memory die 104" to correspond to the claimed limitation], retrieve a temperature value of the memory array from the temperature sensor, and conditionally process the critical operation based on the temperature value [(Paragraphs 0020-0022, 0032 and 0037; FIG.1A) wherein Erez teaches where "By using temperature sensors and the temperature-aware media management layer module 138, each memory die can have its temperature individually sensed and tracked, and, when one of the memory dies reaches its temperature limit, memory accesses (e.g., new write and/or read commands) that would normally be routed to that memory die can instead be routed to a colder memory die, effectively individualizing thermal throttling on a per-memory-die basis"; [0037] "As used herein, “thermal throttle operations” refers to limiting the number of writes and/or read accesses performed to a memory die to some smaller number than normal (e.g., 50%, 25%, etc.) or to no memory access at all" to correspond to the claimed limitation].
Erez does not appear to explicitly disclose receive a critical operation from a host processor the critical operation including an operation identifier, identify the operation as a critical operation based on the operation identifier.
La Fratta discloses receive a critical operation from a host processor the critical operation including an operation identifier, identify the operation as a critical operation based on the operation identifier [(Paragraph 0018) where La Fratta teaches wherein instead of processing memory requests in the order in which the memory subsystem receives or generates the requests, the memory subsystem can place some preference on processing read requests originating from host systems over other pending memory requests (e.g., write requests from the host system and read and write requests from other sources) while still honoring memory request dependencies. In particular, as a memory request is received by a cache controller of the memory subsystem, the cache controller adds the memory request into a cache controller command queue. The cache controller command queue stores the memory request along with a priority indication, which indicates whether the memory request is a high priority or a low priority request. The cache controller sets the newly received request to a high priority if (1) the memory request is a read request received from a host system or (2) a high priority request depends from the newly received request (e.g., requests that access the same sector, line, or other unit of access from the memory devices or cache). The cache controller can periodically iterate the cache controller command queue to select a memory command for issuance to a Dynamic Random-Access Memory (DRAM) controller with consideration to the priority of the memory requests. The DRAM controller can issue and fulfill received memory requests with selective prioritization of high priority requests, including read requests received from host system, based on a high priority flag (i.e., the DRAM controller prioritizes high priority commands when the high priority flag is set). To ensure the memory subsystem does not ignore low priority requests, the cache controller can alternate issuance of low and high priority requests (in equal or unequal turn-taking) to the DRAM controller when both types of requests are available to correspond to the claimed limitation].
Erez and La Fratta are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Erez and La Fratta before him or her, to modify the system of Erez to include the critical priority flags of La Fratta because it will improve data storage access performance.
The motivation for doing so would be to [ provide greater processing improvements to host systems (e.g., reductions in processing of read requests originating from the host system) (Paragraph 0018 by La Fratta)].
Erez/ La Fratta does not appear to explicitly disclose the critical operation including an operation identifier set by the host processor, the operation identifier designating the critical operation as requiring temperature-conditional processing, retrieve a temperature value of the memory array from the temperature sensor in response to identifying the operation as a critical operation.
Miyamoto discloses the critical operation including an operation identifier set by the host processor, the operation identifier designating the critical operation as requiring temperature-conditional processing [(Paragraphs 0029, 0050-0053 and 0111-0116) where Miyamoto teaches wherein the performance control interface 20A receives an instruction related to performance control (hereinafter, referred to as a performance control instruction) transmitted from the host 60A. Specifically, the performance control interface 20A receives, as the performance control instruction, a combination of information indicating the use resources used for operations (information for identifying use resources) (hereinafter, referred to as an available resource ID) and the number of resources for each use resource (the number of parallel operations). In the performance control instruction, for example, the type of use resource (available resource ID) and the number of parallel operations to be changed are designated; when the host 60A writes data to the NAND memory 11, the operation mode may be changed, depending on, for example, the number of bad blocks. As the operation mode of the memory system 10A, there are the following two modes as well as the normal mode: A read only (RO) mode: the memory system 10A does not receive a writing operation from the host 60A, performs the writing operations initiated the drive by itself (for example, management information, statistical information, refresh, compaction, and wear leveling). The memory system 10A changes to the RO mode, for example, when the number of bad blocks or the error rate during a reading operation is equal to or greater than a predetermined value; and A write protected (WP) mode: the memory system 10A prohibits all processes involving the writing of data to the NAND memory 11; the host 60A may transmit transition conditions to the above-mentioned operation mode to the memory system 10A, instead of the endurance information. For example, the host 60A may transmit a first threshold value of the number of bad blocks or the error rate during a reading operation as transition conditions to the RO mode to the memory system 10A. In addition, the host 60A may transmit a second threshold value of the number of bad blocks or the error rate during a reading operation as WP mode to the memory system 10A to correspond to the claimed limitation], retrieve a temperature value of the memory array from the temperature sensor in response to identifying the operation as a critical operation [(Paragraphs 0050-0053 and 0111-0116) where Miyamoto teaches wherein the host 60B transmits a performance control instruction which can achieve the temperature/performance characteristics 80 to the memory system 10B. For example, the host 60B transmits parameters (for example, T.sub.1 to T.sub.4 and X.sub.1 to X.sub.3) for defining the curves (hysteresis) of st1 to st4 to the memory system 10B. The parameters for defining the curves of st1 to st4 may be registered in the memory system 10B in advance. In this case, the memory system 10B performs an operation corresponding to the temperature/performance characteristics 80, without receiving the performance control instruction from the host 60B. The installation environment of the storage server system varies depending on an installation place, such as weather, a region, and air-conditioning equipment. Therefore, the amount of heat which can be dissipated from the memory system 10B varies depending on the memory system 10B. Therefore, there is a demand for controlling the amount of heat generated from the same storage server system according to an environment. In this embodiment, since the memory system 10B includes the temperature setting interface 26, it is possible to easily maintain the appropriate operation environment of the storage server system. In this embodiment, the temperature measurement unit 30 transmits the measurement result of the temperature to the host 60B. However, the measurement result of the temperature may be transmitted to the host 60B through the performance control interface 20B. In addition, the performance control interface 20B may not include the resource usage interface 25x to correspond to the claimed limitation].
Erez and Miyamoto are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Erez and Miyamoto before him or her, to modify the system of Erez to include the critical priority flags of Miyamoto because it will improve data storage access performance.
The motivation for doing so would be to [ “reduces costs, ensures components, and improves maintainability, without changing the performance of the server system” (Paragraph 0144 by Miyamoto)].
Therefore, it would have been obvious to combine Erez, La Fratta and Miyamoto to obtain the invention as specified in the instant claim.
As per dependent claim 2, Erez discloses wherein the critical operation comprises a critical read operation, the critical read operation including an address [(Paragraphs 0020-0022; FIG.1A) wherein Erez teaches where Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to nonvolatile memory die 104"; [0022] "If the host provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. (Alternatively, the host can provide the physical address.); the controller receives requests from the host to access the memory (read, program, or erase). As currently and broadly claimed, no particular method of determining if data is critical or not has been established. As an entire device can be considered critical per [0005], every memory access is critical. Thus in this instance, all operations are critical operations to correspond to the claimed limitation].
As per dependent claim 3, Erez discloses the controller further configured to: query a critical access table using the address to identify a plurality of addresses distributed among the plurality of addressable memory cells [(Paragraphs 0020-0022 and 0040; FIG.5) wherein Erez teaches where "As shown in the flow chart of FIG. 4, a media management layer module typically considers and weighs various factors in making a die selection 410….the media management layer module 138 also factors in temperature consideration 460 of the memory dies"; when the system of Erez receives an access request (read), the system uses the supplied logical address to query a temperature history table for the requested die and for the other die in the system to determine which die to send the request to) to correspond to the claimed limitation]; retrieve temperature data from the plurality of addresses [(Paragraphs 0020-0022 and 0040; FIG.5) wherein Erez teaches where "As shown in the flow chart of FIG. 4, a media management layer module typically considers and weighs various factors in making a die selection 410….the media management layer module 138 also factors in temperature consideration 460 of the memory dies"; when the system of Erez receives an access request (read), the system uses the supplied logical address to query a temperature history table for the requested die and for the other die in the system to determine which die to send the request to) to correspond to the claimed limitation]; and process the critical read operation based on the temperature data and the temperature value returned by the temperature sensor [(Paragraphs 0020-0022 and 0040; FIG.5) wherein Erez teaches where "As another example, in considering temperature, the controller 102 can weight different temperature readings in making a die selection decision" to correspond to the claimed limitation].
As per dependent claim 4, Erez discloses wherein processing the critical read operation comprises executing a majority voter function on the temperature data, the majority voter function returning a selected temperature value from the temperature data [(Paragraphs 0020-0022 and 0040-0041; FIG.5) wherein Erez teaches where weights can be added to the processing of the temperature data to conditionally process the access request. One of the given methods of Erez to weight the data is to use the average over time. As a median value is a type of average, and is the more common term used when discussing the claimed majority voter function, it would be obvious to a person of ordinary skill in the art before the effective filing date of the invention to implement the weighting function of Erez using the median value. As there is only a limited number of average types (mean, median, mode), it would be Obvious to try utilizing the median average to provide a predictable solution with a reasonable chance of success to correspond to the claimed limitation].
As per dependent claim 5, Erez discloses wherein processing the critical read operation comprises determining that the temperature value is within a pre-configured range from the selected temperature value and reading data at the address included in the critical read operation [(Paragraphs 0020-0022 and 0041; FIG.1A) wherein Erez teaches where "For example, as shown in FIG. 5, different weights can be assigned to dies of different temperatures, so that a weight of 10 (most recommended) is assigned the coldest die, a weight of 1 (least recommended) is assigned to the warmest die, and a weight of 0 (prohibited) is assigned to a die that has reached the critical temperature threshold"; the distance is the value between the current value and the threshold, as long as the current value has not breached the threshold, the value is within an acceptable distance and the access can be performed to correspond to the claimed limitation].
As per dependent claim 6, Erez discloses wherein processing the critical read operation comprises determining that the temperature value is not within a pre-configured distance from the selected temperature value and returning an error [(Paragraphs 0020-0022 and 0041; FIG.1A) wherein Erez teaches where "For example, as shown in FIG. 5, different weights can be assigned to dies of different temperatures, so that a weight of 10 (most recommended) is assigned the coldest die, a weight of 1 (least recommended) is assigned to the warmest die, and a weight of 0 (prohibited) is assigned to a die that has reached the critical temperature threshold"; a weight 0 in which access vis denied is an error to correspond to the claimed limitation].
As per dependent claim 7, Erez discloses the critical operation comprising a critical write operation [(Paragraphs 0020-0022; FIG.1A) wherein Erez teaches where Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to nonvolatile memory die 104"; the controller receives requests from the host to access the memory (read, program, or erase). As currently and broadly claimed, no particular method of determining if data is critical or not has been established. As an entire device can be considered critical per [0005], every memory access is critical. Thus in this instance, all operations are critical operations to correspond to the claimed limitation].
As per dependent claim 8, Erez discloses wherein conditionally processing the critical operation comprises writing the temperature value to a plurality of locations in the memory array [(Paragraphs 0020-0022; FIG.1A) wherein Erez teaches where Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to nonvolatile memory die 104"; the controller receives requests from the host to access the memory (read, program, or erase). As currently and broadly claimed, no particular method of determining if data is critical or not has been established. As an entire device can be considered critical per [0005], every memory access is critical. Thus in this instance, all operations are critical operations to correspond to the claimed limitation].
As per dependent claim 9, Erez discloses wherein writing the temperature value to a plurality of locations in the memory array comprises writing the temperature value to a plurality of single-level cell (SLC) locations in the memory array [(Paragraphs 0020-0023) wherein Erez teaches where "The memory cells can also be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), or use other memory technologies, now known or later developed. Also, the memory cells can be arranged in a two-dimensional or three dimensional fashion"; in this instance the memory cells are SLC to correspond to the claimed limitation].
As for independent claims 10 and 19, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claim 11, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
As for dependent claims 12 and 20, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
As for dependent claim 16, the applicant is directed to the rejections to claim 7 set forth above, as they are rejected based on the same rationale.
As for dependent claim 17, the applicant is directed to the rejections to claim 8 set forth above, as they are rejected based on the same rationale.
As for dependent claim 18, the applicant is directed to the rejections to claim 9 set forth above, as they are rejected based on the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED GEBRIL whose telephone number is (571)270-1857. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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