DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1-5, 7-13, 15-20 are pending, independent claims 1, 9 , and 17 are amended, claims 6 and 14 are cancelled.
Applicant’s arguments on pages 8-11, filed 12/19/2025 with respect to U.S.C. 102/103 rejection of claims 1-5, 7-13, 15-20 have been fully considered but they are not considered persuasive.
Applicant argues that Yu, Shin, Im, and Kameyama, whether alone or in combination, fail to disclose the limitation originally from claim 6 now in claim 1, that an external resistor is electrically connected between the node and the fixed voltage.
Examiner respectfully disagrees. In Fig 10 of Yu, the resistor Rt must be external to the test loop. Rt is an external resistor in regards to the test loop, as the test loop can complete its pass without going through the resistor. Rt is between the node found above Tt and the second power supply VCC that provides constant voltage. Thus, Rt is external to the test loop, and likewise Rr is also external to the test loop. For at least these reasons, Applicant’s argument is not persuasive.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 17, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 9418596 B2 from IDS submitted on 4/11/2024).
Regarding Claim 1, Yu teaches a panel (col 2 line 67 “panel 160.”); a detection system (col 5 line 64-66 “As shown in FIG. 6, the timing controller 130 comprises a short circuit detector 135 comprising a pulse generator 131, a pulse comparator 133, and a shutdown signal generator 132 (i.e., a detection system)” and col 7 lines 4-6 “FIGS. 7 to 9 are views for explaining an example of short circuit detection using a pulse transmitter and a pulse receiver that operates in connection with the timing controller (i.e., detection system)”); and a test loop, electrically connected to the panel and the detection system (col 2 line 23-27 “FIGS. 7 to 9 are views for explaining an example of short circuit detection (i.e., figures demonstrate a test loop) using a pulse transmitter and a pulse receiver that operates in connection with a timing controller in accordance with a second example embodiment of the present invention;”); wherein the detection system comprises a detection unit and a controller and the detection unit is configured to detect a signal transmitted by the test loop, and provide a detection result to the controller (col 7 lines 4-6 “FIGS. 7 to 9 are views for explaining an example of short circuit detection using a pulse transmitter and a pulse receiver (i.e., pulse receiver detect pulses so it is a detection unit) that operates in connection with the timing controller” and col 6 line 29-31 “The pulse comparator 133 receives the output pulses PLS2 through the second terminal 102 of the timing controller 130.” And col 6 line 33-34 “The pulse comparator 133 compares the input pulses PLS1 and the output pulses PLS2,”) wherein one end of the test loop is electrically connected to a power-supply voltage (col 4 line 61-62 “That is, the timing controller 130 forms a kind of closed loop with the guide line GR formed on the panel 160 (i.e., test loop)” where col 4 line 6-13 “The power supply part 125 converts external voltages supplied from the outside, and outputs a first potential voltage ( e.g., around 20 V), a second potential voltage ( e.g., around 3.3 V), a low potential voltage (e.g., around OV), etc. The first potential voltage is a drain-level voltage supplied to the first power supply line VDD, the second potential voltage is a collector-level voltage supplied to a second power supply line VCC,”), the other end of the test loop is electrically connected to a fixed voltage (col 4 line 9-14 “a low potential voltage (e.g., around 0V), etc. The first potential voltage is a drain-level voltage supplied to the first power supply line VDD, the second potential voltage is a collector-level voltage supplied to a second power supply line VCC, and the low potential voltage is a base-level voltage supplied to the ground line GND.” Where figure 10 shows the GND being connected in two spots of the loop), the detection unit is electrically connected to a node of the test loop (Fig 10, where the detection unit (170, 130 and 180) are fixed to the nodes TP2 and TP4), and an external resistor is electrically connected between the node and the fixed voltage (col 7 line 47-53 “FIGS. 6 and 10, the pulse transmitter 170 comprises a first resistor Rt and a first transistor Tt. The pulse transmitter 170 serves to transmit the input pulses PLS1 output from the pulse generator 131 connected to the first terminal 101 of the timing controller 130 to the guide line GR. To this end, one end of the first resistor Rt is connected to the second power supply line VCC,”, where the resistors are external to the panel under test).
Regarding Claim 17, Yu teaches a panel (col 2 line 67 “panel 160.”); a detection system (col 5 line 64-66 “As shown in FIG. 6, the timing controller 130 comprises a short circuit detector 135 comprising a pulse generator 131, a pulse comparator 133, and a shutdown signal generator 132 (i.e., a detection system)” and col 7 lines 4-6 “FIGS. 7 to 9 are views for explaining an example of short circuit detection using a pulse transmitter and a pulse receiver that operates in connection with the timing controller (i.e., detection system)”); and a test loop; the test loop is electrically connected to the panel and the detection system (col 2 line 23-27 “FIGS. 7 to 9 are views for explaining an example of short circuit detection (i.e., figures demonstrate a test loop) using a pulse transmitter and a pulse receiver that operates in connection with a timing controller in accordance with a second example embodiment of the present invention;”), and the detection system comprises a detection unit and a controller (col 7 lines 4-6 “FIGS. 7 to 9 are views for explaining an example of short circuit detection using a pulse transmitter and a pulse receiver (i.e., pulse receiver detect pulses so it is a detection unit) that operates in connection with the timing controller”); wherein the detection method comprises: applying a signal to the test loop (col 7 line 14-17 “The pulse transmitter 170 serves as a pulse transmission. buffer that receives input pulses PLS1 from the pulse generator 131 and transmits the input pulses PLS1 through one end of the guide line GR.”); the detection unit receives the signal through the test loop (col 6 line 29-31 “The pulse comparator 133 receives the output pulses PLS2 through the second terminal 102 of the timing controller 130.” Where the output is the signal through the test loop); and the detection unit detects the signal transmitted through the test loop, and provides a detection result to the controller (col 6 line 29-31 “The pulse comparator 133 receives the output pulses PLS2 through the second terminal 102 of the timing controller 130.” And col 6 line 33-34 “The pulse comparator 133 compares the input pulses PLS1 and the output pulses PLS2,”); wherein one end of the test loop is electrically connected to a power-supply voltage (col 4 line 61-62 “That is, the timing controller 130 forms a kind of closed loop with the guide line GR formed on the panel 160 (i.e., test loop)” where col 4 line 6-13 “The power supply part 125 converts external voltages supplied from the outside, and outputs a first potential voltage ( e.g., around 20 V), a second potential voltage ( e.g., around 3.3 V), a low potential voltage (e.g., around OV), etc. The first potential voltage is a drain-level voltage supplied to the first power supply line VDD, the second potential voltage is a collector-level voltage supplied to a second power supply line VCC,”), the other end of the test loop is electrically connected to a fixed voltage (col 4 line 9-14 “a low potential voltage (e.g., around 0V), etc. The first potential voltage is a drain-level voltage supplied to the first power supply line VDD, the second potential voltage is a collector-level voltage supplied to a second power supply line VCC, and the low potential voltage is a base-level voltage supplied to the ground line GND.” Where figure 10 shows the GND being connected in two spots of the loop), the detection unit is electrically connected to a node of the test loop (Fig 10, where the detection unit (170, 130 and 180) are fixed to the nodes TP2 and TP4), and an external resistor is electrically connected between the node and the fixed voltage (col 7 line 47-53 “FIGS. 6 and 10, the pulse transmitter 170 comprises a first resistor Rt and a first transistor Tt. The pulse transmitter 170 serves to transmit the input pulses PLS1 output from the pulse generator 131 connected to the first terminal 101 of the timing controller 130 to the guide line GR. To this end, one end of the first resistor Rt is connected to the second power supply line VCC,”, where the resistors are external to the panel under test).
Regarding Claim 2, Yu teaches the limitations of claim 1.
Yu further teaches wherein the detection unit comprises a comparator (col 6 line 29 “The pulse comparator 133), a first end of the comparator receives the signal transmitted by the test loop (col 6 line 4-6 “The pulse generator 131 generates input pulses PLS1, and outputs the generated input pulses PLS1 through the first terminal 101 of the timing controller 130”, where in figure 6 the input pulse comes from the left), a second end of the comparator receives a setting signal (col 6 line 29-31 The pulse comparator 133 receives the output pulses PLS2 through the second terminal 102 of the timing controller 130” where in Fig 6 the comparator receives the signal from the right side), and the comparator compares the signal with the setting signal to obtain the detection result (col 6 line 28-29 “The pulse comparator 133 compares the input pulses PLS1 and the output pulses PLS2.”).
Regarding Claim 4, Yu teaches all the limitations of claim 1.
Yu further teaches comprising a first circuit board (col 9 line 41-43 “One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157 (i.e., first circuit board).”), and a second circuit board (col 9 line 44-45 “The timing controller 130, the pulse transmitter 170, and the pulse receiver 180 are formed on a control circuit board 134. (i.e., second circuit board)”); wherein the first circuit board is bonded to the panel (col 9 line 41-43 “One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157 (i.e., first circuit board).” Where the data driver acts as a connection point as it is attached to the panel 160 pads and attached to 157 circuit board), the second circuit board is electrically connected to the panel through the first circuit board, and the detection unit is disposed on the second circuit board (col 9 line 46-47 “The source circuit boards 157 and the control circuit board 134 are connected by second flexible substrates 137.”, and col 9 line 44-45 “The timing controller 130, the pulse transmitter 170, and the pulse receiver 180 (i.e., detection unit) are formed on a control circuit board 134.”)
Regarding Claim 18, Yu teaches the limitation of claim 17.
Yu further teaches the detection unit receives a setting signal (col 6 line 33-34 “The pulse comparator 133 compares the input pulses PLS1 (i.e., setting signal) and the output pulses PLS2,” where to compare the signals the comparator must receive the input (i.e., setting) signal); and the detection unit compares the signal with the setting signal to obtain the detection result (col 6 line 33-40 “The pulse comparator 133 compares the input pulses PLS1 and the output pulses PLS2, and if the input pulses PLS1 and the output pulses PLS2 have the same or similar shape, outputs a logic low ( or logic high) signal. On the other hand, if the input pulses PLS1 and the output pulses PLS2 do not have the same or similar shape ( or there is no signal corresponding to the output pulses), the pulse comparator 133 outputs a logic high (or logic low) signal. (i.e. detection results are same shape or not same shape)”) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 7, 8, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Shin et al. (US 2021/0153343 A1 found on IDS 06/01/2023) hereinafter Shin.
Regarding Claim 5, Yun teaches the limits of claim 1.
Yun further teaches comprising a first circuit board bonded to the panel (col 9 line 41-43 “One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157 (i.e., first circuit board).” Where the data driver acts as a connection point as it is attached to the panel 160 pads and attached to 157 circuit board);
Yun does not teach wherein the panel comprises a first dummy pad, the first circuit board comprises a second dummy pad bonded to the first dummy pad, and the first dummy pad is electrically connected to the detection system through the test loop.
Shin teaches wherein the panel comprises a first dummy pad ([0069] “panel dummy pad.”), the first circuit board comprises a second dummy pad bonded to the first dummy pad ([0085] “In other words, the main test pad TM_PAD may be a dummy electrode and not connected to the main circuit part 550.”, where [0084] “Referring to FIG. 4, the second substrate 500 may include a main circuit pad M_PAD and a main test pad TM_PAD.”), and the first dummy pad is electrically connected to the detection system through the test loop ([0087] “The second substrate 500 may include a first main test line TM_L1 physically connected to the first main test pad TM_PAD1”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the use of dummy pads as described in Shin to the electronic device described in Yu for the purpose of utilizing pads that are not integral to the chips function. This is advantageous because dummy components, which may include dummy pads, are used to calibrate and test pick-and-place assembly machines. Some dummy components also contain a "daisy chain" circuit to test electrical continuity, or a silicon die to simulate the thermal mass and behavior of a live component during reflow soldering.
Regarding Claim 7, Yu teaches the limitations of claim 2.
Yu does not teach wherein the controller outputs an enable signal when the detection result is within the voltage range of the setting signal.
Shin teaches wherein the controller outputs an enable signal when the detection result is within the voltage range of the setting signal ([0102] “The resistance measuring device 700 may provide the input voltage to one of the test points (TPOa: TPO1 to TP03) through the jig 600, and may measure an output voltage from another one of the test points (TPOa: TPO1 to TPO3) through the jig 600. Detailed descriptions will be described with reference to FIGS. 9 to 12.” Where [0126] Accordingly, a data value, for example, a voltage value that should be applied from the driving integrated circuit 350 to the panel pads PAD and the first lead lines LE1, may be inaccurately determined, and when a voltage value with a large error (i.e., determined by range) compared to a normal reference value is applied, a pixel defect may be caused.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine a voltage range as discussed in Shin to the electronic device discussed in Yu for the purpose of having a range of voltages in which a device can operate safely in. This is advantageous because it allows for environmental, material, or power fluctuations of the panel and device to be taken into account when looking into the operational status of a device through the voltage range.
Regarding Claim 8, Yu and Shin teach the limitations of claim 7.
Yu further teaches a power control chip (col 9 line 48-49 “The image processing part 120 and the power supply part 125 are formed on the system board 110.(i.e. power control chip)”) , configured to receive the enable signal and control the driving of the panel according to the enable signal (col 9 line 66- col 10 line 2 “The timing controller 130 is connected to the power supply part 125 via a shutdown signal line 139 extending to the system board 110 through the control circuit board 134 and the third flexible substrate 115.” Where an example is col 10 line 65- col 11 line 1 “the timing controller 130 does not output a shutdown signal for turning off the power supply part through the shutdown signal line 139, if there is no short circuit in the panel 160.”).
Regarding Claim 19, Yu teaches all the limitations of claim 17.
Yu further teaches the detection unit outputs an enable signal to drive the panel when the detection result indicates that the signal is within the range of the setting signal (col 7 line 21-27 “As shown in FIG. 7, if there is no factor causing a short circuit in the panel 160, the input pulses PLS1 and the output pulses PLS2 are received in the same or similar shape (i.e., the range is same to similar). Accordingly, the shutdown signal generator 132 outputs no shutdown signal SDS (i.e., enable signal is sent) through the third terminal 103. At this time, the power supply part maintains the output from the output end Vout, as shown in (a) of FIG. 9 [Normal].”)
Yu does not teach the signal is a voltage.
Shin teaches the signal is a voltage ([0126] Accordingly, a data value, for example, a voltage value that should be applied from the driving integrated circuit 350 to the panel pads PAD and the first lead lines LE1, may be inaccurately determined, and when a voltage value with a large error (i.e., determined by range) compared to a normal reference value is applied, a pixel defect may be caused.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine a voltage as the signal as discussed in Shin to the electronic device discussed in Yu for the purpose of having being able to measure the range of voltages in which a device can operate safely in. This is advantageous because it allows for environmental, material, or power fluctuations of the panel and device to be taken into account when looking into the operational status of a device through the voltage range.
Claim(s) 3 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Im et al (US 2021/0027680 A1).
Regarding Claim 9, Yu teaches a panel (col 2 line 67 “panel 160.”); a detection system (col 5 line 64-66 “As shown in FIG. 6, the timing controller 130 comprises a short circuit detector 135 comprising a pulse generator 131, a pulse comparator 133, and a shutdown signal generator 132 (i.e., a detection system)” and col 7 lines 4-6 “FIGS. 7 to 9 are views for explaining an example of short circuit detection using a pulse transmitter and a pulse receiver that operates in connection with the timing controller (i.e., detection system)”); a test loop, electrically connected to the panel and the detection system (col 2 line 23-27 “FIGS. 7 to 9 are views for explaining an example of short circuit detection (i.e., figures demonstrate a test loop) using a pulse transmitter and a pulse receiver that operates in connection with a timing controller in accordance with a second example embodiment of the present invention;”); wherein the detection system comprises a detection unit and a controller; and the detection unit is configured to detect a signal transmitted by the test loop, and provide a detection result to the controller (col 7 lines 4-6 “FIGS. 7 to 9 are views for explaining an example of short circuit detection using a pulse transmitter and a pulse receiver (i.e., pulse receiver detect pulses so it is a detection unit) that operates in connection with the timing controller” and col 6 line 29-31 “The pulse comparator 133 receives the output pulses PLS2 through the second terminal 102 of the timing controller 130.” And col 6 line 33-34 “The pulse comparator 133 compares the input pulses PLS1 and the output pulses PLS2,”); wherein one end of the test loop is electrically connected to a power-supply voltage (col 4 line 61-62 “That is, the timing controller 130 forms a kind of closed loop with the guide line GR formed on the panel 160 (i.e., test loop)” where col 4 line 6-13 “The power supply part 125 converts external voltages supplied from the outside, and outputs a first potential voltage ( e.g., around 20 V), a second potential voltage ( e.g., around 3.3 V), a low potential voltage (e.g., around OV), etc. The first potential voltage is a drain-level voltage supplied to the first power supply line VDD, the second potential voltage is a collector-level voltage supplied to a second power supply line VCC,”), the other end of the test loop is electrically connected to a fixed voltage (col 4 line 9-14 “a low potential voltage (e.g., around 0V), etc. The first potential voltage is a drain-level voltage supplied to the first power supply line VDD, the second potential voltage is a collector-level voltage supplied to a second power supply line VCC, and the low potential voltage is a base-level voltage supplied to the ground line GND.” Where figure 10 shows the GND being connected in two spots of the loop), the detection unit is electrically connected to a node of the test loop (Fig 10, where the detection unit (170, 130 and 180) are fixed to the nodes TP2 and TP4), and an external resistor is electrically connected between the node and the fixed voltage (col 7 line 47-53 “FIGS. 6 and 10, the pulse transmitter 170 comprises a first resistor Rt and a first transistor Tt. The pulse transmitter 170 serves to transmit the input pulses PLS1 output from the pulse generator 131 connected to the first terminal 101 of the timing controller 130 to the guide line GR. To this end, one end of the first resistor Rt is connected to the second power supply line VCC,”, where the resistors are external to the panel under test).
Yu does not teach a vehicle.
Im teaches a vehicle ([0060] “car navigation units”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine a vehicle as discussed in Im to the electronic device discussed in Yu for the purpose of testing the vehicles screen displays. This is advantageous because to transmit the control signals and the image signals to the display panel without distortion, the pads of the connection board should be sufficiently and completely (substantially) connected to pads of the display panel (e.g., Im, [0005]).
Regarding Claim 3, Yu teaches the limitations of claim 1.
Yu further teaches further comprising a first circuit board (col 9 line 41-43 “One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157 (i.e., first circuit board).”), wherein the first circuit board is bonded to the panel (col 9 line 41-43 “One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157 (i.e., first circuit board).” Where the data driver acts as a connection point as it is attached to the panel 160 pads and attached to 157 circuit board).
Yu does not teach the detection unit is disposed on the first circuit board.
Im teaches and the detection unit is disposed on the first circuit board ([0120] “The driving circuit DIC1 (i.e., detection unit) may output the contact test signal CTS of the active level (e.g., the low level) indicating detection of poor connection when it is determined that at least one of the first to fourth panel pads BP1 to BP4 is insufficiently connected to at least one of the first to fourth connection board pads AP1 to AP4.” Where in Fig 4 the DIC is on the first circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the detection unit disposed a first circuit board to the electronic device discussed in Yu for the purpose of having the test apparatus on a different circuit than the device being tested. This is advantageous because it would allow for the replacement of the panel without replacing the test apparatus should the display be erroneous.
Regarding Claim 10, Yu and Im teach the limitations of claim 9.
Yu further teaches wherein the detection unit comprises a comparator (col 6 line 29 “The pulse comparator 133), a first end of the comparator receives the signal transmitted by the test loop (col 6 line 4-6 “The pulse generator 131 generates input pulses PLS1, and outputs the generated input pulses PLS1 through the first terminal 101 of the timing controller 130”, where in figure 6 the input pulse comes from the left), a second end of the comparator receives a setting signal (col 6 line 29-31 The pulse comparator 133 receives the output pulses PLS2 through the second terminal 102 of the timing controller 130” where in Fig 6 the comparator receives the signal from the right side), and the comparator compares the signal with the setting signal to obtain the detection result (col 6 line 28-29 “The pulse comparator 133 compares the input pulses PLS1 and the output pulses PLS2.”).
Regarding Claim 11, Yu and Im teaches the limitations of claim 9.
Yu further teaches comprising a first circuit board, wherein the first circuit board is bonded to the panel (col 9 line 34-43 “As shown in FIG. 12, a plurality of scan drivers 140 are formed in the non-active area NA on both outer sides of the active area AA of the panel 160. The scan drivers 140 are formed on the panel 160 in a gate-in panel type, along with a subpixel transistor process. A data driver 150 is configured as a plurality of (e.g., four) ICs (Integrated Circuits), and mounted on a plurality of ( e.g., four) first flexible substrates 155. One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157.”).
Yu does not teach the detection unit is disposed on the first circuit board.
Im teaches and the detection unit is disposed on the first circuit board ([0120] “The driving circuit DIC1 (i.e., detection unit) may output the contact test signal CTS of the active level (e.g., the low level) indicating detection of poor connection when it is determined that at least one of the first to fourth panel pads BP1 to BP4 is insufficiently connected to at least one of the first to fourth connection board pads AP1 to AP4.” Where in Fig 4 the DIC is on the first circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the detection unit disposed a first circuit board to the electronic device discussed in Yu for the purpose of having the test apparatus on a different circuit than the device being tested. This is advantageous because it would allow for the replacement of the panel without replacing the test apparatus should the display be erroneous.
Regarding Claim 12, Yu and Im teach the limitations of claim 9.
Yu further teaches comprising a first circuit board (col 9 line 41-43 “One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157 (i.e., first circuit board).”), and a second circuit board (col 9 line 44-45 “The timing controller 130, the pulse transmitter 170, and the pulse receiver 180 are formed on a control circuit board 134. (i.e., second circuit board)”); wherein the first circuit board is bonded to the panel (col 9 line 41-43 “One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157 (i.e., first circuit board).” Where the data driver acts as a connection point as it is attached to the panel 160 pads and attached to 157 circuit board), the second circuit board is electrically connected to the panel through the first circuit board, and the detection unit is disposed on the second circuit board (col 9 line 46-47 “The source circuit boards 157 and the control circuit board 134 are connected by second flexible substrates 137.”, and col 9 line 44-45 “The timing controller 130, the pulse transmitter 170, and the pulse receiver 180 (i.e., detection unit) are formed on a control circuit board 134.”).
Claim(s) 13, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu and Im and further in view of Shin.
Regarding Claim 13, Yu and Im teach all the limitations of claim 9.
Yu further teaches comprising a first circuit board bonded to the panel (col 9 line 41-43 “One end of the data driver 150 is attached to pads of the panel 160, and the other end of the data driver 150 is attached to a plurality of ( e.g., two) source circuit boards 157 (i.e., first circuit board).” Where the data driver acts as a connection point as it is attached to the panel 160 pads and attached to 157 circuit board);
Yun and Im do not teach wherein the panel comprises a first dummy pad, the first circuit board comprises a second dummy pad bonded to the first dummy pad, and the first dummy pad is electrically connected to the detection system through the test loop.
Shin teaches wherein the panel comprises a first dummy pad ([0069] “panel dummy pad.”), the first circuit board comprises a second dummy pad bonded to the first dummy pad ([0085] “In other words, the main test pad TM_PAD may be a dummy electrode and not connected to the main circuit part 550.”, where [0084] “Referring to FIG. 4, the second substrate 500 may include a main circuit pad M_PAD and a main test pad TM_PAD.”), and the first dummy pad is electrically connected to the detection system through the test loop ([0087] “The second substrate 500 may include a first main test line TM_L1 physically connected to the first main test pad TM_PAD1”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the use of dummy pads as described in Shin to the electronic device described in Yu for the purpose of utilizing pads that are not integral to the chips function. This is advantageous because dummy components, which may include dummy pads, are used to calibrate and test pick-and-place assembly machines. Some dummy components also contain a "daisy chain" circuit to test electrical continuity, or a silicon die to simulate the thermal mass and behavior of a live component during reflow soldering.
Regarding Claim 15, Yu and Im teach the limitations of claim 10.
Yu does not teach wherein the controller outputs an enable signal when the detection result is within the voltage range of the setting signal.
Shin teaches wherein the controller outputs an enable signal when the detection result is within the voltage range of the setting signal ([0102] “The resistance measuring device 700 may provide the input voltage to one of the test points (TPOa: TPO1 to TP03) through the jig 600, and may measure an output voltage from another one of the test points (TPOa: TPO1 to TPO3) through the jig 600. Detailed descriptions will be described with reference to FIGS. 9 to 12.” Where [0126] Accordingly, a data value, for example, a voltage value that should be applied from the driving integrated circuit 350 to the panel pads PAD and the first lead lines LE1, may be inaccurately determined, and when a voltage value with a large error (i.e., determined by range) compared to a normal reference value is applied, a pixel defect may be caused.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine a voltage range as discussed in Shin to the electronic device discussed in Yu for the purpose of having a range of voltages in which a device can operate safely in. This is advantageous because it allows for environmental, material, or power fluctuations of the panel and device to be taken into account when looking into the operational status of a device through the voltage range.
Regarding Claim 16, Yu, Im and Shin teach the limitations of claim 15.
Yu further teaches a power control chip (col 9 line 48-49 “The image processing part 120 and the power supply part 125 are formed on the system board 110.(i.e. power control chip)”) , configured to receive the enable signal and control the driving of the panel according to the enable signal (col 9 line 66- col 10 line 2 “The timing controller 130 is connected to the power supply part 125 via a shutdown signal line 139 extending to the system board 110 through the control circuit board 134 and the third flexible substrate 115.” Where an example is col 10 line 65- col 11 line 1 “the timing controller 130 does not output a shutdown signal for turning off the power supply part through the shutdown signal line 139, if there is no short circuit in the panel 160.”).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Kameyama et al. (US 2022/0113357 A1) hereinafter Kameyama.
Regarding Claim 20, Yu teaches the limitations of claim 17.
Shin teaches the detection result indicates that the signal is abnormal (col 7 line 28-35 “As shown in FIG. 8, if there is a factor causing short circuit in the panel 160, there is no signal corresponding to the output pulses PLS2 ( or the input pulse and the output pulse do not 30 have the same or similar shape). Accordingly, the shutdown signal generator 132 outputs a shutdown signal SDS through the third terminal 103 of the timing controller 130. At this time, the power supply part cuts off the output from the output end Vout, as shown in (b) of FIG. 9 [Abnormal].”).
Yu does not teach the voltage data of the signal and the voltage data of the setting signal are stored in a register when the detection result indicates that the signal is abnormal
Kameyama teaches the voltage data of the signal and the voltage data of the setting signal are stored in a register the detection result indicates that the signal is abnormal ([0050] the under lower limit voltage condition setting signal (F2-8), and the over upper limit voltage condition setting signal (F2-9) change to incorrect data due to the abnormal power supply voltage (i.e., signal is abnormal), the setting data latched by the latch (F2-12) in the analog voltage area (F2-3) of CIVFD (F1-2) is retained.” Where [0066] “CIVFD (F12-3) can use the cache memory as a storage area for starting programs, etc., when DRAM is not valid, such as at LSI startup in normal operation. Since the data can be retained even after DRAM is enabled, the processor can switch to the program corresponding to function safety without interruption from the start program.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the storing of the voltages when abnormal as discussed in Kameyama to the electronic device in Yu for the purpose of creating a log that contains errors in the voltage signals. This is advantageous because the log may demonstrate a common factor causing the occurrence e.g., faulty wire, temperature, humidity, testing device, etc.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/EMMA ALEXANDER/Patent Examiner, Art Unit 2863
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2857