DETAILED ACTION
1. This communication is in response to the amendments filed on June 30, 2026 for Application No. 18/327,279 in which Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
3. The amendments filed on June 30, 2026 have been considered. Claims 1, 4, 14-15, and 17 have been amended. Thus, Claims 1-20 are pending and presented for examination.
4. Applicant’s amendments and corresponding arguments filed June 30, 2026 with respect to the objection of Claim 15 have been fully considered and are persuasive. Thus, the claim objection of Claim 15 has been withdrawn.
5. Applicant's amendments and corresponding arguments filed June 30, 2026 with respect to the 35 U.S.C. 103 rejection have been fully considered but they are not persuasive.
Applicant’s Arguments on Pgs. 7-13 of Arguments/Remarks state:
“For example, neither Beidas, Aamir, the remaining references, nor any combination thereof discloses, teaches, or suggests "a membrane circuit comprising a variable resistor element comprising a transistor, the membrane circuit configured to receive a weighted synaptic current from a synaptic array and receive an adaptive current from an adaptive circuit," as recited in independent claim 1.
In the rejection of independent claim 1 at pages 3-7, the Office Action asserts:
[…]
As shown, Kim discloses that the memristor device 100 (e.g., the variable resistance memory devices Ml and M2) includes a resistance change layer 120 that may include a metal oxide material including IGZO.
However, the variable resistance memory devices Ml and M2 do not themselves include a transistor. To the contrary, the transistor T is an additional component of the larger synaptic device 50 including the transistor T and the variable resistance memory devices Ml and M2.
Accordingly, Kim fails to disclose, teach, or suggest "a membrane circuit comprising a variable resistor element comprising a transistor, the membrane circuit configured to receive a weighted synaptic current from a synaptic array and receive an adaptive current from an adaptive circuit," as recited in independent claim 1.
It is further respectfully submitted that neither Beidas, Aamir, the remaining references, nor any combination thereof discloses, teaches, or suggests each and every claimed feature of each of independent claims 14 and 17.
Based at least on the foregoing discussion of the actual disclosure of the references, the rejections pursuant to 35 U.S.C. § 103 of independent claims 1, 14, and 17 are deficient, and Applicant respectfully requests the rejections be withdrawn.”
Examiner respectfully disagrees. Beidas Par. [0056] states:
“The integration block 302 may include a membrane potential storage that is configured to store the membrane potential and a membrane potential adjuster that is configured to adjust the membrane potential. The membrane potential storage and the membrane potential adjuster may include analog electrical circuits in a manner that is similar to a control of an electrical potential over electrical components, such as one or more transistors.”
Thus, the integration block (comprising the adder and membrane potential accumulator, which function analogously to the claimed membrane circuit as supported by Beidas Par. [0058-0060] and further explained in the 35 U.S.C. 103 rejection below) may comprise a variable resistor element, such as one or more transistors – these transistors being responsible for controlling/maintaining electrical potential. Hence, primary reference Beidas teaches the newly added limitations of the Independent claims.
Regarding Applicant’s arguments with respect to the Kim reference of record, Examiner asserts that the Kim reference of record is merely relied upon for its recitation of a variable resistor element comprising one or both of a phase change material (PcRAM) and/or a resistive random access memory (RRAM) per instant claim 5 and its recitation of a variable resistor element comprising an indium-gallium-zinc-oxide (IGZO) transistor per instant claim 6. To clarify, Kim is relied upon to teach the benefits of the variable resistor element being an IGZO transistor, where Beidas in view of Aamir already teach the variable resistor elements/transistors themselves in the rejections of the preceding claims (See, for example, the 35 U.S.C. 103 rejection of Claim 1 and Claim 4). Kim is not applied to teach the newly added limitations of the Independent claims and is only introduced in the rejection of Dependent Claims 5 and 6, consequently rendering Applicant’s arguments regarding the Kim reference on Pgs. 11-12 of the filed Arguments/Remarks moot. The updated 35 U.S.C. 103 rejection, in view of the amendments, may be found in the subsequent section below.
Thus, the 35 U.S.C. 103 rejection is maintained.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
7. Claim 5 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Dependent Claim 5 recites “[…] wherein the variable resistor of the membrane circuit […] comprise either one or both of a phase change material (PCM) and a resistive random access memory (RRAM)” – however, amended Independent Claim 1 states “a membrane circuit comprising a variable resistor element comprising a transistor […]” where the variable resistor element of the membrane circuit is already limited to a transistor element. Applicant is encouraged to amend the claim language of Claim 5 to further limit whether the variable resistor element of the membrane circuit may comprise additional elements as well as the transistor and/or a combination of such elements. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 1-4, 7-8, 11, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Beidas et al. (hereinafter Beidas) (US PG-PUB 20230100670), in view of Aamir et al. (hereinafter Aamir) (“A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores”).
Regarding Claim 1, Beidas teaches a neuron circuit (Beidas, Par. [0103], “FIG. 6 shows schematically an example of a spiking neuron. The spiking neuron may include a neuron circuit suitable for a spiking neural network, as exemplarily provided with respect to FIG. 5.”, thus, a neuron circuit is disclosed. Beidas Figure 7 better illustrates such a neuron circuit) comprising:
a membrane circuit (Beidas, Figure 7, label 704 corresponding to the Adder & label 707 corresponding to the Membrane potential accumulator (part of the integration block as specified by supporting Par. [0058-0060]) which are analogous and used in combination to teach the functions of the membrane circuit, as further described below) comprising a variable resistor element comprising a transistor (Beidas, Par. [0056], “The integration block 302 may include a membrane potential storage that is configured to store the membrane potential and a membrane potential adjuster that is configured to adjust the membrane potential. The membrane potential storage and the membrane potential adjuster may include analog electrical circuits in a manner that is similar to a control of an electrical potential over electrical components, such as one or more transistors.”, therefore, the membrane circuit (integration block comprising adder & membrane potential accumulator) may comprise a variable resistor element comprising a transistor), the membrane circuit configured to receive a weighted synaptic current from a synaptic array and receive an adaptive current from an adaptive circuit (Beidas, Par. [0118], “The membrane potential accumulator 640 may be configured to adjust the integration value based on the information which the membrane potential accumulator 640 receives from the adder 630. The membrane potential accumulator 640 may receive information indicating the sum of weights which the weight releasing elements 621, 622, 623 provide based on the trigger signal. The membrane potential accumulator 640 may be configured to add the received sum of weights to the integration value to perform the accumulation. The membrane potential accumulator 640 may be configured to perform the accumulation after an instance of time which the pulse trigger 680 triggers the weight releasing elements 621, 622, 623. For example, the weight releasing elements 621, 622, 623 may be configured to provide weights to the adder 630 with a positive transition of the trigger signal (e.g. when the pulse signal changes from a low signal to a high (0 to 1) signal, and the membrane potential accumulator 640 may be configured to perform the accumulation with a negative transition of the trigger signal (e.g. when the generated pulse changes from the high signal to a low signal).”, thus, the membrane circuit (comprising the adder & membrane potential accumulator) may receive a weighted synaptic current (See Beidas Par. [0047] which further details the synaptic weight block) and an adaptive current (fluctuating generated low and high signal pulses) from the adaptive circuit (shown by the relationship in Figure 7 between the membrane accumulator label 707 and the subsequent parts of the adaptive circuit which comprises a combination of the leakage accumulator label 708/oscillator label 706/oscillator activator label 705, as further described below));
a comparator circuit (Beidas, Par. [0140], “Furthermore, the neuron circuit may include a spike generation circuit 717 including a comparator to determine to activate or deactivate the oscillator 706 based on the integration value and a predefined membrane potential threshold value.”, thus, the spike generation circuit (analogous to the pulse generation circuit) includes a comparator – shown by label 717 in Figure 7) configured to control a pulse generation circuit in response to a voltage of the membrane circuit exceeding a predetermined threshold voltage (Beidas, Par. [0140], “Furthermore, the neuron circuit may include a spike generation circuit 717 including a comparator to determine to activate or deactivate the oscillator 706 based on the integration value and a predefined membrane potential threshold value. The comparator of the spike generation circuit 717 may determine to deactivate the oscillator 706 based on the integration value and the predefined membrane potential threshold value. The comparator may determine to deactivate the oscillator 706 if the integration value is greater than (or equal to) the predefined membrane potential threshold value.”, therefore, the comparator circuit of the spike/pule generation circuit is configured to control the spike/pulse generation circuit in response to a voltage of a membrane circuit exceeding a predetermined threshold);
the pulse generation circuit (Beidas, Figure 7, label 717 corresponding to the spike generation circuit and label 718 corresponding to the OR logic, which are analogous and used in combination to teach the functions of the pulse generation circuit, as further described below) configured to control the membrane circuit and the adaptive circuit based on an output signal from the comparator circuit and generate a pulse comprising a firing pattern (Beidas, Par. [0141], “An OR logic 718 may be coupled to a reset output of the comparator 714 and an output of the spike generation circuit 717 to receive reset signals and provide a reset signal from its output to provide an indication of a reset operation to the components of the neuron circuit. In response to a received reset signal, the membrane potential accumulator 707 may reset the integration value to the predefined membrane resting potential value, and/or the leakage accumulator 708 may reset the leakage value to the predefined initial leakage value. Furthermore, in response to the received reset signal, the oscillator activator 705 may deactivate the oscillator 706. The neuron circuit may include a delay circuit to provide a delay for a period of time between the respective determinations from the comparators and the generation of the reset signal. Alternatively, a delay circuit may receive the reset signal to introduce a predefined delay for a refractory period.”, thus, the spike/pulse generation circuit is configured to control the membrane circuit (membrane potential accumulator) and the adaptive circuit (comprising the leakage accumulator/oscillator/activator) based on an output signal from the comparator circuit within the spike generation circuit (See Par. [0140] for support) and generate a pulse comprising a firing pattern (transmitting signals/resetting signals/delaying signals/etc.)); and
the adaptive circuit (While Beidas discloses components that function analogously to the “adaptive circuit” as shown below, Beidas does not explicitly disclose an “adaptive circuit” – See introduction of Aamir reference below for explicit teaching of an “adaptive circuit”) connected to the membrane circuit and the pulse generation circuit (Beidas, Figure 7, label 708 corresponding to the Leakage accumulator, label 706 corresponding to the Oscillator, and label 705 corresponding to the Oscillator activator, which are analogous and used in combination to teach the functions of the adaptive circuit, as further described below. Moreover, using the broadest reasonable interpretation of the term “connected to”, the leakage accumulator (label 708), oscillator (label 706), and oscillator activator (label 705) comprising the adaptive circuit are connected to the membrane circuit (membrane potential accumulator label 707) and spike/pulse generation circuit (label 717) as depicted by Figure 7, as these components are coupled to a synchronizer (label 713) which provides synchronized trigger signals to the aforementioned components and the circuit itself), and configured to determine the firing pattern of the pulse generation circuit (Beidas, Par. [0129-0130], “The oscillator 706 may further include a frequency control input 711 that is configured to receive an indication to control the frequency of the oscillator signal which the oscillator 706 generates. The frequency of the oscillator 706 may be defined according to a desired leakage response during the design of the neural network. The oscillator 706 may further include a disable input 712 to receive an indication to disable the oscillator 706. When the oscillator activator 705 receives a reset signal, the oscillator activator 705 may deactivate the oscillator 706. The oscillator activator 705 may further include a controller to control the frequency of the oscillator signal. The controller may provide a control signal to the frequency control input of the oscillator 706 to adjust the frequency of the oscillator signal”, therefore, the adaptive circuit (comprising the leakage accumulator/oscillator/oscillator activator) may determine the firing pattern of the spike/pulse generation circuit, as the oscillator controls the frequency of the signal which it generates – hence, impacting the firing pattern of the spike/pulse generation circuit, based on membrane potential).
Although Beidas discloses the use of a leakage accumulator, oscillator, and oscillator activator which function analogously to the adaptive circuit as shown by the claim mapping above, Beidas does not explicitly teach an “adaptive circuit”
However, Aamir teaches such an adaptive circuit (Aamir, Pg. 4, Section IV. Circuit Implementation, “The adaptation circuit implements accelerating and decelerating spike-triggered adaptation as well as adaptation current given by Eq. (3) and (4). A simplified circuit schematic is shown in Fig. 2(b). The circuit has been inspired from our first-generation design presented in [38].”, thus, an adaptation/adaptive circuit which generates adaptive currents is disclosed)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit, as disclosed by Beidas to include an adaptive circuit, as disclosed by Aamir. One of ordinary skill in the art would have been motivated to make this modification to mimic biological neurons through dynamic adaptation of spike generation and thresholds, in order to produce a diverse set of firing patterns, hence improving system processing efficiency and reducing hardware constraints (Aamir, Pg. 1, Section I. Introduction, “The implemented neuron model is designed for integration in the second-generation BrainScaleS 65 nm physical model platform [35], operated (“accelerated” to) 1000 times faster than biological real-time. The presented analog continuous-time neuron in this work is measured on a 65 nm prototype chip that implements a scaled-down array of 32 neurons, connected to 32 × 32 synapses.” & Pg. 8, Section VI. Discussion, “For point-neuron model enhancement, we integrated adaptation and exponential circuit to the modular LIF neuron architecture. The AdEx enhancement let us qualitatively reproduce exponential spikes, and diverse spiking and bursting regimes. Using a floating tunable resistor we can tune very long adaptation time constants.”).
Regarding Claim 2, Beidas in view of Aamir teaches the neuron circuit of claim 1, wherein the adaptive circuit is configured to transmit an adaptive current to the membrane circuit based on an adaptation time constant parameter (Aamir, Pg. 4, Section IV. Circuit Implementation, “The voltage on the capacitor Vw emulates the adaptation variable in the model. The presence of a tunable conductance implements adaptation time constant τw = RwCw, where Rw = 1 gw .”, therefore, the adaptive circuit is configured to transmit an adaptive current based on an adaptation time constant parameter), a subthreshold adaptation conductor parameter (Aamir, Pg. 4, Section IV. Circuit Implementation, “The top right part of the circuit implements Eq. (3), where the output current w generated by the OTA with conductance ga emulates the model’s subthreshold conductance parameter a. It senses the difference between Vleak and Vw at its inputs and switches them with a configuration bit enVa to realize negative ga. The OTA is a source-degenerated architecture identical to the one used in the leak term. (for details, see [32]).”, therefore, a subthreshold adaptation conductor parameter is also used to transmit the adaptive current), and a spike-triggered adaptation current parameter of the adaptive circuit (Aamir, Pg. 6, Section V. Experimental Results, “The accelerating and decelerating spike-triggered adaptation realized by the integration of adaptation circuit is shown in Fig. 5. The adaptation voltage Vw grows from 0.6 V and increments approx 0.1 V with every spike evoked– resulting in decelerating adaptation (Fig. 5(a) and Fig. 5(b)).”, thus, a spike-triggered adaptation current parameter is also used to transmit the adaptive current) and determine the firing pattern (Aamir, Pg. 6, Section V. Experimental Results, “Being a two-variable neuron model, the AdEx circuit repro duces a diverse set of firing patterns [48] known from biological neurons [49], and typically characterized by the response to a step current stimulus. Fig. 6 shows a set of example firing patterns from the designed circuit. Fig. 6(a)–(f) show the adaptation, transient spiking, delayed accelerating, initial bursting, tonic spiking as well as regular bursting”, therefore, the firing pattern is determined based on the one or more parameters related to the adaptive circuit).
The reasons of obviousness have been noted in the rejection of Claim 1 above and applicable herein.
Regarding Claim 3, Beidas in view of Aamir teaches the neuron circuit of claim 1, wherein the membrane circuit is configured to receive the adaptive current from the adaptive circuit based on an adaptation time constant parameter of the membrane circuit (Aamir, Pg. 4, Section IV. Circuit Implementation, “The voltage on the capacitor Vw emulates the adaptation variable in the model. The presence of a tunable conductance implements adaptation time constant τw = RwCw, where Rw = 1 gw .”, therefore, the neuron (membrane) circuit is configured to receive an adaptive current based on an adaptation time constant parameter – better depicted by Figure 2 on Pg. 3) and a reset voltage parameter of the membrane circuit (Aamir, Pg. 2, Section II. Neuron Model, “The neuron circuit adheres to the AdEx point-neuron model. However it replaces a fixed reset with a conductance-based reset. The evolution of the neuron membrane in the AdEx model is described by a two-variable equation [9] given by”, therefore, the adaptive circuit is configured to receive an adaptive current based on a reset voltage parameter of the membrane circuit (neuron membrane)) and determine the firing pattern (Aamir, Pg. 6, Section V. Experimental Results, “Being a two-variable neuron model, the AdEx circuit repro duces a diverse set of firing patterns [48] known from biological neurons [49], and typically characterized by the response to a step current stimulus. Fig. 6 shows a set of example firing patterns from the designed circuit. Fig. 6(a)–(f) show the adap tation, transient spiking, delayed accelerating, initial bursting, tonic spiking as well as regular bursting”, therefore, the firing pattern is determined based on the one or more parameters related to the adaptive circuit).
The reasons of obviousness have been noted in the rejection of Claim 1 above and applicable herein.
Regarding Claim 4, Beidas in view of Aamir teaches the neuron circuit of claim 1, wherein the membrane circuit and the adaptive circuit each comprise a capacitor element (Aamir, Pg. 3, Figure 2 which depicts the (a) synapse column of the neuron circuit (membrane circuit) comprising a variable resistor Rsyn for synaptic input (handled by the membrane circuit) and a capacitor Cmem) and the adaptive circuit comprises another variable resistor element (Aamir, Pg. 3, Figure 2 which depicts the (b) adaptation circuit comprising a tunable/variable resistor gw (further detailed by diagram (d) tunable resistor) and a capacitor element Cw).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit of claim 1, as disclosed by Beidas in view of Aamir to include wherein the membrane circuit and the adaptive circuit each comprise a capacitor element and the adaptive circuit comprises another variable resistor element, as disclosed by Aamir. One of ordinary skill in the art would have been motivated to make this modification to enable the use of a variable resistor and capacitor to mimic the function of biological neurons, by emulating the adaptation variable in order to form a time constant which dictates how frequently the circuits respond to inputs (Aamir, Pg. 4, Section IV. Circuit Implementation, “The voltage on the capacitor Vw emulates the adaptation variable in the model. The presence of a tunable conductance implements adaptation time constant τw = RwCw, where Rw = 1 gw .”).
Regarding Claim 7, Beidas in view of Aamir teaches the neuron circuit of claim 1, wherein the pulse generation circuit is configured to perform an operation of controlling the membrane circuit by changing a voltage of the membrane circuit to a reset voltage based on a feedback spike (Beidas, Par. [0141], “An OR logic 718 may be coupled to a reset output of the comparator 714 and an output of the spike generation circuit 717 to receive reset signals and provide a reset signal from its output to provide an indication of a reset operation to the components of the neuron circuit. In response to a received reset signal, the membrane potential accumulator 707 may reset the integration value to the predefined membrane resting potential value, and/or the leakage accumulator 708 may reset the leakage value to the predefined initial leakage value.”, thus, the pulse generation circuit (comprising the spike generation circuit and OR logic) may control the membrane potential accumulator by changing a voltage of the membrane potential accumulator to a reset voltage based on a feedback spike).
Regarding Claim 8, Beidas in view of Aamir teaches the neuron circuit of claim 1, wherein the pulse generation circuit is configured to perform an operation of controlling the adaptive circuit by charging an adaptive capacitor comprised in the adaptive circuit based on a feedback spike (Aamir, Pg. 4, Section IV. Circuit Implementation, “The circuit is triggered by the input event fireadapt, whose presence indicates a digital spike event. The pulse-width of fireadapt is variable and an equivalent charge q = Iw · tpulse is integrated (or removed) with every input event from the capacitor Cw.The configuration bit enVw controls whether tosourceorsinkcurrent Iw, essentially implementing either decelerating or accelerating output spiking response. The charge pump therefore models the spike-triggered adaptation in terms of integrated voltage, since every output event updates Vw → Vw ± ΔVw.”, thus, the pulse generation circuit (which produces digital spike/pulse events) is configured to perform an operation of controlling the adaptive circuit by charging an adaptive capacitor comprised in the adaptive circuit based on a feedback spike).
The reasons of obviousness have been noted in the rejection of Claims 1 and 4 above and applicable herein.
Regarding Claim 11, Beidas in view of Aamir teaches the neuron circuit of claim 1, wherein the pulse generation circuit corresponds to a digital pulse generation circuit (Beidas, Par. [0028], “The artificial neuron may include various components, such as electronic circuits to provide operations mentioned in this disclosure. The electronic circuits may include analog circuits or digital circuits.”, thus, the pulse generation circuit, which is an electronic circuit that is part of the neuron circuit, may correspond to a digital pulse generation circuit. Further, it must be noted that per the rejection of Independent claim 1, both the “spike generation circuit” and “OR logic” of Beidas are considered to be analogous to the instant pulse generation circuit – thus, this combination also corresponds to a digital pulse generation circuit (no specialized hardware, simply involves the use of logic gates)).
Regarding Claim 14, Beidas teaches a processor-implemented method with neuron circuit control (Beidas, Abstract, “Spiking neuron circuits and methods are provided in this disclosure.”, thus, a processor-implemented (See Figure 13 label 1301 depicting one or more processors) method with neuron circuit control is disclosed), the method comprising:
receiving one or more parameter values determining a firing pattern based on a membrane circuit and an adaptive circuit (While Beidas discloses components that function analogously to the “adaptive circuit” as shown below, Beidas does not explicitly disclose an “adaptive circuit” – See introduction of Aamir reference below for explicit teaching of an “adaptive circuit”) comprised in a neuron circuit (Beidas, Par. [0141], “An OR logic 718 may be coupled to a reset output of the comparator 714 and an output of the spike generation circuit 717 to receive reset signals and provide a reset signal from its output to provide an indication of a reset operation to the components of the neuron circuit. In response to a received reset signal, the membrane potential accumulator 707 may reset the integration value to the predefined membrane resting potential value, and/or the leakage accumulator 708 may reset the leakage value to the predefined initial leakage value. Furthermore, in response to the received reset signal, the oscillator activator 705 may deactivate the oscillator 706. The neuron circuit may include a delay circuit to provide a delay for a period of time between the respective determinations from the comparators and the generation of the reset signal. Alternatively, a delay circuit may receive the reset signal to introduce a predefined delay for a refractory period.”, thus, one or more parameter values determining a firing pattern (integration value, membrane resting potential value, reset signal, delay, refractory period, etc.) based on a membrane circuit (adder & membrane potential accumulator, label 704 & label 707 of Figure 7 which are part of the integration block as specified by supporting Par. [0058-0060]) and an adaptive circuit (leakage accumulator & oscillator & oscillator activator, label 708 & label 706 & label 705 of Figure 7) comprising a neuron circuit (See Beidas Figure 7) are received), the membrane circuit comprising a variable resistor element comprising a transistor (Beidas, Par. [0056], “The integration block 302 may include a membrane potential storage that is configured to store the membrane potential and a membrane potential adjuster that is configured to adjust the membrane potential. The membrane potential storage and the membrane potential adjuster may include analog electrical circuits in a manner that is similar to a control of an electrical potential over electrical components, such as one or more transistors.”, therefore, the membrane circuit (integration block comprising adder & membrane potential accumulator) may comprise a variable resistor element comprising a transistor); and
outputting a voltage comprising a spiking firing pattern based on the received one or more parameter values (Beidas, Par. [0140-0141], “Furthermore, based on the determination, the spike generation circuit 717 may generate an output spike to be transmitted to post-synaptic neurons. An OR logic 718 may be coupled to a reset output of the comparator 714 and an output of the spike generation circuit 717 to receive reset signals and provide a reset signal from its output to provide an indication of a reset operation to the components of the neuron circuit.”, thus, a voltage/output spike comprising a spiking firing pattern based on the received one or more parameter values (integration value, membrane resting potential value, reset signal, delay, refractory period, etc. as described above) is outputted).
Although Beidas discloses the use of a leakage accumulator, oscillator, and oscillator activator which function analogously to the adaptive circuit as shown by the claim mapping above, Beidas does not explicitly teach an “adaptive circuit”
However, Aamir teaches such an adaptive circuit (Aamir, Pg. 4, Section IV. Circuit Implementation, “The adaptation circuit implements accelerating and decelerating spike-triggered adaptation as well as adaptation current given by Eq. (3) and (4). A simplified circuit schematic is shown in Fig. 2(b). The circuit has been inspired from our first-generation design presented in [38].”, thus, an adaptation/adaptive circuit which generates adaptive currents is disclosed)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the processor-implemented method with neuron circuit control of claim 14, as disclosed by Beidas to include an adaptive circuit, as disclosed by Aamir. One of ordinary skill in the art would have been motivated to make this modification to mimic biological neurons through dynamic adaptation of spike generation and thresholds, in order to produce a diverse set of firing patterns, hence improving system processing efficiency and reducing hardware constraints (Aamir, Pg. 1, Section I. Introduction, “The implemented neuron model is designed for integration in the second-generation BrainScaleS 65 nm physical model platform [35], operated (“accelerated” to) 1000 times faster than biological real-time. The presented analog continuous-time neuron in this work is measured on a 65 nm prototype chip that implements a scaled-down array of 32 neurons, connected to 32 × 32 synapses.” & Pg. 8, Section VI. Discussion, “For point-neuron model enhancement, we integrated adaptation and exponential circuit to the modular LIF neuron architecture. The AdEx enhancement let us qualitatively reproduce exponential spikes, and diverse spiking and bursting regimes. Using a floating tunable resistor we can tune very long adaptation time constants.”).
Regarding Claim 15, Beidas in view of Aamir teaches the method of claim 14, wherein the one or more parameter values comprise any one or any combination of any two or more of an adaptation time constant parameter of the adaptive circuit (Aamir, Pg. 4, Section IV. Circuit Implementation, “The voltage on the capacitor Vw emulates the adaptation variable in the model. The presence of a tunable conductance implements adaptation time constant τw = RwCw, where Rw = 1 gw .”, therefore, the adaptive circuit is configured to transmit an adaptive current based on an adaptation time constant parameter), a reset voltage parameter of the membrane circuit, a subthreshold adaptation conductor parameter parameter (Aamir, Pg. 4, Section IV. Circuit Implementation, “The top right part of the circuit implements Eq. (3), where the output current w generated by the OTA with conductance ga emulates the model’s subthreshold conductance parameter a. It senses the difference between Vleak and Vw at its inputs and switches them with a configuration bit enVa to realize negative ga. The OTA is a source-degenerated architecture identical to the one used in the leak term. (for details, see [32]).”, therefore, a subthreshold adaptation conductor parameter is also used to transmit the adaptive current), and a spike-triggered adaptation current parameter of the adaptive circuit (Aamir, Pg. 6, Section V. Experimental Results, “The accelerating and decelerating spike-triggered adaptation realized by the integration of adaptation circuit is shown in Fig. 5. The adaptation voltage Vw grows from 0.6 V and increments approx 0.1 V with every spike evoked– resulting in decelerating adaptation (Fig. 5(a) and Fig. 5(b)).”, thus, a spike-triggered adaptation current parameter is also used to transmit the adaptive current) and determine the firing pattern (Aamir, Pg. 6, Section V. Experimental Results, “Being a two-variable neuron model, the AdEx circuit repro duces a diverse set of firing patterns [48] known from biological neurons [49], and typically characterized by the response to a step current stimulus. Fig. 6 shows a set of example firing patterns from the designed circuit. Fig. 6(a)–(f) show the adap tation, transient spiking, delayed accelerating, initial bursting, tonic spiking as well as regular bursting”, therefore, the firing pattern is determined based on the one or more parameters related to the adaptive circuit).
The reasons of obviousness have been noted in the rejection of Claim 14 above and applicable herein.
Regarding Claim 16, Beidas in view of Aamir teaches a non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors, configure the one or more processors (Beidas, Par. [0217], “In an example, a non-transitory computer-readable medium may store instructions that may be executed by a processor, to cause the processor to perform the method.”, thus, a non-transitory computer-readable storage medium storing instructions is disclosed that, when executed by one or more processors, configure the one or more processors to perform the disclosed methods) to perform the method of claim 14 (See the rejection of Claim 14 above which recites substantially the same limitations and rejected under the same rationale).
The reasons of obviousness have been noted in the rejection of Claim 14 above and applicable herein.
Regarding Claim 17, Beidas teaches a neuron circuit (Beidas, Par. [0103], “FIG. 6 shows schematically an example of a spiking neuron. The spiking neuron may include a neuron circuit suitable for a spiking neural network, as exemplarily provided with respect to FIG. 5.”, thus, a neuron circuit is disclosed. Beidas Figure 7 better illustrates such a neuron circuit) comprising:
a membrane circuit (Beidas, Figure 7, label 704 corresponding to the Adder & label 707 corresponding to the Membrane potential accumulator (part of the integration block as specified by supporting Par. [0058-0060]) which are analogous and used in combination to teach the functions of the membrane circuit, as further described below) comprising a variable resistor element comprising a transistor (Beidas, Par. [0056], “The integration block 302 may include a membrane potential storage that is configured to store the membrane potential and a membrane potential adjuster that is configured to adjust the membrane potential. The membrane potential storage and the membrane potential adjuster may include analog electrical circuits in a manner that is similar to a control of an electrical potential over electrical components, such as one or more transistors.”, therefore, the membrane circuit (integration block comprising adder & membrane potential accumulator) may comprise a variable resistor element comprising a transistor), the membrane circuit configured to receive a weighted synaptic current from a synaptic array and receive an adaptive current from an adaptive circuit (Beidas, Par. [0118], “The membrane potential accumulator 640 may be configured to adjust the integration value based on the information which the membrane potential accumulator 640 receives from the adder 630. The membrane potential accumulator 640 may receive information indicating the sum of weights which the weight releasing elements 621, 622, 623 provide based on the trigger signal. The membrane potential accumulator 640 may be configured to add the received sum of weights to the integration value to perform the accumulation. The membrane potential accumulator 640 may be configured to perform the accumulation after an instance of time which the pulse trigger 680 triggers the weight releasing elements 621, 622, 623. For example, the weight releasing elements 621, 622, 623 may be configured to provide weights to the adder 630 with a positive transition of the trigger signal (e.g. when the pulse signal changes from a low signal to a high (0 to 1) signal, and the membrane potential accumulator 640 may be configured to perform the accumulation with a negative transition of the trigger signal (e.g. when the generated pulse changes from the high signal to a low signal).”, thus, the membrane circuit (comprising the adder & membrane potential accumulator) may receive a weighted synaptic current (See Beidas Par. [0047] which further details the synaptic weight block) and an adaptive current (fluctuating generated low and high signal pulses) from the adaptive circuit (shown by the relationship in Figure 7 between the membrane accumulator label 707 and the subsequent parts of the adaptive circuit which comprises a combination of the leakage accumulator label 708/oscillator label 706/oscillator activator label 705, as further described below));
a pulse generation circuit (Beidas, Figure 7, label 717 corresponding to the spike generation circuit and label 718 corresponding to the OR logic, which are analogous and used in combination to teach the functions of the pulse generation circuit, as further described below) configured to control the membrane circuit and the adaptive circuit and generate a pulse comprising a firing pattern (Beidas, Par. [0141], “An OR logic 718 may be coupled to a reset output of the comparator 714 and an output of the spike generation circuit 717 to receive reset signals and provide a reset signal from its output to provide an indication of a reset operation to the components of the neuron circuit. In response to a received reset signal, the membrane potential accumulator 707 may reset the integration value to the predefined membrane resting potential value, and/or the leakage accumulator 708 may reset the leakage value to the predefined initial leakage value. Furthermore, in response to the received reset signal, the oscillator activator 705 may deactivate the oscillator 706. The neuron circuit may include a delay circuit to provide a delay for a period of time between the respective determinations from the comparators and the generation of the reset signal. Alternatively, a delay circuit may receive the reset signal to introduce a predefined delay for a refractory period.”, thus, the spike/pulse generation circuit is configured to control the membrane circuit (membrane potential accumulator) and the adaptive circuit (comprising the leakage accumulator/oscillator/activator) based on an output signal from the comparator circuit within the spike generation circuit (See Par. [0140] for support) and generate a pulse comprising a firing pattern (transmitting signals/resetting signals/delaying signals/etc.)); and
the adaptive circuit comprising another variable resistor element (While Beidas discloses components that function analogously to the “adaptive circuit” as shown below, Beidas does not explicitly disclose an “adaptive circuit” – See introduction of Aamir reference below for explicit teaching of an “adaptive circuit” comprising another variable resistor element), connected to the membrane circuit and the pulse generation circuit (Beidas, Figure 7, label 708 corresponding to the Leakage accumulator, label 706 corresponding to the Oscillator, and label 705 corresponding to the Oscillator activator, which are analogous and used in combination to teach the functions of the adaptive circuit, as further described below. Moreover, using the broadest reasonable interpretation of the term “connected to”, the leakage accumulator (label 708), oscillator (label 706), and oscillator activator (label 705) comprising the adaptive circuit are connected to the membrane circuit (membrane potential accumulator label 707) and spike/pulse generation circuit (label 717) as depicted by Figure 7, as these components are coupled to a synchronizer (label 713) which provides synchronized trigger signals to the aforementioned components and the circuit itself), and configured to determine the firing pattern of the pulse generation circuit (Beidas, Par. [0129-0130], “The oscillator 706 may further include a frequency control input 711 that is configured to receive an indication to control the frequency of the oscillator signal which the oscillator 706 generates. The frequency of the oscillator 706 may be defined according to a desired leakage response during the design of the neural network. The oscillator 706 may further include a disable input 712 to receive an indication to disable the oscillator 706. When the oscillator activator 705 receives a reset signal, the oscillator activator 705 may deactivate the oscillator 706. The oscillator activator 705 may further include a controller to control the frequency of the oscillator signal. The controller may provide a control signal to the frequency control input of the oscillator 706 to adjust the frequency of the oscillator signal”, therefore, the adaptive circuit (comprising the leakage accumulator/oscillator/oscillator activator) may determine the firing pattern of the spike/pulse generation circuit, as the oscillator controls the frequency of the signal which it generates – hence, impacting the firing pattern of the spike/pulse generation circuit, based on membrane potential).
Although Beidas discloses the use of a leakage accumulator, oscillator, and oscillator activator which function analogously to the adaptive circuit as shown by the claim mapping above, Beidas does not explicitly teach an “adaptive circuit” comprising another variable resistor element
However, Aamir teaches such an adaptive circuit (Aamir, Pg. 4, Section IV. Circuit Implementation, “The adaptation circuit implements accelerating and decelerating spike-triggered adaptation as well as adaptation current given by Eq. (3) and (4). A simplified circuit schematic is shown in Fig. 2(b). The circuit has been inspired from our f irst-generation design presented in [38].”, thus, an adaptation/adaptive circuit which generates adaptive currents is disclosed) comprising another variable resistor element (Aamir, Pg. 3, Figure 2 which depicts the (b) adaptation circuit comprising a tunable/variable resistor gw (further detailed by diagram (d) tunable resistor). Note: The reasons of obviousness regarding the disclosure of another variable resistor element are also noted by the preceding motivation to combine Beidas and Aamir above).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit, as disclosed by Beidas to include an adaptive circuit comprising another variable resistor element, as disclosed by Aamir. One of ordinary skill in the art would have been motivated to make this modification to mimic biological neurons through dynamic adaptation of spike generation and thresholds, in order to produce a diverse set of firing patterns, hence improving system processing efficiency and reducing hardware constraints (Aamir, Pg. 1, Section I. Introduction, “The implemented neuron model is designed for integration in the second-generation BrainScaleS 65 nm physical model platform [35], operated (“accelerated” to) 1000 times faster than biological real-time. The presented analog continuous-time neuron in this work is measured on a 65 nm prototype chip that implements a scaled-down array of 32 neurons, connected to 32 × 32 synapses.” & Pg. 8, Section VI. Discussion, “For point-neuron model enhancement, we integrated adaptation and exponential circuit to the modular LIF neuron architecture. The AdEx enhancement let us qualitatively reproduce exponential spikes, and diverse spiking and bursting regimes. Using a floating tunable resistor we can tune very long adaptation time constants.”).
Regarding Claim 18, Beidas in view of Aamir teaches the neuron circuit of claim 17, further comprising a comparator circuit (Beidas, Par. [0140], “Furthermore, the neuron circuit may include a spike generation circuit 717 including a comparator to determine to activate or deactivate the oscillator 706 based on the integration value and a predefined membrane potential threshold value.”, thus, the spike generation circuit (analogous to the pulse generation circuit) includes a comparator – shown by label 717 in Figure 7) configured to control the pulse generation circuit in response to a voltage of the membrane circuit exceeding a predetermined threshold voltage (Beidas, Par. [0140], “Furthermore, the neuron circuit may include a spike generation circuit 717 including a comparator to determine to activate or deactivate the oscillator 706 based on the integration value and a predefined membrane potential threshold value. The comparator of the spike generation circuit 717 may determine to deactivate the oscillator 706 based on the integration value and the predefined membrane potential threshold value. The comparator may determine to deactivate the oscillator 706 if the integration value is greater than (or equal to) the predefined membrane potential threshold value.”, therefore, the comparator circuit of the spike/pule generation circuit is configured to control the spike/pulse generation circuit in response to a voltage of a membrane circuit exceeding a predetermined threshold).
Regarding Claim 19, Beidas in view of Aamir teaches the neuron circuit of claim 17, wherein the adaptive circuit is configured to adjust the other variable resistor element based on one or more parameters of a neuron model (Aamir, Pg. 4, Section IV. Circuit Implementation, “The voltage on the capacitor Vw emulates the adaptation variable in the model. The presence of a tunable conductance implements adaptation time constant τw = RwCw, where Rw = 1 gw .”, thus, the adaptive circuit is configured to adjust the variable resistor element (tunable resistor) based on one or more parameters of the neuron model (adaptation time constant, for example)).
The reasons of obviousness have been noted in the rejection of Claim 17 above and applicable herein.
Regarding Claim 20, Beidas in view of Aamir teaches the neuron circuit of claim 17, wherein the membrane circuit is configured to adjust the variable resistor element based on one or more parameters of a neuron model (Beidas, Par. [0056], “The integration block 302 may include a membrane potential storage that is configured to store the membrane potential and a membrane potential adjuster that is configured to adjust the membrane potential. The membrane potential storage and the membrane potential adjuster may include analog electrical circuits in a manner that is similar to a control of an electrical potential over electrical components, such as one or more transistors.”, thus, the membrane circuit (part of integration block) is configured to adjust the variable resistor element (transistor) based on one or more parameters of a neuron model)
10. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Beidas et al. (hereinafter Beidas) (US PG-PUB 20230100670), in view of Aamir et al. (hereinafter Aamir) (“A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores”), further in view of Kim et al. (hereinafter Kim) (US PG-PUB 20220068379).
Regarding Claim 5, Beidas in view of Aamir teaches the neuron circuit of claim 4.
Beidas in view of Aamir does not explicitly disclose wherein the variable resistor of the membrane circuit and the variable resistor element of the adaptive circuit each comprise either one or both of a phase change material (PCM) and resistive random access memory (RRAM).
However, Kim teaches wherein the variable resistor of the membrane circuit and the variable resistor element of the adaptive circuit each comprise either one or both of a phase change material (PCM) and resistive random access memory (RRAM) (Kim, Par. [0021], “The variable resistance memory device may include any one of a memristor, a resistive random access memory (RRAM), a phase-change random access memory (PcRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FeRAM) and a conductive bridging random access memory (CBRAM).”, thus, the variable resistor may comprise either one or both of a phase change material (PcRAM) and a resistive random access memory (RRAM)).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit of claim 4, as disclosed by Beidas in view of Aamir to include wherein the variable resistor of the membrane circuit and the variable resistor element of the adaptive circuit each comprise either one or both of a phase change material (PCM) and resistive random access memory (RRAM), as disclosed by Kim. One of ordinary skill in the art would have been motivated to make this modification to enable the maintenance of resistance according to historical signals utilizing a variable resistor element such as a PcRAM or RRAM, hence automating adaptation/tuning and likewise improving performance and reducing power consumption (Kim, Par. [0074], “ For example, the variable resistance memory devices M1 and M2 may include any one or more of a memristor, a resistive random access memory (RRAM), a phase-change random access memory (PcRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FeRAM) and a conductive bridging random access memory (CBRAM), but is not limited thereto. Such variable resistance memory devices M1 and M2 have a characteristic of maintaining resistance according to the history of a previously inputted memory signal in the SET or RESET mode. The information on the maintained resistance may be derived when a memory signal in the reading mode is applied.”).
Regarding Claim 6, Beidas in view of Aamir teaches the neuron circuit of claim 4.
Beidas in view of Aamir does not explicitly disclose wherein the variable resistor element of the membrane circuit and the variable resistor element of the adaptive circuit each comprise an indium-gallium-zinc-oxide (IGZO) transistor.
However, Kim teaches wherein the variable resistor element of the membrane circuit and the variable resistor element of the adaptive circuit each comprise an indium-gallium-zinc-oxide (IGZO) transistor (Kim, Par. [0026], “The resistance change layer may include one or more materials selected from IGZO, ITZO, IWZO, ZSO, IZO and IGO.”, thus, the variable resistor element of the membrane and adaptive circuits may comprise an IGZO transistor).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit of claim 4, as disclosed by Beidas in view of Aamir to include wherein the variable resistor element of the membrane circuit and the variable resistor element of the adaptive circuit each comprise an indium-gallium-zinc-oxide (IGZO) transistor, as disclosed by Kim. One of ordinary skill in the art would have been motivated to make this modification to enable the maintenance of resistance according to historical signals utilizing a variable resistor element such as an IGZO transistor, hence automating adaptation/tuning and likewise improving performance and reducing power consumption by lowering leakage current (Kim, Par. [0074], “ For example, the variable resistance memory devices M1 and M2 may include any one or more of a memristor, a resistive random access memory (RRAM), a phase-change random access memory (PcRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FeRAM) and a conductive bridging random access memory (CBRAM), but is not limited thereto. Such variable resistance memory devices M1 and M2 have a characteristic of maintaining resistance according to the history of a previously inputted memory signal in the SET or RESET mode. The information on the maintained resistance may be derived when a memory signal in the reading mode is applied.” & Par. [0102], “In particular, similar to indium-gallium-zinc-oxide transistors (IGZO transistors) and the like, transistors 200 in which the channel material layer 230 include a metal oxide material of three elements or more (e.g., IGZO, ITZO, IWZO, ZSO, IZO, IGO, etc.) have a lower leakage current and a higher on/off current ratio than those of silicon transistors. In this case, since a high on/off current ratio may be obtained with a small change in the gate voltage, it may be more advantageous to secure multi-levels.”).
11. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Beidas et al. (hereinafter Beidas) (US PG-PUB 20230100670), in view of Aamir et al. (hereinafter Aamir) (“A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores”), further in view of Cappy et al. (hereinafter Cappy) (US PG-PUB 20190130258).
Regarding Claim 9, Beidas in view of Aamir teaches the neuron circuit of claim 1.
Beidas in view of Aamir does not explicitly disclose wherein the pulse generation circuit comprises a plurality of positive channel metal-oxide semiconductors (PMOSs) and a plurality of negative channel metal-oxide semiconductors (NMOSs).
However, Cappy teaches wherein the pulse generation circuit comprises a plurality of positive channel metal-oxide semiconductors (PMOSs) and a plurality of negative channel metal-oxide semiconductors (NMOSs) (Cappy, Par. [0026], “The aim of the invention is to propose an artificial neuron able to address all or some of these constraints, and this aim is achieved, according to one of its aspects, by virtue of an artificial neuron comprising: a capacitor, called membrane capacitor; a negative feedback pulse circuit comprising: a bridge based on PMOS and NMOS transistors in series and connected by a midpoint to the membrane capacitor;”, thus, the pulse generation circuit (negative feedback pulse circuit) comprises a plurality of PMOS and NMOS transistors)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit of claim 1, as disclosed by Beidas in view of Aamir to include wherein the pulse generation circuit comprises a plurality of positive channel metal-oxide semiconductors (PMOSs) and a plurality of negative channel metal-oxide semiconductors (NMOSs), as disclosed by Cappy. One of ordinary skill in the art would have been motivated to make this modification to enable the use of PMOS and NMOS transistors, which may more closely mimic the function of biological neurons, hence improving system performance and reducing power consumption (Cappy, Par. [0039], “According to an advantageous embodiment, the charging of the membrane capacitor is provided by the PMOS transistor of the bridge and the discharging thereof is provided by the NMOS transistor. In this case, the delay capacitance connected to the PMOS transistor is lower than the delay capacitance connected to the NMOS transistor, with the optimum being zero. The delay capacitance connected to the NMOS transistor is preferably greater than the membrane capacitance. This embodiment is similar to the biological operation of the neuron where the sodium/calcium channels (by analogy represented by the PMOS transistor of the bridge) are faster than the potassium channels (by analogy represented by the NMOS transistor of the bridge).”)
Regarding Claim 10, Beidas in view of Aamir in view of Cappy teaches the neuron circuit of claim 9, wherein the pulse generation circuit is configured to perform an operation of applying a pulse to the adaptive circuit based on a common voltage and an output voltage (Beidas, Par. [0141], “An OR logic 718 may be coupled to a reset output of the comparator 714 and an output of the spike generation circuit 717 to receive reset signals and provide a reset signal from its output to provide an indication of a reset operation to the components of the neuron circuit. In response to a received reset signal, the membrane potential accumulator 707 may reset the integration value to the predefined membrane resting potential value, and/or the leakage accumulator 708 may reset the leakage value to the predefined initial leakage value. Furthermore, in response to the received reset signal, the oscillator activator 705 may deactivate the oscillator 706. The neuron circuit may include a delay circuit to provide a delay for a period of time between the respective determinations from the comparators and the generation of the reset signal. Alternatively, a delay circuit may receive the reset signal to introduce a predefined delay for a refractory period.”, thus, the spike/pulse generation circuit is configured to perform an operation of applying a pulse to the adaptive circuit (comprising the leakage accumulator/oscillator/oscillator activator) based on a common voltage (based on the OR logic comparing signals between the components) and an output voltage of the spike generation circuit – this is also supported by supporting Par. [0140]).
Allowable Subject Matter
12. No prior art rejection is made for Claims 12-13. Claims 12-13 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
13. Examiner has disclosed Aamir et al. (“A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores”) which is the closest prior art as compared to instant application Claims 12-13. Aamir discloses a multicompartment neuron circuit based on the adaptive-exponential integrate & fire (AdEx model). In particular, Aamir’s model is characterized by an adaptive current transmitted based on an adaptation time constant parameter, a subthreshold adaptation conductor parameter, and a spike-triggered adaptation current parameter, as outlined by the rejection of instant claim 2 above, which Claims 12-13 are dependent upon. However, Aamir does not explicitly disclose the specific limitations of instant Claims 12 and 13 including “[…] wherein a voltage value of a capacitor element of the adaptive circuit is proportional to a voltage value of a capacitor element of the membrane circuit” and “[…] wherein a capacitor element of the adaptive circuit is configured to decrease a voltage value of a capacitor element of the membrane circuit” in combination with the remaining limitations of the Independent claims.
Conclusion
14. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Devika S Maharaj whose telephone number is (571)272-0829. The examiner can normally be reached Monday - Thursday 8:30am - 5:30pm.
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/DEVIKA S MAHARAJ/Examiner, Art Unit 2123
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