Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION 2 . This Office Action responds to the Application filed on 6/01/2023. Claims 1-20 are pending. Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. 4. Claim(s) 1-6, 8-13, and 15-20 is/are rejected under 35 U.S.C. 102 (A)(1) as being anticipated by Karri et al. (U.S. Pub. No. 2022/0147598 A1) . As per claim 1, Karri discloses: A method for providing a functional verification flow of obfuscated designs for circuits, the method comprising: applying an input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited ] ) to an obfuscated design for an integrated circuit that is formatted in a hardware description language (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing I P s … obfuscate the semantic information in an RTL design , See Para [0039]-[0040], i.e. generate an obfuscated RTL design) ; applying the input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited ] ) to an original design for the integrated circuit that is formatted in the hardware description language (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design [ prior art obfuscate original design, wherein the original design is in RTL ]) ; and comparing respective outputs provided by the obfuscated design and the original design to determine functional correctness of the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art perform formal verification to determine equivalent function, considered as the comparing as cited above ] ). As per claim 2, Karri discloses all of the feature s of claim 1 discloses above wherein Karri also discloses wherein the input sequence is a potential key sequence generated during obfuscation of the original design (See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 3, Karri discloses all of the feature s of claim 1 discloses above wherein Karri also discloses wherein the applying the input sequence to the obfuscated design comprises providing the input sequence to a key checker that compares the input sequence to data stored in a key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 4, Karri discloses all of the feature s of claim 3 discloses above wherein Karri also discloses applying the input sequence to the obfuscated design in response to a determination that the input sequence corresponds to the data stored in the key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 5, Karri discloses all of the feature s of claim 3 discloses above wherein Karri also discloses wherein the data stored in the key register is a predetermined key sequence generated during an obfuscation process for the obfuscated design ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 6, Karri discloses all of the feature s of claim 3 discloses above wherein Karri also discloses generating a key error value in response to a determination that the input sequence does not correspond to the data stored in the key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 8, Karri disclosesL An apparatus comprising at least one processor and at least one memory including program code, the at least one memory and the program code configured to, with the at least one processor, cause the apparatus to (See Figure 11, i.e. processor and computer accessible medium) at least: apply an input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited ] ) to an obfuscated design for an integrated circuit that is formatted in a hardware description language (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design); apply the input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited ] ) to an original design for the integrated circuit that is formatted in the hardware description langua ge (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design [ prior art obfuscate original design, wherein the original design is in RTL ]); and compare respective outputs provided by the obfuscated design and the original design to determine functional correctness of the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art perform formal verification to determine equivalent function, considered as the comparing as cited above ]). As per claim 9, Karri discloses all of the feature s of claim 8 discloses above wherein Karri also discloses wherein the input sequence is a potential key sequence generated during obfuscation of the original design (See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 10, Karri discloses all of the feature s of claim 8 discloses above wherein Karri also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: provide the input sequence to a key checker that compares the input sequence to data stored in a key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 11, Karri discloses all of the feature s of claim 10 discloses above wherein Karri also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: apply the input sequence to the obfuscated design in response to a determination that the input sequence corresponds to the data stored in the key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 12, Karri discloses all of the feature s of claim 10 discloses above wherein Karri also discloses wherein the data stored in the key register is a predetermined key sequence generated during an obfuscation process for the obfuscated design ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 13, Karri discloses all of the feature s of claim 10 discloses above wherein Karri also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: generate a key error value in response to a determination that the input sequence does not correspond to the data stored in the key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 15, Karri discloses: A non-transitory computer storage medium comprising instructions, the instructions being configured to cause one or more processors to at least perform operations configured (See Figure 11, i.e. processor and computer accessible medium) to: apply an input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited ] ) to an obfuscated design for an integrated circuit that is formatted in a hardware description language (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design) ; apply the input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited ] ) to an original design for the integrated circuit that is formatted in the hardware description language (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design [ prior art obfuscate original design, wherein the original design is in RTL ]) ; and compare respective outputs provided by the obfuscated design and the original design to determine functional correctness of the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [ prior art perform formal verification to determine equivalent function, considered as the comparing as cited above ]). As per claim 16, Karri discloses all of the feature s of claim 15 discloses above wherein Karri also discloses wherein the input sequence is a potential key sequence generated during obfuscation of the original design (See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 17, Karri discloses all of the feature s of claim 15 discloses above wherein Karri also discloses wherein the operations are further configured to: provide the input sequence to a key checker that compares the input sequence to data stored in a key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 18, Karri discloses all of the feature s of claim 17 discloses above wherein Karri also discloses wherein the operations are further configured to: apply the input sequence to the obfuscated design in response to a determination that the input sequence corresponds to the data stored in the key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 19, Karri discloses all of the feature s of claim 17 discloses above wherein Karri also discloses wherein the data stored in the key register is a predetermined key sequence generated during an obfuscation process for the obfuscated design ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). As per claim 20, Karri discloses all of the feature s of claim 17 discloses above wherein Karri also discloses wherein the operations are further configured to: generate a key error value in response to a determination that the input sequence does not correspond to the data stored in the key register ( See Para [0037], i.e. verify that resulting RTL can be equivalent to original design , Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL desig n, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation , See Para [0037], See Para [0039]-[0043], i.e. k ey bits that can be used by ASSURE , See Para [0044]-[0081]). Claim Rejections - 35 USC § 103 5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 6. Claim (s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karri et al. (U.S. Pub. No. 2022/0147598 A1) in view Moondanos et al. (U.S. Pub. No. 2004/0093574 A1). As per claim 7, Karri discloses all of the feature s of claim 1 as discloses above . Karri does not teach the limitations: wherein the comparing the respective outputs comprises comparing the respective outputs provided by the obfuscated design and the original design via a miter circuit. However, Moondanos teach the limitations: wherein the comparing the respective outputs comprises comparing the respective outputs provided by the obfuscated design and the original design via a miter circuit (See Para [0033], i.e. the formal equivalence verification tool 155 creates the miter circuit ). Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to incorporate the teaching of Moondanos into the teaching of Karri because it would reduce false negative result in formal verification (See Para [0005]-[0006]). As per claim 14, Karri discloses all of the feature s of claim 8 as discloses above . Karri does not teach the limitations: compare the respective outputs provided by the obfuscated design and the original design via a miter circuit. However, Moondanos teach the limitations: compare the respective outputs provided by the obfuscated design and the original design via a miter circuit. (See Para [0033], i.e. the formal equivalence verification tool 155 creates the miter circuit ). Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to incorporate the teaching of Moondanos into the teaching of Karri because it would reduce false negative result in formal verification (See Para [0005]-[0006]). Conclusion 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NHA T NGUYEN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1405 . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NHA T NGUYEN/ Primary Examiner, Art Unit 2851