Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Amendment filed on 6/26/2023.
Claims 1-20 are pending.
Response to Applicant’s Remarks
3. With respect to Applicant’s remarks, the following are addressed:
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of new ground(s) of rejection(s) as follow:
Claim(s) 1-6, 8-13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karri et al. (U.S. Pub. No. 2022/0147598 A1) in view of Tanimoto (U.S. Pub. No. 2009/0241074 A1).
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karri et al. (U.S. Pub. No. 2022/0147598 A1) in view of Tanimoto (U.S. Pub. No. 2009/0241074 A1) and further in view Moondanos et al. (U.S. Pub. No. 2004/0093574 A1).
In the current rejection(s) of the claims, newly cited prior art Tanimoto teach the use of input queue to verify equivalence between a first circuit design and a second circuit design (See Tanimoto, Figure 1 & Para [0100]). Therefore, the combination of Tanimoto into prior art Karri would allow for Karri to verify equivalency between an original design and an obfuscated design using input queue in order to eliminate difference between input/output access timing cycle between the two design. Therefore, the combination of prior art Karri, Tanimoto, and Moondanos teach the limitations of the claims as cited below.
The rejections of the claims are as cited below. This office action is Final.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 1-6, 8-13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karri et al. (U.S. Pub. No. 2022/0147598 A1) in view of Tanimoto (U.S. Pub. No. 2009/0241074 A1).
As per claim 1, Karri discloses:
A method for providing a functional verification flow of obfuscated designs for circuits, the method comprising:
applying an input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited]) to an original design for an integrated circuit that is formatted in a hardware description language (See Para [0007], i.e. IC design based on a first register-transfer level (RTL) design, See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design);
applying the input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited]) to an obfuscated design (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design [prior art obfuscate original design, wherein the original design is in RTL]); and
comparing respective outputs provided by the obfuscated design and the original design to determine functional correctness of the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art perform formal verification to determine equivalent function, considered as the comparing as cited above]).
Karri does not teach: in parallel to the input sequence being processed by the original design for the integrated circuit, storing the input sequence in an input queue to align verification framework processing between the original design and an obfuscated design for the integrated circuit, and applying the input sequence to the obfuscated design subsequent to the input sequence being stored in the input queue.
However, Tanimoto teach: in parallel to the input sequence being processed by the original design for the integrated circuit, storing the input sequence in an input queue to align verification framework processing between the original design and an second design for the integrated circuit, and applying the input sequence to the second design subsequent to the input sequence being stored in the input queue (See Para [0006], i.e. circuit descriptions of the circuit description of the operation level described in the system level design language, See Para [0100], i.e. the model to be verified test input/output model 6 reads (pops) and fetches input data from the input FIFO group 5 with the same timing as that of the model to be verified 2 and outputs the fetched data to the model to be verified 2… check the function of the model to be verified 2 having the equivalence of input/output for the sample model 1, See Figure 1, i.e. example circuit 1 in parallel with second circuit 2 , with storing input in input queue 4 –[prior art teach using input queue to verify equivalence between a first and a second circuit, the combine teaching of Tanimoto and Karri would allow for Karri to verify the equivalence between an original design and a obfuscated design (second) using queue to allow for elimination difference between input/output access timing cycle between a first model and a second circuit model]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Tanimoto
into the teaching of Karri because it would eliminate difference between input/output
access timing cycle between a first model and a second circuit model when performing
equivalence checking (See Para [0013]-[0014]).
As per claim 2, Karri and Tanimoto discloses all of the features of claim 1 discloses above wherein Karri also discloses wherein the input sequence is a potential key sequence generated during obfuscation of the original design (See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 3, Karri and Tanimoto discloses all of the features of claim 1 discloses above wherein Karri also discloses wherein the applying the input sequence to the obfuscated design comprises providing the input sequence to a key checker that compares the input sequence to data stored in a key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 4, Karri and Tanimoto discloses all of the features of claim 3 discloses above wherein Karri also discloses applying the input sequence to the obfuscated design in response to a determination that the input sequence corresponds to the data stored in the key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 5, Karri and Tanimoto discloses all of the features of claim 3 discloses above wherein Karri also discloses wherein the data stored in the key register is a predetermined key sequence generated during an obfuscation process for the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 6, Karri and Tanimoto discloses all of the features of claim 3 discloses above wherein Karri also discloses generating a key error value in response to a determination that the input sequence does not correspond to the data stored in the key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 8, Karri discloses:
An apparatus comprising at least one processor and at least one memory including program code, the at least one memory and the program code configured to, with the at least one processor, cause the apparatus to (See Figure 11, i.e. processor and computer accessible medium) at least:
apply an input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited]) to an original design for an integrated circuit that is formatted in a hardware description language (See Para [0007], i.e. IC design based on a first register-transfer level (RTL) design, See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design);
apply the input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited]) to an original design the obfuscated design (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design [prior art obfuscate original design, wherein the original design is in RTL]); and
compare respective outputs provided by the obfuscated design and the original design to determine functional correctness of the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art perform formal verification to determine equivalent function, considered as the comparing as cited above]).
Karri does not teach: in parallel to the input sequence being processed by the original design for the integrated circuit, storing the input sequence in an input queue to align verification framework processing between the original design and an obfuscated design for the integrated circuit, and applying the input sequence to the obfuscated design subsequent to the input sequence being stored in the input queue.
However, Tanimoto teach: in parallel to the input sequence being processed by the original design for the integrated circuit, storing the input sequence in an input queue to align verification framework processing between the original design and an second design for the integrated circuit, and applying the input sequence to the second design subsequent to the input sequence being stored in the input queue (See Para [0006], i.e. circuit descriptions of the circuit description of the operation level described in the system level design language, See Para [0100], i.e. the model to be verified test input/output model 6 reads (pops) and fetches input data from the input FIFO group 5 with the same timing as that of the model to be verified 2 and outputs the fetched data to the model to be verified 2… check the function of the model to be verified 2 having the equivalence of input/output for the sample model 1, See Figure 1, i.e. example circuit 1 in parallel with second circuit 2 , with storing input in input queue 4 –[prior art teach using input queue to verify equivalence between a first and a second circuit, the combine teaching of Tanimoto and Karri would allow for Karri to verify the equivalence between an original design and a obfuscated design (second) using queue to allow for elimination difference between input/output access timing cycle between a first model and a second circuit model]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Tanimoto
into the teaching of Karri because it would eliminate difference between input/output
access timing cycle between a first model and a second circuit model when performing
equivalence checking (See Para [0013]-[0014]).
As per claim 9, Karri and Tanimoto discloses all of the features of claim 8 discloses above wherein Karri also discloses wherein the input sequence is a potential key sequence generated during obfuscation of the original design (See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 10, Karri and Tanimoto discloses all of the features of claim 8 discloses above wherein Karri also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: provide the input sequence to a key checker that compares the input sequence to data stored in a key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 11, Karri and Tanimoto discloses all of the features of claim 10 discloses above wherein Karri also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: apply the input sequence to the obfuscated design in response to a determination that the input sequence corresponds to the data stored in the key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 12, Karri and Tanimoto discloses all of the features of claim 10 discloses above wherein Karri also discloses wherein the data stored in the key register is a predetermined key sequence generated during an obfuscation process for the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 13, Karri and Tanimoto discloses all of the features of claim 10 discloses above wherein Karri also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: generate a key error value in response to a determination that the input sequence does not correspond to the data stored in the key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 15, Karri discloses:
A non-transitory computer storage medium comprising instructions, the instructions being configured to cause one or more processors to at least perform operations configured (See Figure 11, i.e. processor and computer accessible medium) to:
apply an input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited]) to an original design for an integrated circuit that is formatted in a hardware description language (See Para [0007], i.e. IC design based on a first register-transfer level (RTL) design, See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design);
apply the input sequence (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art verify circuit equivalent function by performing formal verification, considered as the applying input as cited]) to an obfuscated design (See Para [0029], i.e. obfuscation can be applied to existing RTL IPs , Para [0033]-[0038], i.e. an RTL design D…obfuscate existing IPs … obfuscate the semantic information in an RTL design, See Para [0039]-[0040], i.e. generate an obfuscated RTL design [prior art obfuscate original design, wherein the original design is in RTL]); and
compare respective outputs provided by the obfuscated design and the original design to determine functional correctness of the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original [prior art perform formal verification to determine equivalent function, considered as the comparing as cited above]).
Karri does not teach: in parallel to the input sequence being processed by the original design for the integrated circuit, storing the input sequence in an input queue to align verification framework processing between the original design and an obfuscated design for the integrated circuit, and applying the input sequence to the obfuscated design subsequent to the input sequence being stored in the input queue.
However, Tanimoto teach: in parallel to the input sequence being processed by the original design for the integrated circuit, storing the input sequence in an input queue to align verification framework processing between the original design and an second design for the integrated circuit, and applying the input sequence to the second design subsequent to the input sequence being stored in the input queue (See Para [0006], i.e. circuit descriptions of the circuit description of the operation level described in the system level design language, See Para [0100], i.e. the model to be verified test input/output model 6 reads (pops) and fetches input data from the input FIFO group 5 with the same timing as that of the model to be verified 2 and outputs the fetched data to the model to be verified 2… check the function of the model to be verified 2 having the equivalence of input/output for the sample model 1, See Figure 1, i.e. example circuit 1 in parallel with second circuit 2 , with storing input in input queue 4 –[prior art teach using input queue to verify equivalence between a first and a second circuit, the combine teaching of Tanimoto and Karri would allow for Karri to verify the equivalence between an original design and a obfuscated design (second) using queue to allow for elimination difference between input/output access timing cycle between a first model and a second circuit model]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Tanimoto
into the teaching of Karri because it would eliminate difference between input/output
access timing cycle between a first model and a second circuit model when performing
equivalence checking (See Para [0013]-[0014]).
As per claim 16, Karri and Tanimoto discloses all of the features of claim 15 discloses above wherein Karri also discloses wherein the input sequence is a potential key sequence generated during obfuscation of the original design (See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 17, Karri and Tanimoto discloses all of the features of claim 15 discloses above wherein Karri also discloses wherein the operations are further configured to: provide the input sequence to a key checker that compares the input sequence to data stored in a key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 18, Karri and Tanimoto discloses all of the features of claim 17 discloses above wherein Karri also discloses wherein the operations are further configured to: apply the input sequence to the obfuscated design in response to a determination that the input sequence corresponds to the data stored in the key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 19, Karri and Tanimoto discloses all of the features of claim 17 discloses above wherein Karri also discloses wherein the data stored in the key register is a predetermined key sequence generated during an obfuscation process for the obfuscated design (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
As per claim 20, Karri and Tanimoto discloses all of the features of claim 17 discloses above wherein Karri also discloses wherein the operations are further configured to: generate a key error value in response to a determination that the input sequence does not correspond to the data stored in the key register (See Para [0037], i.e. verify that resulting RTL can be equivalent to original design, Para [0088]-[0092], i.e. formal verification of the locked design against the unprotected design…unlocked circuit matches the original, See Para [0005], i.e. key … memory, See Para [0008], i.e. key can be applied to the second RTL design, See Para [0033], i.e. the locking key; their values can be known to the designer during obfuscation, See Para [0037], See Para [0039]-[0043], i.e. key bits that can be used by ASSURE, See Para [0044]-[0081]).
6. Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karri et al. (U.S. Pub. No. 2022/0147598 A1) in view of Tanimoto (U.S. Pub. No. 2009/0241074 A1) and further in view Moondanos et al. (U.S. Pub. No. 2004/0093574 A1).
As per claim 7, Karri and Tanimoto discloses all of the features of claim 1 as discloses above.
Karri and Tanimoto does not teach the limitations: wherein the comparing the respective outputs comprises comparing the respective outputs provided by the obfuscated design and the original design via a miter circuit.
However, Moondanos teach the limitations: wherein the comparing the respective outputs comprises comparing the respective outputs provided by the obfuscated design and the original design via a miter circuit (See Para [0033], i.e. the formal equivalence verification tool 155 creates the miter circuit).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Moondanos
into the teaching of Karri and Tanimoto because it would reduce false negative result in
formal verification (See Para [0005]-[0006]).
As per claim14, Karri and Tanimoto discloses all of the features of claim 8 as discloses above.
Karri and Tanimoto does not teach the limitations: compare the respective outputs provided by the obfuscated design and the original design via a miter circuit.
However, Moondanos teach the limitations: compare the respective outputs provided by the obfuscated design and the original design via a miter circuit. (See Para [0033], i.e. the formal equivalence verification tool 155 creates the miter circuit).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Moondanos
into the teaching of Karri and Tanimoto because it would reduce false negative result in
formal verification (See Para [0005]-[0006]).
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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