DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/01/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1 and 6 are objected to because of the following informalities:
Claim 1 line 3- delete “for” to positively describe that the data memory stores the synaptic weights and neuron states.
Claim 1 line 7- insert --first-- before “memory port” to clarify that this refers to the first memory port introduced in line 4.
Similar clarifications should be made for this term in line 9 and line 21
Claim 1 line 19- delete the comma to improve readability.
Claim 6- insert --configurable-- after “said” in line 4 to clarify that this refers to the configurable data-type introduced in line 2.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, the phrase "such as" in line 2 renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d). For purposes of examination the configurable data type will be interpreted as comprising one of the data types following the phrase.
Claim 7 recites “said sub-portion” in line 4. It is unclear which sub-portion this refers to as lines 2-3 introduce plural sub-portions. For purposes of examination this limitation will be interpreted as any one of the introduced sub-portions.
Claim 8 recites “the execution” in line 2. It is unclear whether this refers to the execution of the micro-code kernel by the load buffer providing NPE instructions to the NPEs or if it refers to the execution by the NPEs. For purposes of examination, this will be interpreted as referring to the execution by the NPEs.
Claim 10 recites “the output event” in line 3. It is unclear whether this refers to the output events introduced in claim 9 or if it refers to one of the one or more of the output events introduced in line 2. For purposes of examination, the latter interpretation will be taken.
Claim 11 recites “a plurality of neuro-synaptic processing circuitries according to claim 1”. This limitation is unclear because claim 1 does not introduce a plurality of neuro-synaptic processing circuitries. For purposes of examination this limitation will be interpreted as “a plurality of neuro-synaptic processing circuitries each configured according to the neuro-synaptic processing circuitry of claim 1”.
Claim 12 recites “a plurality of neuro-synaptic processing circuitries according to claim 7”. This limitation is unclear because claim 7 does not introduce a plurality of neuro-synaptic processing circuitries. For purposes of examination this limitation will be interpreted as “a plurality of neuro-synaptic processing circuitries each configured according to the neuro-synaptic processing circuitry of claim 7”.
Claim 13 recites “the NoC” in line 1. There is insufficient antecedent basis for this limitation as the claim does not introduce a NoC in this chain. For purposes of examination this claim will be interpreted as depending from claim 12, which introduces a NoC.
Claim 14 recites “the program code” in line 3. It is unclear which program code this refers to as claim 11 introduces “a plurality of neuro-synaptic processing circuitries according to claim 1” which indicates that there is a program code for each neuro-synaptic processing circuitry. For purposes of examination, this will be interpreted as the program code of any one of the neuro-synaptic processing circuitries.
Claim 14 recites “the synaptic weights and/or neuron states” in lines 3-4. It is unclear which synaptic weights and neuron states this refers to as claim 11 introduces “a plurality of neuro-synaptic processing circuitries according to claim 1” which indicates that there are synaptic weights and neuron states for each neuro-synaptic processing circuitry. For purposes of examination, this will be interpreted as the synaptic weights and neuron states of any one of the neuro-synaptic processing circuitries.
Claim 14 recites “the data memory” in line 4. It is unclear which data memory this refers to as claim 11 introduces “a plurality of neuro-synaptic processing circuitries according to claim 1” which indicates that there is a data memory for each neuro-synaptic processing circuitry. For purposes of examination, this will be interpreted as the data memory of any one of the neuro-synaptic processing circuitries.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Allowable Subject Matter
Claims 1-5 are allowed. While no prior art rejection is given for claims 6-14, these claims are currently rejected under 112(b) and are not allowable at the current point.
The following is a statement of reasons for the indication of allowable subject matter:
The known prior art, taken alone or in combination, was not found to teach, in combination with other limitations in the claim, a loop buffer having a register-based memory, and address calculation unit, and a program counter, wherein the loop buffer receives a micro-code kernel from a GP-CPU and iteratively provides instructions of the micro-code kernel to NPEs for execution, and upon a load or store instruction the loop buffer provides a memory address stored in the loop buffer to a memory port and updates the memory address, as required by claim 1.
The closest prior art of record was found to be:
US 2007/0113058 which teaches a coprocessor fetching instructions for a loop of SIMD type, placing them in an instruction queue dedicated to SIMD instructions, and executing the loop from there, freeing up the instruction execution logic unit that is not dedicated to SIMD instructions for other activities, see [0022], and a load queue of the coprocessor that loads data for loop operation and keeps track of the base address, index, offset, and the adder to generate addresses to L2 cache, see [0026]-[0027].
US 2019/0311251 which teaches reusing instructions for different neural network layers when they are substantially similar, see [0015]
US 2016/0283439 which teaches a SIMD processing module comprising multiple vector processing units that execute an instruction on respective parts of a vector, see Abstract, and that a load instruction may be executed by a vector processing unit which increments the address pointer when the instruction is repeated, see [0004].
US 2020/0293867 which teaches a program executed on a host processor that encodes a command stream in a buffer that provides workloads to a parallel processing unit, see [0116], and exploiting data reuse opportunities across multiple loop levels, see [0028]
US 2005/0102659 teaches a loop buffer holding program loop instructions and a register file holding loop control parameters, see [0007]
While the known prior art of record was found to generally teach loop buffers and processing elements executing instructions in parallel from a CPU, the known prior art of record was not found to teach a loop buffer that receives a micro-code kernel from a GP-CPU and iteratively provides NPE instructions of the micro-code kernel to neuron processing elements upon instruction of the GP-CPU, where upon a load or store instruction, the loop buffer provides a stored memory address to a memory port and updates the memory address by an address calculation unit of the loop buffer as specifically described in claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0156077 teaches reusing the same operation code in the same storage area for repeated instructions in two instruction sets, see Abstract
US 2017/0316312 teaches kernel reuse, wherein a same kernel is kept and repeatedly applied on different data at each convolution layer, see [0030] and Fig. 7A
US 2014/0281373 teaches a local queue that repeats a sequence of instructions to a vector execution unit, see Abstract
US 2012/0216012 teaches an array of ALUs executing the same or different instructions on the same or different data, where issued instructions may be kept for multiple cycles in order to process an inner loop efficiently, see [0024]-[0025]
US 2013/0185516 teaches a hardware prefetcher that recognizes an auto-increment address instruction and prefetches based on a stride determined from an increment field of the instruction, see [0037]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KASIM ALLI whose telephone number is (571)270-1476. The examiner can normally be reached Monday - Friday 9am 5pm.
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183