DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 10/7/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 are rejected under 35 U.S.C. 102a2 as being anticipated by Subramanian (US 2024/0192714).
With respect to claim 1, Subramanian discloses a power supply circuit (Fig. 2A 200) for a load (Fig. 2A 240 powers Fig. 1 100), the power supply circuit comprising: a power supply voltage regulator (Fig. 2A 220, and main FET driven by 220); a current driver (Fig. 2A VCC and 230 FETs with BIAS) configured to supply current to a load node (Fig. 2A node CLOAD) of a circuit in parallel (Fig. 2A FETs in parallel) with the voltage regulator; and a switch (Fig. 2A switches controlled by EN1-EN3) configured to couple (Fig. 2A closed EN1-EN3 permits I1-I3) the current driver to the load node in response (Fig. 4B EN1-EN3 generated from Gate_enable) to an input signal (Fig. 1 Gate_enable) to the load.
With respect to claim 2, Subramanian discloses the power supply circuit of claim 1, wherein the current driver comprises a current mirror (Fig. 2A 230 FETs biased to BIAS form a current mirror.
With respect to claim 3, Subramanian discloses the power supply circuit of claim 2, wherein the current mirror is configured to receive a digital code (Fig. 2A EN1-EN3) to set an amount of output current.
With respect to claim 4, Subramanian discloses the power supply circuit of claim 3, further comprising training (paragraph 25) logic (Fig. 4A DELAY1-DELAY3) configured to determine a setting for the digital code.
With respect to claim 5, Subramanian discloses the power supply circuit of claim 1, the input signal comprising an enable signal (Fig. 1 Gate_enable) for the load.
Claim(s) 1 and 5-9 are rejected under 35 U.S.C. 102a1 as being anticipated by Lam (US 2010/0026251).
With respect to claim 1, Lam discloses a power supply circuit (Fig. 6 302) for a load (Fig. 6 204), the power supply circuit comprising: a power supply voltage regulator (Fig. 6 amplifier and FET); a current driver (Fig. 6 304) configured to supply current to a load node (Fig. 6 node VREG) of a circuit (Fig. 6 308) in parallel with the voltage regulator; and a switch (Fig. 6 switch in series with 304) configured to couple the current driver to the load node in response to an input signal (Fig. 6 INP-INM) to the load.
With respect to claim 5, Lam discloses the power supply circuit of claim 1, the input signal comprising an enable signal (paragraph 55, “can monitor … an enable signal”) for the load.
With respect to claim 6, Lam discloses the power supply circuit of claim 1, further comprising a detector (Fig. 6 302) interposed between the input signal and the switch.
With respect to claim 7, Lam discloses the power supply circuit of claim 6, wherein the detector comprises logic (Fig. 6 302) to detect a clock signal (paragraph 55, “can monitor a clock”) to the load.
With respect to claim 8, Lam discloses the power supply circuit of claim 6, wherein the detector comprises logic to detect a data signal (Fig. 8 INP-INM) to the load.
With respect to claim 9, Lam discloses the power supply circuit of claim 8, wherein the logic to detect the data signal to the load comprises logic (Fig. 6 302) to operate the switch in response to binary transitions (Fig. 6 INP-INM transitions high to low and low to high) in the data signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian (US 2024/0192714) in view of Pineda (US 2006/0248354).
With respect to claim 6, Subramanian discloses the power supply circuit of claim 1 as set forth above, wherein the Gate_enable signal is detected and does not disclose a detector interposed between the input signal and the switch.
Pineda discloses a detector (Fig. 8 72,80) interposed between the input signal (Fig. 8 INPUT DATA) and the controller of the voltage regulator (Fig. 8 84). It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement a detector interposed between the input signal and the switch, in order to detect the activity of the load.
With respect to claim 8, Subramanian in view or Pineda make obvious the power supply circuit of claim 6, wherein the detector comprises logic to detect a data signal (Fig. 8 INPUT DATA) to the load.
With respect to claim 9, Subramanian in view of Pineda make obvious the power supply circuit of claim 8, wherein the logic to detect the data signal to the load comprises logic (Fig. 8 72) to operate the switch (in combination Subrmanian controls the switch in response to the binary transitions of the INPUT DATA) in response to binary transitions in the data signal.
Claim(s) 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian (US 2024/0192714) in view of Kim (US 2017/0060165).
With respect to claim 12, Subramanian discloses a circuit comprising: a voltage regulator (Fig. 2A 220, FET coupled to 220) coupled to a power rail (Fig. 2A VCC); a current driver (Fig. 2A 230 FETs) comprising a plurality of incremental current sources (Fig. 2A 230 FETs source I1-I3) configured in parallel with the voltage regulator between a load (Fig. 2A 240) and the power rail (Fig. 2A 240); and a plurality of independently-operable switches (Fig. 2A 230 switches coupled to EN1-EN3) in series with the incremental current sources and the load, the switches responsive to (Fig. 4B EN1-EN3 responsive to Gate_signal) one or more of an enable signal (Fig. 4B Gate_signal), clock signal, and binary sequence applied to the load (Fig. 2A 240 powers Fig. 1 100). Subramian discloses wherein the switches are in series with the biased FET current sources, and in Figure 2A the switches are not shown configured between the FETs and the load 240. However, the ordering of the switches and current sources does not alter the operation of the circuit and it was well known to arrange the switches between the current source and load.
Kim discloses a plurality of independently-operable switches (Fig. 3C SW1-SW6) configured between the incremental current sources (Fig. 3A I) and the load (Fig. 3A IREF1). It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement a plurality of independently-operable switches configured between the incremental current sources and the load as taught by Kim, since the ordering of the components in series does not change the output current.
With respect to claim 13, Subramian in view of Kim make obvious the circuit of claim 12, wherein the current sources comprise a current mirror (Fig. 2A FETs 230 driven at BIAS form a current mirror).
With respect to claim 14, Subramian in view of Kim make obvious the circuit of claim 13, wherein the current mirror is configured to respond to a digital code (Fig. 2A EN1-EN3) corresponding to one or more of the enable signal (Fig. 4B Gate_enable), clock signal, and binary sequence.
With respect to claim 15, Subramian in view of Kim make obvious the circuit of claim 14, further comprising training (paragraph 25) logic (Fig. 4A Delay-Delay3) configured to determine a value of the digital code.
With respect to claim 16, Subramian in view of Kim make obvious the circuit of claim 12, wherein the switches are responsive to an enable signal (Fig. 4B Gate_enable) applied to the load.
Claim(s) 2-3, 12-14 and 16-21are rejected under 35 U.S.C. 103 as being unpatentable over Lam (US 2010/0026251) in view of Kim (US 2017/0060165).
With respect to claim 2, Lam discloses the power supply circuit of claim 1 as set forth above, and remains silent as how to form the current source. It was well known at the time of filing of the invention to implement a current source as a current mirror.
Kim discloses wherein the current driver (Fig. 3C 224a) comprises a current mirror (paragraph 52; Fig. 3A 222a or Fig. 3B 222b). It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement wherein the current driver comprises a current mirror.
With respect to claim 3, Lam in view of Kim make obvious the power supply circuit of claim 2 as set forth above. Lam discloses only a fixed current source while Kim discloses an adjustable current source. It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement wherein the current mirror is configured to receive a digital code (Kim Fig. 3C ICS<5:0>) to set an amount of output current, in order to make the current source adjustable.
With respect to claim 12, Lam discloses a circuit comprising: a voltage regulator coupled (Fig. 6 amplifier and FET) to a power rail (Fig. 6 VDD); a current driver (Fig. 6 304) comprising a fixed current source configured in parallel with the voltage regulator between a load (Fig. 6 204) and the power rail; and a switch (Fig. 6 switch in series with 304) configured between the fixed current source and the load, the switch responsive to one or more of an enable signal, clock signal, and binary sequence (paragraph 55) applied to the load. Lam discloses a fixed current source and remains silent as to implementing an adjustable current source, which was well known at the time of filing of the invention.
Kim discloses a plurality of incremental current sources (Fig. 3C I) and a plurality of independently operable switches (Fig. 3C SW). It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement a plurality of incremental currents source and a plurality of independently operable switches between the power rail and the load, in order to be able to adjust the current source to improve the transient response.
With respect to claim 13, Lam in view of Kim make obvious the circuit of claim 12, wherein the current sources comprise a current mirror (Lam paragraph 52 and Fig 3A 222a or Fig 3B 222b).
With respect to claim 14, Lam in view of Kim make obvious the circuit of claim 13, wherein the current mirror is configured to respond to a digital code (Kim Fig. 3C ICS<5:0>) corresponding to one or more of the enable signal, clock signal, and binary sequence (Lam paragraph 55).
With respect to claim 16, Lam in view of Kim make obvious the circuit of claim 12, wherein the switches are responsive to an enable signal (Lam paragraph 55) applied to the load.
With respect to claim 17, Lam in view of Kim make obvious the circuit of claim 12, wherein the switches are responsive to a clock signal (Lam paragraph 55) applied to the load.
With respect to claim 18, Lam in view of Kim make obvious the circuit of claim 17, wherein the switches are responsive to a binary sequence applied (Lam paragraph 55) to the load.
With respect to claim 19, Lam in view of Kim make obvious the circuit of claim 18, wherein the switches are responsive to transitions (Fig. 6 transitions of INP-INM high to low and low to high) in the binary sequence.
With respect to claim 20, Lam in view of Kim make obvious the circuit of claim 17, further comprising a detector (Fig. 6 302) configured to detect one or both of the clock signal and the binary sequence.
With respect to claim 21, Lam discloses a circuit comprising: a voltage regulator (Fig. 6 amplifier and FET of 202) coupled between a power supply (Fig. 6 VDD) and a load (Fig. 6 204); a fixed current source (Fig. 6 304) configured in parallel with the voltage regulator between the power supply and the load; a detector (Fig. 6 302) configured to enable or disable (Fig. 6 open or close switch in series with 304) current to flow from the fixed current source to the load based on a state of a data signal or a state of a clock signal (paragraph 55) applied (Fig. 5 INP-INM) to the load. Lam discloses sensing either the clock signal or the data signal and remains silent as to sensing both. Nevertheless, it would have been obvious to one of ordinary skill in the art at the time of filing of the invention to sense both the clock and data signal in order to more accurately determine the power state of the load. Furthermore, Lam discloses a fixed current source and does not disclose an adjustable current source.
Kim discloses a controllable current source (Fig. 3C 224a) configured to adjust the current with a digital code (Fig. 3C ICS<5:0>). It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement a controller configured to convert a preconfigured digital code corresponding to the state of the data signal and the state of the clock signal into control signals that set an amount of the current flow provided by the controllable current source to the load, in order to be able to adjust the current to the detected power state in order to improve the transient.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang (US 8,539,262) discloses voltage regulation with improved transient response.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838