DETAILED ACTION
Correction to the Prior Office Action
In the previous office action dated 1/6/2026, PTOL-326 5a) incorrectly identified claims 11-12 as withdrawn, which should have been claims 10-11 are withdrawn; relatedly, 7) indicated claims 1-10 and 12-21 were rejected, and should have been claims 1-9 and 12-21 are rejected.
Claim Objections
Claims 14-15 are objected to because of the following informalities: in claim 14, “codes each” should be ‘codes, each’. Appropriate correction is required.
Response to Arguments
Applicant's arguments filed 4/6/20206 with respect to the amended claims and Subramanian have been fully considered and are persuasive. The amendments have overcome the previous rejections under Subramanian.
Applicant's arguments filed 4/6/20206 with respect to Lam have been fully considered but they are not persuasive. With respect to claims 1-3, Applicant argues Lam does not describe a switch configured to couple the current driver to the load node in response to an input signal to the load, wherein the input signal comprises a binary data signal associated applied to the load, and wherein the current driver is configured to supply supplemental current to the load node in predetermined amounts based on switching activity of the data signal. Examiner respectfully disagrees since Lam discloses in Figure 6 a switch configured to couple the current driver 304 to the load node VREG in response to the input signal INP to the load 204, and wherein the current driver 304 is configured to supply supplemental current as shown in Figure 5 BOOST CURRENT to the load node in predetermined amounts (Figure 5 amounts from 0A to ~4mA) based on switching activity (Fig. 5 TXP switching tracks INP) of the date signal (Fig. 5 and Fig. 6 transitions of INP).
With respect to claims 12-14, Applicant argues there is no disclosure in Kim that would suggest to modify Lam to configure a plurality of independently-operable switches configured between the incremental current source and the load, the switches responsive to transitions in a binary data sequence applied to the load. The rejection under Lam has been maintained below. Examiner disagrees as Kim teaches uses of the plurality of independently-operable switches and one of ordinary skill in the art would have been motivated to calibrate the current source to the need value to provide the improved response for Lam’s transitions in a binary data sequence applied to the load. Applicant’s arguments against claim 16 are moot since claim 16 has been cancelled.
Applicant’s amendment to claim 21 has placed the claim in condition for allowance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Examiner notes Applicant states that care has been exercised to introduce no new matter, but does not formally state no new matter has been entered. The new claim language of “particular transition patterns” is not support in the original disclosure which makes no mention of particular transition patterns and does not support the digital code corresponding to particular transition patterns. Applicant cannot further refine the invention while retaining the original filing date.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 6-7 are rejected under 35 U.S.C. 102a1 as being anticipated by Lam (US 2010/0026251).
With respect to claim 1, Lam discloses a power supply circuit (Fig. 6 202) for a load (Fig. 6 204), the power supply circuit comprising: a power supply voltage regulator (Fig. 6 amplifier and FET); a current driver (Fig. 6 304) configured to supply current to a load node (Fig. 6 node VREG) of a circuit (Fig. 6 308) in parallel with the voltage regulator; a switch (Fig. 6 switch in series with 304) configured to couple the current driver to the load node in response to an input signal (Fig. 6 INP) to the load;
wherein the input signal comprises a binary data signal (Fig. 5 TXP is INP delayed by buffers 204) applied to the load (Fig. 6 204); and wherein the current driver is configured to supply supplemental current (Fig. 6 current from 304) to the load node in predetermined amounts (Fig. 5 BOOST CURRENT AMPLITUDE) based on switching activity (Fig. 5 TXP transitions track transitions of INP) of the data signal.
With respect to claim 6, Lam discloses the power supply circuit of claim 1, further comprising a detector (Fig. 6 302) interposed between the input signal (Fig. 6 INP) and the switch.
With respect to claim 7, Lam discloses the power supply circuit of claim 6, wherein the detector comprises logic (Fig. 6 302) to detect activity [clock transitions] of a clock signal (paragraph 55, “can monitor a clock”) to the load.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 12-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lam (US 2010/0026251) in view of Kim (US 2017/0060165).
With respect to claim 2, Lam discloses the power supply circuit of claim 1 as set forth above, and remains silent as how to form the current source. It was well known before the effective filing date of the claimed invention to implement a current source as a current mirror.
Kim discloses wherein the current driver (Fig. 3C 224a) comprises a current mirror (paragraph 52; Fig. 3A 222a or Fig. 3B 222b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the current driver comprises a current mirror.
With respect to claim 3, Lam in view of Kim make obvious the power supply circuit of claim 2 as set forth above. Lam discloses a fixed current source to provide the supplemental current for binary transitions (Fig. 5 TXP transitions) in the data signal and does not disclose the current driver receiving a digital code, while Kim discloses an adjustable current source configured to receive a digital code (Kim Fig. 3C ICS<5:0>) to set a predetermined amount of current. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the current driver is configured to receive a digital code to set a predetermined amount of the supplemental current for a binary transition in the data signal, in order to make the current source adjustable such as for calibrating the current driver or decreasing the ripple by providing the required supplemental current.
With respect to claim 12, Lam discloses a circuit comprising: a voltage regulator coupled (Fig. 6 amplifier and FET) to a power rail (Fig. 6 VDD); a current driver (Fig. 6 304) comprising a fixed current source configured in parallel with the voltage regulator between a load (Fig. 6 204) and the power rail; and a switch (Fig. 6 switch in series with 304) configured between the fixed current source and the load, the switch responsive to transitions (Fig. 5 transitions input to buffer creating the TXP transitions) in a binary data sequence (Fig. 5 INP) applied to the load. Lam discloses a fixed current source and remains silent as to implementing an adjustable current source, which was well known at the time of filing of the invention.
Kim discloses a plurality of incremental current sources (Fig. 3C I) and a plurality of independently operable switches (Fig. 3C SW). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a plurality of incremental currents source and a plurality of independently operable switches configured between the incremental current sources and the load, the switches responsive to transitions in a binary date sequence applied to the load, in order to be able to adjust the current source to improve the transient response.
With respect to claim 13, Lam in view of Kim make obvious the circuit of claim 12, wherein the current sources comprise a current mirror (Lam paragraph 52 and Fig 3A 222a or Fig 3B 222b).
With respect to claim 14, Lam in view of Kim make obvious the circuit of claim 13, wherein the current mirror is configured to respond to digital codes (Kim Fig. 3C ICS<5:0>), each corresponding (Fig. 5 BOOST CURRENT is selected to correspond to the binary data sequence TXP).to particular transition patterns of the binary data sequence (Fig. 5 TXP).
With respect to claim 17, Lam in view of Kim make obvious the circuit of claim 12, wherein the switches are further responsive to a clock signal (Lam paragraph 55) applied to the load.
Allowable Subject Matter
Claim 21 is allowed, while Claims 4, 20 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The prior art does not disclose or suggest, primarily, a detector configured to enable or disable current to flow from the controllable current source to the load based on a switching state of a data signal and a state of a clock signal applied to the load; and a controller configured to convert a preconfigured digital code corresponding to the state of the data signal and the state of the clock signal into control signals that set an amount of the current flow provided by the controllable current source to the load.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the input signal comprises a binary data signal applied to the load; and wherein the current driver is configured to supply supplemental current to the load node in predetermined amounts based on switching activity of the data signal; and training logic configured to determine a setting for the digital code.
With respect to claim 20, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, a plurality of independently-operable switches configured between the incremental current sources and the load, the switches responsive to transitions in a binary data sequence applied to the load, wherein the switches are further responsive to a clock signal applied to the load; and a detector configured to detect both of the clock signal and the binary data sequence.
With respect to claim 22, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the input signal comprises a binary data signal applied to the load; and wherein the current driver is configured to supply supplemental current to the load node in predetermined amounts based on switching activity of the data signal; and the current driver configured to supply current to the load node in the form of pulses synchronized to a clock signal.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HARRY R BEHM/Primary Examiner, Art Unit 2838
Prosecution Insights