DETAILED ACTION Notice to Applicant The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1-20 are pending. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 , 5, 6, and 12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ahn et al. US Patent 6,446,327 . As per claims 1 , 5, 6, and 12 , Ahn et al. discloses in Fig s . 1a-1c and 2 an electronic component ( e.g. inductor 100 ) comprising: as per claim 1, a semiconductor substrate ( Col. 2 lines 40-43, substrate 103 which is formed of doped semiconductor material ) having a main surface ( e.g. bottom surface of substrate 103 ) and containing a semiconductor material ( Col. 2 lines 40-43 , silicon ) ; and a coil ( e.g. conductive segments 10 6 ) on the main surface and made of a conductive material, wherein the semiconductor substrate includes a low-resistance portion having a lower electrical resistance than a semiconductor made of the semiconductor material ( Col. 2 lines 40-43 ; S ubstrate 103 is formed of a doped semiconductor material (i.e. silicon). It is inherent that the doped material (i.e. “low resistance portion”) within the silicon (i.e. “semiconductor material”) has a lower electrical resistance than the silicon, as well-known in the art. For example, see pertinent art section below for an example of a teaching Choi et al. which exemplarily teaches that the higher the doping concentration of a silicon substrate, the more the resistance thereof decreases. ) , and the coil is electrically connected to the low-resistance portion ( Conductive segments 106 of inductor 100 are electrically connected to the dopant within the substrate 10 3 by virtue of the segments being disposed thereon , as well-known in the art. ) , and an axial direction of the coil is parallel to the main surface ( The conductive segments 106 are wrapped around a horizontal axial direction which is parallel to the bottom surface of the substrate 10 3 . ) ; as per claim 5, a first external terminal ( Fig. 1a, terminal disposed on top surface 118 that is directly connected to path 121 ) that is electrically connected to the coil and disposed along a plane parallel to the main surface ( The defined “ first external terminal” is directly c onnected to the co nductive segments 106 and are disposed along a top horizontal plane that is in parallel to the bottom surface of substrate 103 . ) ; as per claim 6, wherein the first external terminal is inside an outer edge of the main surface when viewed in a direction perpendicular to the main surface ( The defined “first external terminal” is disposed inside an edge of the top surface 118 when viewing in a vertical direction shown in Fig. 1a. ) ; and as per claim 12, wherein the semiconductor substrate is entirely configured by the low-resistance portion ( The substrate 103 is doped fully by the dopant by virtue of being a doped semiconductor substrate. ) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. US Patent 6,446,327 . As per claim 17, Ahn et al. discloses a method of manufacturing the electronic component of claim 1, comprising: forming the low-resistance portion in the semiconductor substrate; and forming the coil, but does not disclose forming the coil after forming the low-resistance portion. However, when manufacturing the inductor of Ahn et al., there are only two possibilities in the order in which the coil and the low-resistance portion are formed. The coil can either be formed before the low-resistance portion or after the low-resistance portion, as well-known in the art. Before the effective filing date, it would have been obvious to one of ordinary skill in the art at the time of manufacture to have formed the coil of Ahn et al. either after or before the low-resistance portion, such as for example after the low-resistance portion, as being an obvious design consideration based on yielding expected results as known in the art. Allowable Subject Matter Claim s 2-4, 7- 11 , 13-1 6 , and 18 - 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Pertinent Art The following reference is an example of an exemplary teaching for an assertion made by the Examiner above: Choi et al. US 2006/0246660 exemplarily teaches in Fig. 1a and Paragraph 49 a silicon substrate 101, and that the higher the doping concentration of the silicon substrate, the more the resistance thereof decreases . Thus, the dopant necessarily has a lower resistance than the silicon by virtue of the resistance decreasing when adding the dopant thereof. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT RAKESH PATEL whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-0961 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9AM-5PM EST M-F . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAKESH B PATEL/ Primary Examiner, Art Unit 2843