Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 6, 13, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments, see pg. 7 of applicant’s arguments, filed 06/05/2026, with respect to the rejection(s) of claim(s) 1-5, 7-12, and 14-19 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chid.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7, 11-12, 15, 18-19 are rejected under 35 USC 103 in view of Chidambaram Nachiappan (US Pub US 20200050379 A1, herein referred to as “Chid”) in view of Tang et al. (US 5748203 A).
As per claim 1, Chid teaches the claimed:
1. An apparatus comprising:
a control circuit, wherein responsive to a condition being satisfied for changing one or more operating parameters of a memory subsystem, (Chid fig. 1 shows a control circuit and conditions being satisfied for changing operation parameters, e.g. please see figure 4 where operating parameters include factors such as bandwidth requirements, storage space limits and monitoring transactions for multiple sources for a memory subsystem).
the control circuit is configured to:
send a first indication distinct from memory access transactions (Chid fig. 6, the first indication corresponds to “Bandwidth Requirements for Sources 640” or “Bandwidth Requirement Thresholds 642”).
to a communication fabric that causes an increase in memory bandwidth (Chid [0049]: “Other factors reported by one or more of hardware resources 260-280, kernel subsystem 230 and dynamic behavior monitor 244 that indicate changes in bandwidth requirements of hardware resources 260-280 include availability of hardware resources 260-280 in the computing system”. In this passage, Chid does not mention an increase per se however it is obvious that a change in bandwidth would be either an increase or decrease. Thus, the claimed feature is obvious to one of ordinary skill in the art. Also, please see Chid in figure 4 where bandwidth is changed in step 410.),
of the memory subsystem, allocated to a display controller (Chid [0028]: “Endpoints 140-150 are representative of any number and type of components coupled to fabric 130. For example, in some embodiments, endpoints 140-150 include one or more cameras, flash controllers, display controllers, media controllers, graphics units, communication interfaces such as radio communication interfaces, and/or other devices”).
send a second indication to the display controller which causes the display controller to prefetch display data from the memory subsystem (Chid fig. 1 shows endpoints 140-150 which may include a display controller for displaying data from the memory subsystem.)
Chid alone does not teach the remaining claim feature.
However, Chid in combination with Tang teaches the claimed:
which causes the display controller to prefetch display data from the memory subsystem (Tang teaches prefetching in col 3, lines 35-39: “The control signals for the main memory 31 generated by the display controller 34 include prefetch of display data, access and refresh for the central processing unit and so on.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the prefetch of graphical display data as taught by Tang with the system of Chid in order improve the speed and performance of display data for the display controller.
As per claims 8 and 15, these claims are similar in scope to limitations recited in claim 1, and thus are rejected under the same rationale.
As per claim 4, Chid teaches the claimed:
4. The apparatus as recited in claim 1, wherein the control circuit is further configured to send a third indication that causes a decrease in memory bandwidth allocated to the display controller (Chid [0049]: “Other factors reported by one or more of hardware resources 260-280, kernel subsystem 230 and dynamic behavior monitor 244 that indicate changes in bandwidth requirements of hardware resources 260-280 include availability of hardware resources 260-280 in the computing system”. In this passage, Chid does not mention a decrease per se. However, it is obvious that a change in bandwidth would be either an increase or decrease. Thus, the claimed feature is obvious to one of ordinary skill in the art. Also, please see Chid in figure 4 where bandwidth is changed in step 410.).
As per claims 11 and 18, these claims are similar in scope to limitations recited in claim 4, and thus are rejected under the same rationale.
As per claim 5, Chid alone does not teach the claimed.
Chid in combination with Tang teaches the claimed:
The apparatus as recited in claim 4, wherein the control circuit is configured to convey the third indication responsive to the display controller completing the prefetch of the display data from the memory subsystem. (Tang col. 4 lines 25-32: “Another situation is shown in FIG. 4. The arbiter stops the grant signal VGAGNT# at E after the display controller 34 stops the request signal VGAREQ#, i.e., after the cycle of display data prefetch is ended at D. Thereafter, the refresh operation may proceed until it concludes at F. That is, refresh occurs after the display controller 34 ceases to request data access.” The signal being output is transmitted after the prefetch is ended. It would be obvious that ceasing the request for data access would decrease the bandwidth allocated to the display controller.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the indication of the end of the prefetch taught by Tang with the system of Chid in order to organize and characterize the uses of memory in relation to the prefetch, including indicating when the bandwidth is reduced.
As per claims 12 and 19, these claims are similar in scope to limitations recited in claim 1, and thus are rejected under the same rationale.
As per claim 7, Chid teaches the claimed:
7. The apparatus as recited in claim 1, wherein the one or more operating parameters include a power state change of the memory subsystem (Chid teaches of P-state changes of the memory subsystem, e.g. Chid [0030]: “…In some embodiments, logic local to various components control the power states of the components, including power up and power down and various other power-performance states (P-states) and operating modes for those components that support more than one P-state and operating mode. In various embodiments, the P-state is used to determine the operational voltage and operational frequency used by a component, whereas the operating mode determines how many sub-components are powered up such as particular execution pipelines.”).
Claims 2-3, 9, and 16 are rejected under 35 USC 103 over Chid in view of Tang in further view of Ray (Pub No. US 20230014565 A1).
As per claim 2, Chid alone does not explicitly teach the claimed limitations.
However, Chid in combination with Ray teaches the remaining claim limitations
2. the apparatus as recited in claim 1, wherein the second indication causes a change to one or more arbitration attributes associated with memory requests generated by one or more computing clients. (Ray [0403]: “The memory access circuitry can then submit a memory access request to the L1 cache with the arbitrated cache attributes (3109). The arbitrated cache attributes are the L1 and L3 cache attributes that are selected from multiple sources based in source priority”. The attributes are used to make memory requests. Ray [0404]: “FIG. 32 illustrates a method 3200 of determining L3 cache attributes for memory requests, according to an embodiment. In one embodiment, the method 3200 is performed by cache control logic associated with an L3 cache of a graphics processor or compute accelerator.” Ray teaches that it can be configured for multiple clients. Ray [0147]: “In one embodiment, each graphics processing engine 431-432, N may be presented to the hypervisor 496 as a distinct graphics processor device. QoS settings can be configured for clients of a specific graphics processing engine 431-432, N and data isolation”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the change arbitration attributes associated with memory requests from different as taught by Ray with the system of Chid in order to control the organize and characterize the uses of the memory taught by Khoury to organize them and control them.
As per claims 9 and 16, these claims are similar in scope to limitations recited in claim 2, and thus are rejected under the same rationale.
As per claim 3, Chid alone does not explicitly teach the claimed limitations.
However, Chid in combination with Ray teaches the remaining claim limitations
Ray teaches the apparatus as recited in claim 2, wherein the arbitration attributes include a priority level (Ray [0383]: “The priority associated with prefetch operations indicates a pre-configured likelihood that prefetched data will be selected for eviction by the L1 cache replacement algorithm based on the rate or frequency in which the prefetched data is accessed. In one embodiment, the cacheability attribute for prefetched data determines the cache replacement policy that is used when determining whether to evict that data, with multiple cache replacement policies being active for different sets of cache lines.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the priority levels of the attributes of memory requests as taught by Ray with the system of Chid in order to use the characteristics of the request to give different ones more importance of others based on various characteristics and perform the requested tasks in an optimized manner.
Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chid in view of Tang and in further view of Ray and further in view of Fukami (Pub No. US 10423558 B1).
As per claim 10, Chid alone does not explicitly teach the claimed limitations.
However, Chid in combination with Fukami teaches the remaining claim limitations
the method as recited in claim 9, wherein the arbitration attributes include a size of the data (Fukami col. 6 lines 7-16: “an application identifier or type, such as a real-time application, an indication of traffic type, such as real-time traffic or low latency traffic or bulk traffic, a bandwidth requirement or a latency tolerance requirement, and an indication of a data size associated with the request and so forth. Similarly, data selection logic 196 in control and data arbiters 138 selects the write data of the write request among other data transactions based on one or more of a priority level, age, data size of the write data, and so forth.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the size of the data as taught by Fukami with the system of Chid modified by Ray in order Measure the size of the data in the system to prioritize the data to be processed an allocate the proper resources to them.
Regarding claim 17 Chid alone does not explicitly teach the claimed limitations.
However, Chid in combination with Fukami teaches the remaining claim limitations
The computing system as recited in claim 16, wherein the arbitration attributes include a source identifier of the data. (Fukami in col. 6 lines 5-15: “Control selection logic 192 in control and data arbiters 138 selects the write command among other commands and messages based on attributes that include one or more of an age, a priority level, a quality-of-service parameter, a source identifier, an application identifier or type, such as a real-time application, an indication of traffic type, such as real-time traffic or low latency traffic or bulk traffic, a bandwidth requirement or a latency tolerance requirement, and an indication of a data size associated with the request and so forth. Similarly, data selection logic 196 in control and data arbiters 138 selects the write data of the write request among other data transactions based on one or more of a priority level, age, data size of the write data, and so forth”. The control selection logic different attributes to arbitrate write commands to memory. Along with age, priority level, and application identifier, a source identifier is one of the attributes used.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a source identifier for memory requests as taught by Fukami with the system of Chid in order to control the change the structure of the memory request based on its source, or the client the request came from.
Conclusion
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/THOMAS JOHN FOSTER/Examiner, Art Unit 2616
/DANIEL F HAJNIK/Supervisory Patent Examiner, Art Unit 2616
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