DETAILED ACTION
Claims 1-20 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 U.S.C. § 101
35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The invention, as taught in Claims 1-20, is directed to “mental steps” and “mathematical steps” without significantly more.
The claims recite:
• the data flow graph includes a first operator having an input tensor and an output tensor (i.e., the graph is mental steps)
• transforming the data flow graph, wherein transforming the data flow graph includes transforming the first operator into a set of operators that are functionally equivalent to the first operator (i.e., mental steps)
• assigning each operator in the set of operators to a computing device from a plurality of computing devices that are part of an execution environment configured to execute the NN model (i.e., mental steps)
Claim 1
Step 1 inquiry: Does this claim fall within a statutory category?
The preamble of the claim recites “1. A system for generating a parallelization plan for a Neural Network (NN) model comprising…” Therefore, it is a “system” (or “apparatus”), which is a statutory category of invention. Therefore, the answer to the inquiry is: “YES.”
Step 2A (Prong One) inquiry:
Are there limitations in Claim 1 that recite abstract ideas?
YES. The following limitations in Claim 1 recite abstract ideas that fall within at least one of the groupings of abstract ideas enumerated in the 2019 PEG. Specifically, they are “mental steps” and “mathematical steps”:
• the data flow graph includes a first operator having an input tensor and an output tensor (i.e., the graph is mental steps)
• transforming the data flow graph, wherein transforming the data flow graph includes transforming the first operator into a set of operators that are functionally equivalent to the first operator (i.e., mental steps)
• assigning each operator in the set of operators to a computing device from a plurality of computing devices that are part of an execution environment configured to execute the NN model (i.e., mental steps)
Step 2A (Prong Two) inquiry:
Are there additional elements or a combination of elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception?
Applicant’s claims contain the following “additional elements”:
(1) A processor (i.e., “one or more processors”/“an execution environment configured to execute the NN model”)
(2) A “non-transitory computer-readable medium storing a program executable by the one or more processors”
(3) A “receiving a data flow graph representing the NN model”
A “processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “processor” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
A “non-transitory computer-readable medium storing a program executable by the one or more processors” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “non-transitory computer-readable medium storing a program executable by the one or more processors” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
A “receiving a data flow graph representing the NN model” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “receiving a data flow graph representing the NN model” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. It merely receives data before the actual solution activity starts (i.e., pre-solution activity). (See, M.P.E.P. § 2106.05(g).
The answer to the inquiry is “NO”, no additional elements integrate the claimed abstract idea into a practical application.
Step 2B inquiry:
Does the claim provide an inventive concept, i.e., does the claim recite additional element(s) or a combination of elements that amount to significantly more than the judicial exception in the claim?
Applicant’s claims contain the following “additional elements”:
(1) A processor (i.e., “one or more processors”/“an execution environment configured to execute the NN model”)
(2) A “non-transitory computer-readable medium storing a program executable by the one or more processors”
(3) A “receiving a data flow graph representing the NN model”
A “processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05 (I)(A)(i-ii) recites:
Limitations that the courts have found not to be enough to qualify as “significantly more” when recited in a claim with a judicial exception include:
i. Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, e.g., a limitation indicating that a particular function such as creating and maintaining electronic records is performed by a computer, as discussed in Alice Corp., 573 U.S. at 225-26, 110 USPQ2d at 1984 (see MPEP § 2106.05(f));
ii. Simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, e.g., a claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry, as discussed in Alice Corp., 573 U.S. at 225, 110 USPQ2d at 1984 (see MPEP § 2106.05(d));
Further, M.P.E.P. § 2016.05(f) recites:
2106.05(f) Mere Instructions To Apply An Exception [R-10.2019]
Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”).
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
The processor is well-understood, routine, and conventional. Applicant's Specification recites:
[0015] In some embodiments, a computing system is configured to generate a parallelization plan for a NN, such as a DNN. With the growing model size, DNNs are commonly trained over multiple computing devices that belong to an execution environment. These multiple computing devices may be a central processing unit (CPU), a graphics processing unit (GPU), other processor, or a combination of the above such as a GPU accelerator which is a combination of a GPU in addition to a CPU. In some embodiments, the computing system generates the parallelization plan based on a data flow graph (DFG) representation of the NN model. The parallelization plan may first transform the DFG into fine-grained tasks and then schedule these tasks to the multiple computing devices within the execution environment for execution. This transformation and scheduling of the DFG on multiple computing devices is a parallelization plan. The DFG may express the architecture of a NN model in terms of operators such as matrix multiplication. Each node in the DFG is an operator and each edge corresponds to the input and output data for each node. In some embodiments, each edge is a tensor capable of storing data that is output from one operator and used as input to another operator. The computing system may generate a parallelization plan in the form of a transformed DFG where the transformed DFG contains partitioned operators that may be assigned to different computing devices in the execution environment.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
A “a non-transitory computer-readable medium storing a program executable by the one or more processors” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
A “receiving a data flow graph representing the NN model” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
Therefore, the answer to the inquiry is “NO”, no additional elements provide an inventive concept that is significantly more than the claimed abstract ideas the claimed abstract idea into a practical application.
Claim 1 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 2
Claim 2 recites:
2. The system of claim 1, wherein transforming the data flow graph further includes generating, for each operator in the set of operators, a virtual input tensor that links to the input tensor and a virtual output tensor that links to the output tensor.
Applicant’s Claim 2 merely teaches mathematical calculation of tensors (i.e., mathematical steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 2 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 3
Claim 3 recites:
3. The system of claim 2, wherein the virtual input tensor includes an input mask representing a portion of the input tensor that an operator from the set of operators accesses.
Applicant’s Claim 3 merely teaches mathematical calculation of tensors (i.e., mathematical steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 3 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 4
Claim 4 recites:
4. The system of claim 3, wherein the virtual output tensor includes an output mask representing a portion of the output tensor that the operator from the set of operators accesses.
Applicant’s Claim 4 merely teaches mathematical calculation of tensors (i.e., mathematical steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 4 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 5
Claim 5 recites:
5. The system of claim 4, wherein the program further comprises sets of instructions for:
identifying a plurality of virtual input tensors that are linked to the input tensor and a plurality of virtual output tensors that are linked to the input tensor; and
determining a data dependency exists between a first virtual input tensor from the plurality of virtual input tensors and a first virtual output tensor from the plurality of virtual output tensors.
Applicant’s Claim 5 merely teaches “identifying” and “determining” steps that are mental steps. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 5 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 6
Claim 6 recites:
6. The system of claim 5, wherein data dependency is determined when there is an overlap between the masks of the first virtual input tensor and the first virtual output tensor.
Applicant’s Claim 6 merely teaches mathematical calculation of an “overlap” and mental step of “determining” a data dependency. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 6 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 7
Claim 7 recites:
7. The system of claim 5, wherein the program further comprises sets of instructions for determining an execution order for the set of operators based on the data dependency.
Applicant’s Claim 7 merely teaches “sets of instructions for determining an execution order” (i.e., mental steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 7 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 8
Claim 8 recites:
8. The system of claim 5, wherein the first virtual input tensor is stored in a first computing device and the first virtual output tensor is stored in a second computing device, and wherein the program further comprises sets of instructions for sending a portion of the first virtual output tensor from the second computing device to the first computing device based on the data dependency.
Applicant’s Claim 8 merely teaches well-understood, routine and conventional storage of mathematical data (see, M.P.E.P. citation about this in the independent claim) and sets of program instructions. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 8 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 9
Claim 9 recites:
9. The system of claim 8, wherein the portion based on the overlap.
Applicant’s Claim 9 merely teaches mathematical determination of “overlap”. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 9 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 10
Claim 10 recites:
10. The system of claim 1, wherein transforming the first operator comprises partitioning the first operator into the set of operators based on a batch dimension of the first operator and a count of the plurality of computing devices when the first operator is a forward operation.
Applicant’s Claim 10 merely teaches the mental step of “partitioning”. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 10 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 11
Claim 11 recites:
11. The system of claim 1, wherein transforming the first operator comprises replicating the first operator into the set of operators when the first operator is not a forward operation.
Applicant’s Claim 11 merely teaches the mathematical step of “replicating” an “operator”. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 11 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 12
Step 1 inquiry: Does this claim fall within a statutory category?
The preamble of the claim recites “12. A method for generating a parallelization plan for a Neural Network (NN) model comprising…” Therefore, it is a “method” (or “process”), which is a statutory category of invention. Therefore, the answer to the inquiry is: “YES.”
Step 2A (Prong One) inquiry:
Are there limitations in Claim 12 that recite abstract ideas?
YES. The following limitations in Claim 12 recite abstract ideas that fall within at least one of the groupings of abstract ideas enumerated in the 2019 PEG. Specifically, they are “mental steps” and “mathematical steps”:
• the data flow graph includes a first operator having an input tensor and an output tensor (i.e., the graph is mental steps)
• transforming the data flow graph, wherein transforming the data flow graph includes transforming the first operator into a set of operators that are functionally equivalent to the first operator (i.e., mental steps)
• assigning each operator in the set of operators to a computing device from a plurality of computing devices that are part of an execution environment configured to execute the NN model (i.e., mental steps)
Step 2A (Prong Two) inquiry:
Are there additional elements or a combination of elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception?
Applicant’s claims contain the following “additional elements”:
(1) A processor (i.e., “one or more processors”/“an execution environment configured to execute the NN model”)
(2) A “receiving a data flow graph representing the NN model”
A “processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “processor” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
A “receiving a data flow graph representing the NN model” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “receiving a data flow graph representing the NN model” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. It merely receives data before the actual solution activity starts (i.e., pre-solution activity). (See, M.P.E.P. § 2106.05(g).
The answer to the inquiry is “NO”, no additional elements integrate the claimed abstract idea into a practical application.
Step 2B inquiry:
Does the claim provide an inventive concept, i.e., does the claim recite additional element(s) or a combination of elements that amount to significantly more than the judicial exception in the claim?
Applicant’s claims contain the following “additional elements”:
(1) A processor (i.e., “one or more processors”/“an execution environment configured to execute the NN model”)
(2) A “receiving a data flow graph representing the NN model”
A “processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05 (I)(A)(i-ii) recites:
Limitations that the courts have found not to be enough to qualify as “significantly more” when recited in a claim with a judicial exception include:
i. Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, e.g., a limitation indicating that a particular function such as creating and maintaining electronic records is performed by a computer, as discussed in Alice Corp., 573 U.S. at 225-26, 110 USPQ2d at 1984 (see MPEP § 2106.05(f));
ii. Simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, e.g., a claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry, as discussed in Alice Corp., 573 U.S. at 225, 110 USPQ2d at 1984 (see MPEP § 2106.05(d));
Further, M.P.E.P. § 2016.05(f) recites:
2106.05(f) Mere Instructions To Apply An Exception [R-10.2019]
Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”).
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
The processor is well-understood, routine, and conventional. Applicant's Specification recites:
[0015] In some embodiments, a computing system is configured to generate a parallelization plan for a NN, such as a DNN. With the growing model size, DNNs are commonly trained over multiple computing devices that belong to an execution environment. These multiple computing devices may be a central processing unit (CPU), a graphics processing unit (GPU), other processor, or a combination of the above such as a GPU accelerator which is a combination of a GPU in addition to a CPU. In some embodiments, the computing system generates the parallelization plan based on a data flow graph (DFG) representation of the NN model. The parallelization plan may first transform the DFG into fine-grained tasks and then schedule these tasks to the multiple computing devices within the execution environment for execution. This transformation and scheduling of the DFG on multiple computing devices is a parallelization plan. The DFG may express the architecture of a NN model in terms of operators such as matrix multiplication. Each node in the DFG is an operator and each edge corresponds to the input and output data for each node. In some embodiments, each edge is a tensor capable of storing data that is output from one operator and used as input to another operator. The computing system may generate a parallelization plan in the form of a transformed DFG where the transformed DFG contains partitioned operators that may be assigned to different computing devices in the execution environment.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
A “receiving a data flow graph representing the NN model” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
Therefore, the answer to the inquiry is “NO”, no additional elements provide an inventive concept that is significantly more than the claimed abstract ideas the claimed abstract idea into a practical application.
Claim 12 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 13
Claim 13 recites:
13. The method of claim 12, wherein the virtual input tensor includes an input mask representing a portion of the input tensor that an operator from the set of operators accesses and an output mask representing a portion of the output tensor that the operator from the set of operators accesses.
Applicant’s Claim 13 merely teaches mathematical tensors (i.e., mathematical steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 13 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 14
Claim 14 recites:
14. The method of claim 13, further comprising:
identifying a plurality of virtual input tensors that are linked to the input tensor and a plurality of virtual output tensors that are linked to the input tensor; and
determining a data dependency exists between a first virtual input tensor from the plurality of virtual input tensors and a first virtual output tensor from the plurality of virtual output tensors.
Applicant’s Claim 14 merely teaches “identifying” and “determining” steps that are mental steps. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 14 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 15
Claim 15 recites:
15. The method of claim 14, wherein data dependency is determined when there is an overlap between the masks of the first virtual input tensor and the first virtual output tensor.
Applicant’s Claim 15 merely teaches mathematical calculation of an “overlap” and mental step of “determining” a data dependency. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 15 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 16
Claim 16 recites:
16. The method of claim 14, wherein the program further comprises sets of instructions for determining an execution order for the set of operators based on the data dependency.
Applicant’s Claim 16 merely teaches “sets of instructions for determining an execution order” (i.e., mental steps). It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 16 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 17
Claim 17 recites:
17. The method of claim 14, wherein the first virtual input tensor is stored in a first computing device and the first virtual output tensor is stored in a second computing device, and wherein the program further comprises sets of instructions for sending a portion of the first virtual output tensor from the second computing device to the first computing device based on the data dependency.
Applicant’s Claim 17 merely teaches well-understood, routine and conventional storage of mathematical data (see, M.P.E.P. citation about this in the independent claim) and sets of program instructions. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 17 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 18
Claim 18 recites:
18. The method of claim 12, wherein transforming the first operator comprises partitioning the first operator into the set of operators based on a batch dimension of the first operator and a count of the plurality of computing devices when the first operator is a forward operation.
Applicant’s Claim 18 merely teaches the mental step of “partitioning”. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 18 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 19
Claim 19 recites:
19. The method of claim 12, wherein transforming the first operator comprises replicating the first operator into the set of operators when the first operator is not a forward operation.
Applicant’s Claim 19 merely teaches the mathematical step of “replicating” an “operator”. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 19 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 20
Step 1 inquiry: Does this claim fall within a statutory category?
The preamble of the claim recites “20. A non-transitory computer-readable medium storing a program executable by one or more processors, the program comprising sets of instructions for…” Therefore, it is a “non-transitory computer-readable medium” (or “product of manufacture”), which is a statutory category of invention. Therefore, the answer to the inquiry is: “YES.”
Step 2A (Prong One) inquiry:
Are there limitations in Claim 20 that recite abstract ideas?
YES. The following limitations in Claim 20 recite abstract ideas that fall within at least one of the groupings of abstract ideas enumerated in the 2019 PEG. Specifically, they are “mental steps” and “mathematical steps”:
• the data flow graph includes a first operator having an input tensor and an output tensor (i.e., the graph is mental steps)
• transforming the data flow graph, wherein transforming the data flow graph includes transforming the first operator into a set of operators that are functionally equivalent to the first operator (i.e., mental steps)
• assigning each operator in the set of operators to a computing device from a plurality of computing devices that are part of an execution environment configured to execute the NN model (i.e., mental steps)
Step 2A (Prong Two) inquiry:
Are there additional elements or a combination of elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception?
Applicant’s claims contain the following “additional elements”:
(1) A processor (i.e., “one or more processors”/“an execution environment configured to execute the NN model”)
(2) A “non-transitory computer-readable medium storing a program executable by the one or more processors”
(3) A “receiving a data flow graph representing the NN model”
A “processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “processor” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
A “non-transitory computer-readable medium storing a program executable by the one or more processors” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “non-transitory computer-readable medium storing a program executable by the one or more processors” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
A “receiving a data flow graph representing the NN model” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “receiving a data flow graph representing the NN model” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. It merely receives data before the actual solution activity starts (i.e., pre-solution activity). (See, M.P.E.P. § 2106.05(g).
The answer to the inquiry is “NO”, no additional elements integrate the claimed abstract idea into a practical application.
Step 2B inquiry:
Does the claim provide an inventive concept, i.e., does the claim recite additional element(s) or a combination of elements that amount to significantly more than the judicial exception in the claim?
Applicant’s claims contain the following “additional elements”:
(1) A processor (i.e., “one or more processors”/“an execution environment configured to execute the NN model”)
(2) A “non-transitory computer-readable medium storing a program executable by the one or more processors”
(3) A “receiving a data flow graph representing the NN model”
A “processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05 (I)(A)(i-ii) recites:
Limitations that the courts have found not to be enough to qualify as “significantly more” when recited in a claim with a judicial exception include:
i. Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, e.g., a limitation indicating that a particular function such as creating and maintaining electronic records is performed by a computer, as discussed in Alice Corp., 573 U.S. at 225-26, 110 USPQ2d at 1984 (see MPEP § 2106.05(f));
ii. Simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, e.g., a claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry, as discussed in Alice Corp., 573 U.S. at 225, 110 USPQ2d at 1984 (see MPEP § 2106.05(d));
Further, M.P.E.P. § 2016.05(f) recites:
2106.05(f) Mere Instructions To Apply An Exception [R-10.2019]
Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”).
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
The processor is well-understood, routine, and conventional. Applicant's Specification recites:
[0015] In some embodiments, a computing system is configured to generate a parallelization plan for a NN, such as a DNN. With the growing model size, DNNs are commonly trained over multiple computing devices that belong to an execution environment. These multiple computing devices may be a central processing unit (CPU), a graphics processing unit (GPU), other processor, or a combination of the above such as a GPU accelerator which is a combination of a GPU in addition to a CPU. In some embodiments, the computing system generates the parallelization plan based on a data flow graph (DFG) representation of the NN model. The parallelization plan may first transform the DFG into fine-grained tasks and then schedule these tasks to the multiple computing devices within the execution environment for execution. This transformation and scheduling of the DFG on multiple computing devices is a parallelization plan. The DFG may express the architecture of a NN model in terms of operators such as matrix multiplication. Each node in the DFG is an operator and each edge corresponds to the input and output data for each node. In some embodiments, each edge is a tensor capable of storing data that is output from one operator and used as input to another operator. The computing system may generate a parallelization plan in the form of a transformed DFG where the transformed DFG contains partitioned operators that may be assigned to different computing devices in the execution environment.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
A “a non-transitory computer-readable medium storing a program executable by the one or more processors” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
A “receiving a data flow graph representing the NN model” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
Therefore, the answer to the inquiry is “NO”, no additional elements provide an inventive concept that is significantly more than the claimed abstract ideas the claimed abstract idea into a practical application.
Claim 20 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 U.S.C. § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 12, and 20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Chen, et al., Multiply Accumulate Operations in Memristor Crossbar Arrays for Analog Computing, Journal of Semiconductors, 2021, Vol.: 42, Issue: 1, pp. 1-23, in its entirety. Specifically:
Claim 1
Claim 1’s “one or more processors” is anticipated by Chen, et al., page 17, right column, first full paragraph, where it recites:
Taking advantage of sparsity, the matrix slice processor has shown a good potential to process a giant sparse matrix by using multiply small-scale arrays with high processing speed and low energy consumption. Combining this with the traditional bit-slice technique, a high precision solution can be obtained.
Claim 1’s “a non-transitory computer-readable medium storing a program executable by the one or more processors, the program comprising sets of instructions for” is anticipated by Chen, et al., page 5, right column, last full paragraph, where it recites:
By combining a von Neumann machine with the memristive MAC unit, the mixed-precision in-memory computing architecture already overperforms the CPU/GPU-based numerical computers in terms of the energy consumption and computation speed, with the same accuracy level to process giant non-sparse matrices. The mixed-precision system still suffers from the fact that the data needs to be stored both in the memristor array and the high-precision digital unit. Additional resources are needed to solve the problem. Although O(N2) computation time complexity can be achieved, it still depends on the matrix scale.
Claim 1’s “receiving a data flow graph representing the NN model, wherein the data flow graph includes a first operator having an input tensor and an output tensor” is anticipated by Chen, et al., page 17, right column, third full paragraph, where it recites:
With the fastest process speed and highest energy/area efficiency, the one-shot in-memory computing architecture is another good example of the powerful capability of the memristive MAC unit, and can even outperform the quantum computing accelerator in computation complexity[106]. This architecture can also satisfy the approximate solution for machine learning problems such as the linear regression and logic regression problems[107]. However, the one-shot computing requires a high performance memristive device with precise conductance programming and high I–V linearity. Moreover, the hardwired circuits at this stage limits the system reconfigurability.
Note that Applicant does not define how the data flow graph is “received”. In the prior art, it is received through hardwiring. Further, it doesn’t specify how the graph is represented.
Claim 1’s “transforming the data flow graph, wherein transforming the data flow graph includes transforming the first operator into a set of operators that are functionally equivalent to the first operator” is anticipated by Chen, et al., page 2, right column, next to last full paragraph, where it recites:
2.1. Introduction of MAC operation
MAC operation is an important and expensive operation, which is frequently used in digital signal processing and video/graphics applications for convolution, discrete cosine transform, Fourier transform, and so on[33−37]. The MAC performs multiplication and accumulation processes, which computes the product of two numbers and adds that product to an accumulator: Z = Z + A × B. Many basic operations, such as the dot product, matrix multiplication, digital filter operations, and even polynomial evaluation operations, can be decomposed (i.e., the claimed “transforming”) into MAC operations, as follows:
Note that this paragraph and equation (1), which follows the paragraph, show the dot product operation being transformed into the sum of scalar multiplications.
Claim 1’s “assigning each operator in the set of operators to a computing device from a plurality of computing devices that are part of an execution environment configured to execute the NN model” is anticipated by Chen, et al., page 2, right column, last partial paragraph and page 3, left column, first partial and first full paragraphs, where it recites:
2.2. Implementation of MAC operation in memristor array
As a powerful alternative for improving the efficiency of data-intensive task processing in the era of big data, the in-memory computing hardware solution to the computational bottleneck is essentially a manifestation of the acceleration of MAC operations. Naturally, a memristive crossbar is highly efficient at executing vector-matrix multiplication (VMM) in one step by parallel MAC operations.
As shown in Fig. 2, for a memristive array, each row and column crossing node represents a memristor. The numerical values in a matrix can be directly mapped as the analog conductance on the crossbar array. When a forward input vector V is applied in the form of voltage pulses with different pulse amplitudes or widths to the rows, the currents collected at the columns result from the MAC operation between the input voltages and corresponding conductance nodes, following Ohm’s law and Kirchhoff’s current law. Thus, the array implements a one-step calculation of the VMM. The same goes for backpropagation. In other words, the VMM operation could be efficiently performed with O(1) time complexity.
Claim 12
Claim 12’s “receiving a data flow graph representing the NN model, wherein the data flow graph includes a first operator having an input tensor and an output tensor” is anticipated by Chen, et al., page 17, right column, third full paragraph, where it recites:
With the fastest process speed and highest energy/area efficiency, the one-shot in-memory computing architecture is another good example of the powerful capability of the memristive MAC unit, and can even outperform the quantum computing accelerator in computation complexity[106]. This architecture can also satisfy the approximate solution for machine learning problems such as the linear regression and logic regression problems[107]. However, the one-shot computing requires a high performance memristive device with precise conductance programming and high I–V linearity. Moreover, the hardwired circuits at this stage limits the system reconfigurability.
Note that Applicant does not define how the data flow graph is “received”. In the prior art, it is received through hardwiring. Further, it doesn’t specify how the graph is represented.
Claim 12’s “transforming the data flow graph, wherein transforming the data flow graph includes transforming the first operator into a set of operators that are functionally equivalent to the first operator” is anticipated by Chen, et al., page 2, right column, next to last full paragraph, where it recites:
2.1. Introduction of MAC operation
MAC operation is an important and expensive operation, which is frequently used in digital signal processing and video/graphics applications for convolution, discrete cosine transform, Fourier transform, and so on[33−37]. The MAC performs multiplication and accumulation processes, which computes the product of two numbers and adds that product to an accumulator: Z = Z + A × B. Many basic operations, such as the dot product, matrix multiplication, digital filter operations, and even polynomial evaluation operations, can be decomposed (i.e., the claimed “transforming”) into MAC operations, as follows:
Note that this paragraph and equation (1), which follows the paragraph, show the dot product operation being transformed into the sum of scalar multiplications.
Claim 12’s “assigning each operator in the set of operators to a computing device from a plurality of computing devices that are part of an execution environment configured to execute the NN model” is anticipated by Chen, et al., page 2, right column, last partial paragraph and page 3, left column, first partial and first full paragraphs, where it recites:
2.2. Implementation of MAC operation in memristor array
As a powerful alternative for improving the efficiency of data-intensive task processing in the era of big data, the in-memory computing hardware solution to the computational bottleneck is essentially a manifestation of the acceleration of MAC operations. Naturally, a memristive crossbar is highly efficient at executing vector-matrix multiplication (VMM) in one step by parallel MAC operations.
As shown in Fig. 2, for a memristive array, each row and column crossing node represents a memristor. The numerical values in a matrix can be directly mapped as the analog conductance on the crossbar array. When a forward input vector V is applied in the form of voltage pulses with different pulse amplitudes or widths to the rows, the currents collected at the columns result from the MAC operation between the input voltages and corresponding conductance nodes, following Ohm’s law and Kirchhoff’s current law. Thus, the array implements a one-step calculation of the VMM. The same goes for backpropagation. In other words, the VMM operation could be efficiently performed with O(1) time complexity.
Claim 20
Claim 20’s “receiving a data flow graph representing the NN model, wherein the data flow graph includes a first operator having an input tensor and an output tensor” is anticipated by Chen, et al., page 17, right column, third full paragraph, where it recites:
With the fastest process speed and highest energy/area efficiency, the one-shot in-memory computing architecture is another good example of the powerful capability of the memristive MAC unit, and can even outperform the quantum computing accelerator in computation complexity[106]. This architecture can also satisfy the approximate solution for machine learning problems such as the linear regression and logic regression problems[107]. However, the one-shot computing requires a high performance memristive device with precise conductance programming and high I–V linearity. Moreover, the hardwired circuits at this stage limits the system reconfigurability.
Note that Applicant does not define how the data flow graph is “received”. In the prior art, it is received through hardwiring. Further, it doesn’t specify how the graph is represented.
Claim 20’s “transforming the data flow graph, wherein transforming the data flow graph includes transforming the first operator into a set of operators that are functionally equivalent to the first operator” is anticipated by Chen, et al., page 2, right column, next to last full paragraph, where it recites:
2.1. Introduction of MAC operation
MAC operation is an important and expensive operation, which is frequently used in digital signal processing and video/graphics applications for convolution, discrete cosine transform, Fourier transform, and so on[33−37]. The MAC performs multiplication and accumulation processes, which computes the product of two numbers and adds that product to an accumulator: Z = Z + A × B. Many basic operations, such as the dot product, matrix multiplication, digital filter operations, and even polynomial evaluation operations, can be decomposed (i.e., the claimed “transforming”) into MAC operations, as follows:
Note that this paragraph and equation (1), which follows the paragraph, show the dot product operation being transformed into the sum of scalar multiplications.
Claim 20’s “assigning each operator in the set of operators to a computing device from a plurality of computing devices that are part of an execution environment configured to execute the NN model” is anticipated by Chen, et al., page 2, right column, last partial paragraph and page 3, left column, first partial and first full paragraphs, where it recites:
2.2. Implementation of MAC operation in memristor array
As a powerful alternative for improving the efficiency of data-intensive task processing in the era of big data, the in-memory computing hardware solution to the computational bottleneck is essentially a manifestation of the acceleration of MAC operations. Naturally, a memristive crossbar is highly efficient at executing vector-matrix multiplication (VMM) in one step by parallel MAC operations.
As shown in Fig. 2, for a memristive array, each row and column crossing node represents a memristor. The numerical values in a matrix can be directly mapped as the analog conductance on the crossbar array. When a forward input vector V is applied in the form of voltage pulses with different pulse amplitudes or widths to the rows, the currents collected at the columns result from the MAC operation between the input voltages and corresponding conductance nodes, following Ohm’s law and Kirchhoff’s current law. Thus, the array implements a one-step calculation of the VMM. The same goes for backpropagation. In other words, the VMM operation could be efficiently performed with O(1) time complexity.
Reasons Why the Dependent Clams are Not Rejected
The following is an Examiner's statement of reasons why the dependent clams are not rejected: Claims 2-11 and 13-19 are considered allowable since when reading the claims in light of the specification, as per MPEP § 2111.01, none of the references of record, whether taken alone or in combination, discloses or suggests the combination of limitations specified in independent Claims 2-9 and 14-17. Specifically:
Claims 2-9 and 14-17's "...virtual output tensor..."
Further, none of the references of record, whether taken alone or in combination, discloses or suggests the combination of limitations specified in independent Claim 10 and 18. Specifically:
Claim 10 and 18's "...partitioning the first operator..."
Further, none of the references of record, whether taken alone or in combination, discloses or suggests the combination of limitations specified in independent Claim 11 and 19. Specifically:
Claim 11 and 19's "...replicating the first operator into the set of operators when the first operator is not a forward operation..."
Only to the extent that these limitations (specifically as defined above) are not found in the prior art of record are those claims not rejected under the prior art.
Conclusion
Any inquiries concerning this communication or earlier communications from the examiner should be directed to Wilbert L. Starks, Jr., who may be reached Monday through Friday, between 8:00 a.m. and 5:00 p.m. EST. or via telephone at (571) 272-3691 or email: Wilbert.Starks@uspto.gov.
If you need to send an Official facsimile transmission, please send it to (571) 273-8300.
If attempts to reach the examiner are unsuccessful the Examiner’s Supervisor (SPE), Kakali Chaki, may be reached at (571) 272-3719.
Hand-delivered responses should be delivered to the Receptionist @ (Customer Service Window Randolph Building 401 Dulany Street, Alexandria, VA 22313), located on the first floor of the south side of the Randolph Building.
Finally, information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Moreover, status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have any questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) toll-free @ 1-866-217-9197.
/WILBERT L STARKS/
Primary Examiner, Art Unit 2122
WLS
22 MAR 2026
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