Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
This action is in response to Applicant’s amendments filed 19 January 2026. Claims 1-16 were previously pending. Claims 1, 4, 7, 8, 9, 12, and 13 have been amended according to Applicant’s amendments. Claim 11 has been cancelled. No new claims have been added. Accordingly, claims 1-10 and 12-16 remain pending and under consideration.
Response to Arguments
35 USC 112 –
Applicant's arguments, see remarks pages 9 and 10, filed 19 January 2026, with respect to the interpretation of claim 1 under 35 USC 112(f), and more particularly, the amendment of detection engine to detection circuit adding sufficient structure, is persuasive. Accordingly, the 112(f) interpretation is withdrawn.
35 USC 103 –
Applicant’s arguments, see remarks pages 12-15, filed 19 January 2026, with respect to the rejection of claims 1-16 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Kanter, Soffer et al (US 2022/0308957 A1), Benedict, Sonnekalb, and Brueggen.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kanter et al (US 2022/0229725 A1, hereinafter Kanter) in view of Soffer et al (US 2022/0308957 A1, hereinafter Soffer), in view of Benedict (US 20160188399 A1, hereinafter Benedict), in view of Sonnekalb (US 2023/0359523 A1, hereinafter Sonnekalb), and further in view of Brueggen (US 2007/0033488 A1, hereinafter Brueggen).
Regarding claims 1, 9 and 13, taking claim 1 as exemplary, Kanter discloses a storage device comprising: a nonvolatile memory configured to store data (See Kanter, Fig. 1, and [0028], disclosing non-volatile storage device 100 having a memory array 130 including NAND flash memory); a volatile memory (See Kanter, Fig. 1, DRAM 114 and [0038] data buffered in DRAM volatile memory);
a write operation controller configured to receive a write request and a first detection value representing a first validity of data stored (See Kanter, Fig. 1, disclosing controller 110 and [0032], disclosing controller 110 executing I/O handling [0034], disclosing host interface 105 receiving a write command and data, and [0044], disclosing both user data and E3D signature appended thereto are communicated along the write data path);
a plurality of detection circuits configured to acquire, after acquiring the first detection value and before storing the data to the nonvolatile memory, a second detection value representing a second validity of the data stored and transfer the second detection value to the write operation controller (See Kanter, Fig. 3 and [0060] - [0064], disclosing controller determines validity of user data using a signature comparison including a first signature D1 and second signature D2, or in other words, a first and second detection value representing a first and second validity, and which indicates no soft errors had occurred during handling and/or processing along the read/write data path which includes a volatile DRAM data buffer and accordingly, soft errors are detected before being written to the memory array 130 – nonvolatile memory); and
an engine controller configured to control a detection circuit to acquire the second detection value after receiving the write request (See Kanter [0044], disclosing both user data and E3D signature appended thereto are communicated along the write data path and [0060] & [0063], disclosing controller determines validity of user data using a signature which indicates no soft errors had occurred during handling and/or processing along the read/write data path),
wherein the write operation controller is configured to determine whether to perform a write operation of storing the data stored into the nonvolatile memory according to the write request, based on the first detection value and the second detection value (See Kanter, Fig. 1, disclosing controller 110 and [0032], disclosing controller 110 executing I/O handling [0034], disclosing host interface 105 receiving a write command and data, [0051] & [0054], disclosing the controller receiving user data through the write data path and subsequently performing validation, and [0063], using D1 and D2 to determine validity of user write data).
Kanter does not disclose a processor configured to update data stored in a selected bank among the plurality of banks, wherein the first detection value is a detection value acquired after data stored in the selected bank of the volatile memory is updated.
However, Soffer discloses a processor configured to update data stored in a selected location, wherein the first detection value is a detection value acquired after data stored in the selected location is updated (See Soffer, Fig.1 disclosing checksum generator 126 as part of computer system 100 utilizing physical processing devices 134, and [0044], disclosing checksum generator 126 using a checksum calculation function that can be invoked repeatedly with incremental updates to the input data 152, or in other words, the “detection value” or checksum value is calculated/acquired after incremental updates to the input data).
Kanter and Soffer are analogous are directed to improved memory management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the error detection memory system of Kanter with the checksum calculation and comparison of Soffer as memory system reliability and efficiency may be increased by verifying data has correctly been copied or transferred (See Soffer, [0015]).
Neither Kanter nor Soffer discloses whether to perform a write operation based on a comparison between the first detection value and the second detection value, and to perform the write operation when the second detection value is equal to the first detection value.
However, Benedict discloses whether to perform a write operation based on a comparison between the first detection value and the second detection value, and to perform the write operation when the second detection value is equal to the first detection value (See Benedict, [0011], disclosing a memory controller generating a CRC for each data packet sent to DRAM for a write operation, the DRRAM may check for a valid CRC prior to storing the data, and if the CRC check fails, signaling for the controller to resend the data, or in other words, comparing CRCs and when equal, writing the associated data, otherwise requesting the data to be resent).
Kanter, Soffer, and Benedict are analogous art directed to improved data storage techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the error detection memory system of Kanter and Soffer with the write verification check of Bendict as memory system reliability may be further improved by ensuring data is successfully and accurately transferred between the memory controller and the memory module (See Benedict [0011], the CRC is for each data packet sent during write operations).
None of Kanter, Soffer, or Benedict disclose the volatile memory including a plurality of banks; a selected bank among the plurality of banks; the write operation controller configured to receive a first detection value representing a first validity of data stored in the selected location, a plurality of detection circuits each configured to acquire a second detection value representing validity of data stored in the selected location of the volatile memory, and the write operation controller is configured to determine whether a write operation of storing the data in the selected location into nonvolatile memory is to be performed based on the first detection value and a second detection value.
However, Sonnekalb the write operation controller configured to receive a first detection value representing validity of data stored in a selected location among the plurality of locations, detection circuits configured to acquire a second detection value representing validity of data stored in the selected location, and the write operation controller is configured to determine whether a write operation of storing the data in the selected location into nonvolatile memory is to be performed based on the first detection value and a second detection value (See Sonnekalb, Figs. 1 & 2, disclosing memory 101 containing memory locations 102, and [0013] & [0018], disclosing a memory area 108 respectively storing error detection codes for the respective memory location 102 and [0061]-[0064] disclosing comparing an error detection code for a write memory location).
Kanter, Soffer, Benedict, and Sonnekalb are analogous art directed to improved memory data integrity techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the error detection memory system of Kanter, Soffer, and Benedict with the integrity check of Sonnekalb as memory system reliability can be improved by being able to detect memory access attacks that manage to manipulate which memory location is written to (See Sonnekalb, [0039]).
None of Kanter, Soffer, Benedict, or Sonnekalb discloses the locations as including a plurality of banks.
However, Brueggen discloses volatile memory locations as including a plurality of banks (See Brueggen, [0024], disclosing a DRAM system with multiple ranks and eight DRAM banks).
Kanter, Benedict, Sonnekalb and Brueggen are analogous art directed to improved error detection in memory systems. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the error detection memory system of Kanter, Benedict, and Sonnekalb with the multiple DRAM memory banks of Brueggen as memory system performance can be increased using banks to allow interleaving of read and write accesses and eliminate access delays (See Brueggen, [0024]).
None of Kanter, Soffer, Benedict, Sonnekalb nor Brueggen discloses a detection circuit among the plurality of detection circuits. However, both Kanter and Sonnekalb disclose a detection circuit as described above.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to use a plurality of detection circuits as ““Mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled” In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976). Alternatively, merely duplicating parts “has no patentable significance unless a new and unexpected result is produced. In reHarza 274, F.2d 449, 104 USPQ 300 (CCPA 1955). Using a plurality of detection circuits does not result in any new or unexpected results and one would be motivated to increase the speed of detections by having additional dedicated error detection circuits.
Regarding claim 2, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed the storage device of claim 1 as described hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen further discloses wherein the write operation controller is configured to transmit, to the nonvolatile memory (See Kanter, Fig. 1, disclosing controller 110 and memory array 130 consisting of NAND 135 and [0032], disclosing controller 110 executing I/O handling [0034], disclosing host interface 105 receiving a write command and data), the write request and the data stored in the selected bank when the second detection value is equal to the first detection value (See Kanter, [0063], using D1 and D2 to determine validity of user write data and [0051] & [0054], disclosing the controller receiving user data through the write data path and subsequently performing validation).
Regarding claim 3, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed the storage device of claim 2 as described hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, in view of Brueggen further discloses wherein the write operation controller is configured to control the nonvolatile memory to suspend the write operation when the second detection value is not equal to the first detection value (See Sonnekalb, [0026], disclosing if the two check values do not match, stopping processing).
Regarding claim 4, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed the storage device of claim 1 as described hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, in view of Brueggen further discloses the processor configured to generate the write request and control the detection circuit to acquire the first detection value of the selected bank when the data stored in the selected bank is updated before the write request is outputted (See Sonnekalb, [0029], [0034], & [0035], disclosing there may be write accesses between generation of reference value and the comparison check value and therefore requires the integrity checking device 103 to adjust the reference value by acquiring and replacing the old value with an update value and also [0064], “check the error detection code stored in the error detection area associated with the memory location to be written to prior to the write access”).
Regarding claims 5, 12, and 16, taking claim 5 as exemplary, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed the storage device of claim 4 as described hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen further discloses wherein, when the data stored in the selected bank is updated, the processor does not acquire any detection value of the other bank except the selected bank among the plurality of banks (See Sonnekalb, [0058], disclosing the integrity checking device is configured in the event of write access to a memory location by a specified address, reading and adjusting the reference value identified by the specified address, or in other words, only the relevant address).
Regarding claim 6, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed he storage device of claim 4 as described hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen further discloses wherein the processor transmits to the nonvolatile memory, the write request and the first detection value acquired after the data is updated (See Kanter, [0032], disclosing controller 110 executing I/O handling [0044], disclosing both user data and E3D signature appended thereto are communicated along the write data path, [0063], using D1 and D2 to determine validity of user write data and [0051] & [0054], disclosing the controller receiving user data through the write data path and subsequently performing validation)
Regarding claim 7, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed the storage device of claim 1 as described hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen further discloses wherein the engine controller is configured to select, when the write request and a bank address representing the selected bank are received (See Sonnekalb, [0022] disclosing integrity checking device 104 is provided for accessing the memory 101. The integrity checking device 104 may be implemented in hardware, or in software running on a processor. The processor implementing the integrity checking device 104 may also be the same processor implementing the memory access element 103. For example, a processor executes two processes, one corresponding to the memory access element 103 and one implementing the integrity checking device 104 and [0058], disclosing the integrity checking device is configured in the event of write access to a memory location by a specified address, reading and adjusting the reference value identified by the specified address), the detection circuit corresponding to the bank address and control the detection circuit to acquire the second detection value of the selected bank (See Sonnekalb, [0058], disclosing the integrity checking device is configured in the event of write access to a memory location by a specified address, reading and adjusting the reference value identified by the specified address, or in other words, the integrity checking values corresponds to the address).
Regarding claim 8, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed the storage device of claim 1 as described hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen further discloses wherein each of the first detection value and the second detection value is a value acquired by the detection circuit, using a checksum method, by using a value of the data stored in the selected bank (See Sonnekalb [0018], [0023]-[0025], disclosing storage of a checksum used as a reference value for integrity checks against a second checksum calculation).
Regarding claims 10 and 14, taking claim 10 as exemplary, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed the method of claim 9 as disclosed hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen further discloses wherein the determining of whether the write operation is to be performed includes: determining that the write operation is performed when the second detection value is equal to the first detection value (See Kanter, [0063], using D1 and D2 to determine validity of user write data and [0051] & [0054], disclosing the controller receiving user data through the write data path and subsequently performing validation); and determining that the write operation is suspended when the second detection value is not equal to the first detection value (See Sonnekalb, [0026], disclosing if the two check values do not match, stopping processing).
Regarding claim 15, Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen disclosed the method of claim 9 as described hereinabove. Kanter in view of Soffer, in view of Benedict, in view of Sonnekalb, further in view of Brueggen further discloses wherein the first detection value of the selected bank is acquired when the data stored in the selected bank is updated (See Sonnekalb, [0029], [0034], & [0035], disclosing there may be write accesses between generation of reference value and the comparison check value and therefore requires the integrity checking device 103 to adjust the reference value by acquiring and replacing the old value with an update value).
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.H.K/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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