Prosecution Insights
Last updated: October 23, 2026
Application No. 18/328,119

ELECTRONIC DEVICE, METHOD, AND STORAGE MEDIUM

Final Rejection §103
Filed
Jun 02, 2023
Priority
Jun 08, 2022 — JP 2022-092931
Examiner
SCOLES, PHILIP GRANT
Art Unit
2837
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Casio Computer Co., Ltd.
OA Round
2 (Final)
56%
Grant Probability
Moderate
3-4
OA Rounds
2m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 56% of resolved cases
56%
Career Allowance Rate
40 granted / 72 resolved
-12.4% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
36 currently pending
Career history
115
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
56.1%
+16.1% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
17.9%
-22.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 72 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-3, 6-7, 10-12, 15-16, and 19-20 are rejected under 35 U.S.C. 103 as unpatentable over Takahashi et al. (US 20190273997 A1, September 5, 2019), hereinafter Takahashi, in view of Sjursen et al. (US 20040000950 A1, January 1, 2004), hereinafter Sjursen, and further in view of Moertel (US 20020071572 A1, January 31, 2002), and CD ("Audio Limiters Theory and Practice," copyright 2021, retrieved 10/3/2026 from https://coherentdistribution.com/wp-content/uploads/2021/02/NST-Audio-Tech-Library-Limiters-2-of-2.pdf). Regarding claim 1, Takahashi teaches an electronic device comprising: an amplifier configured to amplify an input signal and output an output signal obtained by shaping the amplified input signal (Takahashi ¶0028: "Among audio signals to which signal processing is applied by the digital signal processing unit 11, an audio signal of a L (Left) channel is fed to the amplifier 14L. The amplifier 14L amplifies the fed audio signal with a predetermined amplification factor and feeds the amplified audio signal to the speaker unit 15L."); and at least one processor (Takahashi ¶0024: "The control unit 10 includes, for example, a CPU (Central Processing Unit) and controls each unit of the audio signal reproduction apparatus 1."), wherein the at least one processor is configured to: obtain a value indicating power supplied to the amplifier (Takahashi ¶0036: "The voltage detection unit 22A detects the voltage of the battery pack 21, to thereby providing information showing the voltage (hereinafter appropriately referred to as voltage information)." Takahashi ¶0033: "For example, power is fed from battery pack 21 to drive the control unit 10, the digital signal processing unit 11, the amplifiers 14L and 14R, and the like."); control the amplifier in a first pattern such that a clip value for the output signal decreases (Takahashi ¶0047: "In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB. The set limit value may be any appropriate value and is preferably a value that a compression effect by the DRC is less aurally recognizable to a listener. The control is repeated at 3 minutes intervals, for example. For example, the limit value is set to −1.0 dB 3 minutes later. Thus, the effect by the DRC is gradually increased. Note that −6 dB is the restricted value."), when detecting that the value is larger than a reference potential and that the value becomes larger than a first threshold (Takahashi ¶0047: "Then, it assumes that the temperature of the battery pack 21 detected by the temperature detection unit 22C exceeds the threshold value (for example, 42° C.). In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB.") larger than a second threshold (Takahashi ¶0049: "Then, it assumes that the temperature of the battery pack 21 detected by the temperature detection unit 22C exceeds the threshold value (for example, 42° C.). In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB."); and control the amplifier in a second pattern such that the clip value for the output signal increases, when detecting that the value is larger than the reference potential and that the value becomes smaller than the second threshold (Takahashi ¶0050: "In a case where the temperature of the battery pack 21 detected by the temperature detection unit 22C becomes 40° C. or less, the control unit 10 instructs the digital signal processing unit 11 to set the limit value from the limit value at present to +0.5 dB. The control is repeated at 3 minutes intervals, for example, and the volume value is gradually increased. At the time point that the limit value is returned to the limit value at the time point of 42° C. or more as described above, the control is stopped.") from a state of being larger than the first threshold (Takahashi ¶0050: "Note that in a case where the temperature of the battery pack 21 exceeds 42° C. during the control of increasing the limit value, the control is performed to increase the above-described effect by the DRC."). Takahashi does not explicitly disclose becoming larger than a first threshold larger than a second threshold from a state of being smaller than the second threshold, wherein the first threshold is set to a value larger than a rated noise voltage of a speaker to which the output signal from the amplifier is input and smaller than a maximum input voltage of the speaker, and the second threshold is set to a value smaller than the rated noise voltage. However, Sjursen teaches becoming larger than a first threshold larger than a second threshold from a state of being smaller than the second threshold (Sjursen ¶0066: "FIG. 8 illustrates exemplary waveforms of the control signals and the gain of the amplifier for the operation of the circuit 300 of FIG. 7. At time t0 the gain is at its maximum and the input signal is below the threshold levels." Sjursen's operating cycle begins below both threshold levels, so the upper-threshold crossing occurs from a state below the second threshold.). Furthermore, Moertel teaches that the first threshold is set to a value larger than a rated noise voltage of a speaker to which the output signal from the amplifier is input and smaller than a maximum input voltage of the speaker (Moertel ¶0049: "Another data record relates to the peak limiter, by means of which an overload of the final stage or an overload of the speaker with regard to short-term peak outputs is avoided. The data record includes the data fields (data types): Element ID (Byte)/Element number (Byte)/Maximum peak voltage (Float)/Compression ratio (Float)/Attack time (Float)/Hold time (Float)/Release time (Float)/Averaging time constant (Float)." Moertel sets a peak limiter separate from a continuous output limiter. A peak threshold at or below the continuous-withstand level would be redundant with the continuous limiter.). Additionally, CD teaches that the second threshold is set to a value smaller than the rated noise voltage (CD, page 2: "Check the RMS power rating of the speaker system, and its impedance. 2) Look up this value in the table above, using the closest value below the rated power of the speaker system. Note the corresponding ‘dB’ value. 3) Check the gain of your amplifier, which needs to be in ‘dB’. 4) Subtract this gain figure FROM that obtained from the table to find the required absolute setting for the limiter thresholds. Note that, for safety, always set the limiter threshold 1 or 2 dB below the maximum allowable worked out using the above method."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the electronic device of Takahashi by adding the threshold levels of Sjursen, the first threshold of Moertel, and the second threshold of CD to optimize amplifier operation (Moertel ¶0009). Regarding claim 2, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. CD further teaches that the at least one processor is further configured to; set the first pattern such that at least one of feature signals included in the output signal is not shaped by the amplifier (CD p. 1: "Any limiter, which is to protect the driver from damage, must be able to fulfil the following tasks: - Have an attack time which is calculated to allow transients through but keep the RMS level below the speaker manufacturers specification"). Regarding claim 3, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. Takahashi further teaches that the first pattern is a pattern in which the clip value for the output signal decreases with passage of time (Takahashi ¶0047: "The control is repeated at 3 minutes intervals, for example. For example, the limit value is set to −1.0 dB 3 minutes later. Thus, the effect by the DRC is gradually increased."), and the second pattern is a pattern in which the clip value for the output signal increases with passage of time (Takahashi ¶0050: "The control is repeated at 3 minutes intervals, for example, and the volume value is gradually increased."). Regarding claim 6, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. Moertel further teaches that the first threshold and the second threshold are values set based on at least one of rated noise voltage of the speaker, a maximum input voltage of the speaker, and an instantaneous maximum input voltage of the speaker (Moertel ¶0049: "Another data record relates to the peak limiter, by means of which an overload of the final stage or an overload of the speaker with regard to short-term peak outputs is avoided. The data record includes the data fields (data types): Element ID (Byte)/Element number (Byte)/Maximum peak voltage (Float)/Compression ratio (Float)/Attack time (Float)/Hold time (Float)/Release time (Float)/Averaging time constant (Float)."). Regarding claim 7, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. Takahashi further teaches that the input signal and the output signal are audio signals, and the audio signal output from the amplifier is input to the speaker (Takahashi ¶0028: "Among audio signals to which signal processing is applied by the digital signal processing unit 11, an audio signal of a L (Left) channel is fed to the amplifier 14L. The amplifier 14L amplifies the fed audio signal with a predetermined amplification factor and feeds the amplified audio signal to the speaker unit 15L."). Regarding claim 10, Takahashi teaches a method performed by at least one processor (Takahashi ¶0024: "The control unit 10 includes, for example, a CPU (Central Processing Unit) and controls each unit of the audio signal reproduction apparatus 1."), comprising: obtaining a value indicating power supplied to an amplifier configured to amplify an input signal and output an output signal obtained by shaping the amplified input signal (Takahashi ¶0036: "The voltage detection unit 22A detects the voltage of the battery pack 21, to thereby providing information showing the voltage (hereinafter appropriately referred to as voltage information)." Takahashi ¶0033: "For example, power is fed from battery pack 21 to drive the control unit 10, the digital signal processing unit 11, the amplifiers 14L and 14R, and the like."); controlling the amplifier in a first pattern such that a clip value for the output signal decreases (Takahashi ¶0047: "In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB. The set limit value may be any appropriate value and is preferably a value that a compression effect by the DRC is less aurally recognizable to a listener. The control is repeated at 3 minutes intervals, for example. For example, the limit value is set to −1.0 dB 3 minutes later. Thus, the effect by the DRC is gradually increased. Note that −6 dB is the restricted value."), when detecting that the value is larger than a reference potential and that the value becomes larger than a first threshold (Takahashi ¶0047: "Then, it assumes that the temperature of the battery pack 21 detected by the temperature detection unit 22C exceeds the threshold value (for example, 42° C.). In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB.") larger than a second threshold (Takahashi ¶0049: "Then, it assumes that the temperature of the battery pack 21 detected by the temperature detection unit 22C exceeds the threshold value (for example, 42° C.). In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB."); and controlling the amplifier in a second pattern such that the clip value for the output signal increases, when detecting that the value is larger than the reference potential and that the value becomes smaller than the second threshold (Takahashi ¶0050: "In a case where the temperature of the battery pack 21 detected by the temperature detection unit 22C becomes 40° C. or less, the control unit 10 instructs the digital signal processing unit 11 to set the limit value from the limit value at present to +0.5 dB. The control is repeated at 3 minutes intervals, for example, and the volume value is gradually increased. At the time point that the limit value is returned to the limit value at the time point of 42° C. or more as described above, the control is stopped.") from a state of being larger than the first threshold (Takahashi ¶0050: "Note that in a case where the temperature of the battery pack 21 exceeds 42° C. during the control of increasing the limit value, the control is performed to increase the above-described effect by the DRC."). Takahashi does not explicitly disclose becoming larger than a first threshold larger than a second threshold from a state of being smaller than the second threshold, wherein the first threshold is set to a value larger than a rated noise voltage of a speaker to which the output signal from the amplifier is input and smaller than a maximum input voltage of the speaker, and the second threshold is set to a value smaller than the rated noise voltage. However, Sjursen teaches becoming larger than a first threshold larger than a second threshold from a state of being smaller than the second threshold (Sjursen ¶0066: "FIG. 8 illustrates exemplary waveforms of the control signals and the gain of the amplifier for the operation of the circuit 300 of FIG. 7. At time t0 the gain is at its maximum and the input signal is below the threshold levels." Sjursen's operating cycle begins below both threshold levels, so the upper-threshold crossing occurs from a state below the second threshold.). Furthermore, Moertel teaches that the first threshold is set to a value larger than a rated noise voltage of a speaker to which the output signal from the amplifier is input and smaller than a maximum input voltage of the speaker (Moertel ¶0049: "Another data record relates to the peak limiter, by means of which an overload of the final stage or an overload of the speaker with regard to short-term peak outputs is avoided. The data record includes the data fields (data types): Element ID (Byte)/Element number (Byte)/Maximum peak voltage (Float)/Compression ratio (Float)/Attack time (Float)/Hold time (Float)/Release time (Float)/Averaging time constant (Float)." Moertel sets a peak limiter separate from a continuous output limiter. A peak threshold at or below the continuous-withstand level would be redundant with the continuous limiter.). Additionally, CD teaches that the second threshold is set to a value smaller than the rated noise voltage (CD, page 2: "Check the RMS power rating of the speaker system, and its impedance. 2) Look up this value in the table above, using the closest value below the rated power of the speaker system. Note the corresponding ‘dB’ value. 3) Check the gain of your amplifier, which needs to be in ‘dB’. 4) Subtract this gain figure FROM that obtained from the table to find the required absolute setting for the limiter thresholds. Note that, for safety, always set the limiter threshold 1 or 2 dB below the maximum allowable worked out using the above method."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the method of Takahashi by adding the threshold levels of Sjursen, the first threshold of Moertel, and the second threshold of CD optimize amplifier operation (Moertel ¶0009). Regarding claim 11, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. CD further teaches setting the first pattern such that at least one of feature signals included in the output signal is not shaped by the amplifier (CD p. 1: "Any limiter, which is to protect the driver from damage, must be able to fulfil the following tasks: - Have an attack time which is calculated to allow transients through but keep the RMS level below the speaker manufacturers specification"). Regarding claim 12, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. Takahashi further teaches that the first pattern is a pattern in which the clip value for the output signal decreases with passage of time (Takahashi ¶0047: "The control is repeated at 3 minutes intervals, for example. For example, the limit value is set to −1.0 dB 3 minutes later. Thus, the effect by the DRC is gradually increased."), and the second pattern is a pattern in which the clip value for the output signal increases with passage of time (Takahashi ¶0050: "The control is repeated at 3 minutes intervals, for example, and the volume value is gradually increased."). Regarding claim 13, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose that the amplifier includes a clip circuit configured to clip the output signal, and the at least one processor is further configured to: change a clip value of the clip circuit in the first pattern such that the clip value for the output signal decreases with passage of time, when the value is larger than the first threshold; and change the clip value of the clip circuit in the second pattern such that the clip value for the output signal increases with passage of time, when the value is smaller than the second threshold. However, Chieng teaches that the amplifier includes a clip circuit configured to clip the output signal (Chieng ¶0009: "The binary signal is provided to a hard clipping unit that is placed in the digital audio signal path before a noise shaper. The hard clipping unit clips the audio signal when it exceeds high or low clip levels."), and the at least one processor is further configured to: change a clip value of the clip circuit in the first pattern such that the clip value for the output signal decreases with passage of time, when the value is larger than the first threshold (Chieng ¶0012: "The hard clipping unit is configured to receive the binary signal and to decrease the clip level for each successive time period in which the binary signal indicates that the output current exceeds the threshold value."); and change the clip value of the clip circuit in the second pattern such that the clip value for the output signal increases with passage of time, when the value is smaller than the second threshold (Chieng ¶0053: "When the over-current signal is not asserted, multiplexer 540 selects the value received from adder 535 and passes this value through second hard clipper 550 to register 560. Thus, in a first PWM switch period, register 560 contains a particular value. In the next PWM switch period, this value is incremented (i.e., an incremental value, ramp_up increment, is added to the register value,) clipped by second hard clipper 550 to ensure that it does not exceed the maximum clip level, and then stored in register 560."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the method of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the changing clip values over a passage of time of Chieng to transition gracefully between a normal operating mode and a corrective operating mode (Chieng ¶0006). Regarding claim 15, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. Moertel further teaches that the first threshold and the second threshold are values set based on at least one of rated noise voltage of the speaker, a maximum input voltage of the speaker, and an instantaneous maximum input voltage of the speaker (Moertel ¶0049: "Another data record relates to the peak limiter, by means of which an overload of the final stage or an overload of the speaker with regard to short-term peak outputs is avoided. The data record includes the data fields (data types): Element ID (Byte)/Element number (Byte)/Maximum peak voltage (Float)/Compression ratio (Float)/Attack time (Float)/Hold time (Float)/Release time (Float)/Averaging time constant (Float)."). Regarding claim 16, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. Takahashi further teaches that the input signal and the output signal are audio signals, and the audio signal output from the amplifier is input to the speaker (Takahashi ¶0028: "Among audio signals to which signal processing is applied by the digital signal processing unit 11, an audio signal of a L (Left) channel is fed to the amplifier 14L. The amplifier 14L amplifies the fed audio signal with a predetermined amplification factor and feeds the amplified audio signal to the speaker unit 15L."). Regarding claim 19, Takahashi teaches a non-transitory computer-readable storage medium that stores a program for causing at least one processor to execute a process (Takahashi ¶0024: "The control unit 10 includes, for example, a CPU (Central Processing Unit) and controls each unit of the audio signal reproduction apparatus 1."), the process comprising: obtaining a value indicating power supplied to an amplifier (Takahashi ¶0036: "The voltage detection unit 22A detects the voltage of the battery pack 21, to thereby providing information showing the voltage (hereinafter appropriately referred to as voltage information)." Takahashi ¶0033: "For example, power is fed from battery pack 21 to drive the control unit 10, the digital signal processing unit 11, the amplifiers 14L and 14R, and the like.") configured to amplify an input signal and output an output signal obtained by shaping the amplified input signal (Takahashi ¶0028: "Among audio signals to which signal processing is applied by the digital signal processing unit 11, an audio signal of a L (Left) channel is fed to the amplifier 14L. The amplifier 14L amplifies the fed audio signal with a predetermined amplification factor and feeds the amplified audio signal to the speaker unit 15L."); controlling the amplifier in a first pattern such that a clip value for the output signal decreases (Takahashi ¶0047: "In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB. The set limit value may be any appropriate value and is preferably a value that a compression effect by the DRC is less aurally recognizable to a listener. The control is repeated at 3 minutes intervals, for example. For example, the limit value is set to −1.0 dB 3 minutes later. Thus, the effect by the DRC is gradually increased. Note that −6 dB is the restricted value."), when detecting that the value is larger than a reference potential and that the value becomes larger than a first threshold (Takahashi ¶0047: "Then, it assumes that the temperature of the battery pack 21 detected by the temperature detection unit 22C exceeds the threshold value (for example, 42° C.). In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB.") larger than a second threshold (Takahashi ¶0049: "Then, it assumes that the temperature of the battery pack 21 detected by the temperature detection unit 22C exceeds the threshold value (for example, 42° C.). In this case, the control unit 10 instructs the digital signal processing unit 11 to set the limit value in the DRC from the limit value at present to −0.5 dB."); and controlling the amplifier in a second pattern such that the clip value for the output signal increases, when detecting that the value is larger than the reference potential and that the value becomes smaller than the second threshold (Takahashi ¶0050: "In a case where the temperature of the battery pack 21 detected by the temperature detection unit 22C becomes 40° C. or less, the control unit 10 instructs the digital signal processing unit 11 to set the limit value from the limit value at present to +0.5 dB. The control is repeated at 3 minutes intervals, for example, and the volume value is gradually increased. At the time point that the limit value is returned to the limit value at the time point of 42° C. or more as described above, the control is stopped.") from a state of being larger than the first threshold (Takahashi ¶0050: "Note that in a case where the temperature of the battery pack 21 exceeds 42° C. during the control of increasing the limit value, the control is performed to increase the above-described effect by the DRC."). Takahashi does not explicitly disclose becoming larger than a first threshold larger than a second threshold from a state of being smaller than the second threshold, wherein the first threshold is set to a value larger than a rated noise voltage of a speaker to which the output signal from the amplifier is input and smaller than a maximum input voltage of the speaker, and the second threshold is set to a value smaller than the rated noise voltage. However, Sjursen teaches becoming larger than a first threshold larger than a second threshold from a state of being smaller than the second threshold (Sjursen ¶0066: "FIG. 8 illustrates exemplary waveforms of the control signals and the gain of the amplifier for the operation of the circuit 300 of FIG. 7. At time t0 the gain is at its maximum and the input signal is below the threshold levels." Sjursen's operating cycle begins below both threshold levels, so the upper-threshold crossing occurs from a state below the second threshold.). Furthermore, Moertel teaches that the first threshold is set to a value larger than a rated noise voltage of a speaker to which the output signal from the amplifier is input and smaller than a maximum input voltage of the speaker (Moertel ¶0049: "Another data record relates to the peak limiter, by means of which an overload of the final stage or an overload of the speaker with regard to short-term peak outputs is avoided. The data record includes the data fields (data types): Element ID (Byte)/Element number (Byte)/Maximum peak voltage (Float)/Compression ratio (Float)/Attack time (Float)/Hold time (Float)/Release time (Float)/Averaging time constant (Float)." Moertel sets a peak limiter separate from a continuous output limiter. A peak threshold at or below the continuous-withstand level would be redundant with the continuous limiter.). Additionally, CD teaches that the second threshold is set to a value smaller than the rated noise voltage (CD, page 2: "Check the RMS power rating of the speaker system, and its impedance. 2) Look up this value in the table above, using the closest value below the rated power of the speaker system. Note the corresponding ‘dB’ value. 3) Check the gain of your amplifier, which needs to be in ‘dB’. 4) Subtract this gain figure FROM that obtained from the table to find the required absolute setting for the limiter thresholds. Note that, for safety, always set the limiter threshold 1 or 2 dB below the maximum allowable worked out using the above method."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the non-transitory computer-readable storage medium of Takahashi by adding the threshold levels of Sjursen, the first threshold of Moertel, and the second threshold of CD optimize amplifier operation (Moertel ¶0009). Regarding claim 20, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. Takahashi further teaches that the first threshold is a step function that decreases with time and the second threshold is a step function that increases with time (Takahashi ¶0047: "The control is repeated at 3 minutes intervals, for example. For example, the limit value is set to −1.0 dB 3 minutes later. Takahashi ¶0050: "The control is repeated at 3 minutes intervals, for example, and the volume value is gradually increased. At the time point that the limit value is returned to the limit value at the time point of 42° C. or more as described above, the control is stopped."). Claims 4 and 13 are rejected under 35 U.S.C. 103 as unpatentable over Takahashi in view of Sjursen, and further in view of Moertel, CD, and Chieng et al. (US 20070182486 A1, August 9, 2007), hereinafter Chieng. Regarding claim 4, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose that the amplifier includes a clip circuit configured to clip the output signal, and the at least one processor is further configured to: change a clip value of the clip circuit in the first pattern such that the clip value for the output signal decreases with passage of time, when the value is larger than the first threshold; and change the clip value of the clip circuit in the second pattern such that the clip value for the output signal increases with passage of time, when the value is smaller than the second threshold. However, Chieng teaches that the amplifier includes a clip circuit configured to clip the output signal (Chieng ¶0009: "The binary signal is provided to a hard clipping unit that is placed in the digital audio signal path before a noise shaper. The hard clipping unit clips the audio signal when it exceeds high or low clip levels."), and the at least one processor is further configured to: change a clip value of the clip circuit in the first pattern such that the clip value for the output signal decreases with passage of time, when the value is larger than the first threshold (Chieng ¶0012: "The hard clipping unit is configured to receive the binary signal and to decrease the clip level for each successive time period in which the binary signal indicates that the output current exceeds the threshold value."); and change the clip value of the clip circuit in the second pattern such that the clip value for the output signal increases with passage of time, when the value is smaller than the second threshold (Chieng ¶0053: "When the over-current signal is not asserted, multiplexer 540 selects the value received from adder 535 and passes this value through second hard clipper 550 to register 560. Thus, in a first PWM switch period, register 560 contains a particular value. In the next PWM switch period, this value is incremented (i.e., an incremental value, ramp_up increment, is added to the register value,) clipped by second hard clipper 550 to ensure that it does not exceed the maximum clip level, and then stored in register 560."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the electronic device of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the changing clip values over a passage of time of Chieng to transition gracefully between a normal operating mode and a corrective operating mode (Chieng ¶0006). Regarding claim 13, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose that the amplifier includes a clip circuit configured to clip the output signal, and the at least one processor is further configured to: change a clip value of the clip circuit in the first pattern such that the clip value for the output signal decreases with passage of time, when the value is larger than the first threshold; and change the clip value of the clip circuit in the second pattern such that the clip value for the output signal increases with passage of time, when the value is smaller than the second threshold. However, Chieng teaches that the amplifier includes a clip circuit configured to clip the output signal (Chieng ¶0009: "The binary signal is provided to a hard clipping unit that is placed in the digital audio signal path before a noise shaper. The hard clipping unit clips the audio signal when it exceeds high or low clip levels."), and the at least one processor is further configured to: change a clip value of the clip circuit in the first pattern such that the clip value for the output signal decreases with passage of time, when the value is larger than the first threshold (Chieng ¶0012: "The hard clipping unit is configured to receive the binary signal and to decrease the clip level for each successive time period in which the binary signal indicates that the output current exceeds the threshold value."); and change the clip value of the clip circuit in the second pattern such that the clip value for the output signal increases with passage of time, when the value is smaller than the second threshold (Chieng ¶0053: "When the over-current signal is not asserted, multiplexer 540 selects the value received from adder 535 and passes this value through second hard clipper 550 to register 560. Thus, in a first PWM switch period, register 560 contains a particular value. In the next PWM switch period, this value is incremented (i.e., an incremental value, ramp_up increment, is added to the register value,) clipped by second hard clipper 550 to ensure that it does not exceed the maximum clip level, and then stored in register 560."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the method of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the changing clip values over a passage of time of Chieng to transition gracefully between a normal operating mode and a corrective operating mode (Chieng ¶0006). Claims 5 and 14 are rejected under 35 U.S.C. 103 as unpatentable over Takahashi in view of Sjursen, and further in view of Moertel, CD and Izumoto et al. (US 20140320098 A1, October 30, 2014), hereinafter Izumoto. Regarding claim 5, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose that the at least one processor is further configured to: obtain, with a peak hold circuit configured to detect a peak value of a value measured by a current sense amplifier installed on a power supply path to the amplifier, the value indicating the power from the detected peak value. However, Izumoto teaches that the at least one processor is further configured to: obtain, with a peak hold circuit configured to detect a peak value of a value measured by a current sense amplifier installed on a power supply path to the amplifier, the value indicating the power from the detected peak value (Izumoto ¶0308: "The peak hold circuit 52B is a circuit for acquiring the peak value of the input current Iin1. More specifically, the peak hold circuit 52B is a circuit for detecting the maximum value of the input current Iin1 in one cycle (one period) of control on the transistor 101B. The peak hold circuit 52B receives the output of the input current Iin1 from the sense amplifier 24B, and acquires the maximum value (peak value) of the input current Iin1 in one cycle (one period) from when the transistor 101B is turned on until when the transistor 101B is turned off, and outputs a current (hereinafter, referred to as "input peak current Ip1") configured by the peak value of the input current Iin1, to the LPF 53B. The peak hold circuit 52B resets the acquired peak value at a predetermined timing."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the electronic device of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the input current sense amplifier of Izumoto to acquire peak value at a predetermined timing (Izumoto ¶0308). Regarding claim 14, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose obtaining, with a peak hold circuit configured to detect a peak value of a value measured by a current sense amplifier installed on a power supply path to the amplifier, the value indicating the power from the detected peak value. However, Izumoto teaches obtaining, with a peak hold circuit configured to detect a peak value of a value measured by a current sense amplifier installed on a power supply path to the amplifier, the value indicating the power from the detected peak value (Izumoto ¶0308: "The peak hold circuit 52B is a circuit for acquiring the peak value of the input current Iin1. More specifically, the peak hold circuit 52B is a circuit for detecting the maximum value of the input current Iin1 in one cycle (one period) of control on the transistor 101B. The peak hold circuit 52B receives the output of the input current Iin1 from the sense amplifier 24B, and acquires the maximum value (peak value) of the input current Iin1 in one cycle (one period) from when the transistor 101B is turned on until when the transistor 101B is turned off, and outputs a current (hereinafter, referred to as "input peak current Ip1") configured by the peak value of the input current Iin1, to the LPF 53B. The peak hold circuit 52B resets the acquired peak value at a predetermined timing."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the method of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the input current sense amplifier of Izumoto to acquire peak value at a predetermined timing (Izumoto ¶0308). Claims 8 and 17 are rejected under 35 U.S.C. 103 as unpatentable over Takahashi in view of Sjursen, and further in view of Moertel, CD and Wolf et al. (US 20130216049 A1, August 22, 2013), hereinafter Wolf. Regarding claim 8, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose a memory storing a plurality of types of the first pattern and the second pattern corresponding to the plurality of types of the speaker, wherein the at least one processor is further configured to: obtain the first pattern and the second pattern corresponding to a type of the speaker that is an output destination of the amplifier from among the plurality of types of the first pattern and the second pattern; and control the amplifier in the obtained first pattern and second pattern. However, Wolf teaches a memory storing a plurality of types of the first pattern and the second pattern corresponding to the plurality of types of the speaker (Wolf ¶0018: "The lower critical frequency fL may be substituted by a less accurate range identifier for, e.g., woofer, midrange speaker or tweeter. The time constant for an optimum attack time is then supplied to the compressor 2 that seeks to adjust/adapt the actual attack and release time dependent on the audio signal. The nominal Power PN, the voice coil ohmic (DC) resistance RL, which both can be determined or may be taken from a data sheet, may be stored in a memory or manually adjusted, e.g., using a potentiometer. The time constant estimator 8 may be a signal processing unit that processes the signal y according to a given function or a table stored in memory."), wherein the at least one processor is configured to: obtain the first pattern and the second pattern corresponding to a type of the speaker that is an output destination of the amplifier from among the plurality of types of the first pattern and the second pattern (Wolf ¶0018: "From these it estimates, e.g., time constants representing optimum attack and release times for a certain type of loudspeaker; the loudspeaker being identified by the lower critical frequency fL and the nominal power PN. The lower critical frequency fL may be substituted by a less accurate range identifier for, e.g., woofer, midrange speaker or tweeter."); and control the amplifier in the obtained first pattern and second pattern (Wolf ¶0033: "The overshoots are controlled by specifically adapting/adjusting the attack and release times TA, TR to the specific type of loudspeaker to be protected."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the electronic device of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the memory corresponding to the speaker to be protected of Wolf to represent optimum attack and release times for a certain type of loudspeaker (Wolf ¶0018). Regarding claim 17, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose obtaining the first pattern and the second pattern corresponding to a type of the speaker that is an output destination of the amplifier from among the plurality of types of the first pattern and the second pattern corresponding to the plurality of types of the speaker; and controlling the amplifier in the obtained first pattern and second pattern. However, Wolf teaches obtaining the first pattern and the second pattern corresponding to a type of the speaker that is an output destination of the amplifier from among the plurality of types of the first pattern and the second pattern corresponding to the plurality of types of the speaker (Wolf ¶0018: "From these it estimates, e.g., time constants representing optimum attack and release times for a certain type of loudspeaker; the loudspeaker being identified by the lower critical frequency fL and the nominal power PN. The lower critical frequency fL may be substituted by a less accurate range identifier for, e.g., woofer, midrange speaker or tweeter."); and control the amplifier in the obtained first pattern and second pattern (Wolf ¶0033: "The overshoots are controlled by specifically adapting/adjusting the attack and release times TA, TR to the specific type of loudspeaker to be protected."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the method of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the memory corresponding to the speaker to be protected of Wolf to represent optimum attack and release times for a certain type of loudspeaker (Wolf ¶0018). Claims 9 and 18 are rejected under 35 U.S.C. 103 as unpatentable over Takahashi in view of Sjursen, and further in view of Moertel, CD and Shimizu (JP 2022029205 A, February 17, 2022). Regarding claim 9, Takahashi (in view of Sjursen, Moertel, and CD) teaches an electronic device comprising the features of claim 1 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose that the electronic device is an electronic musical instrument having a plurality of keys. However, Shimizu teaches that the electronic device is an electronic musical instrument having a plurality of keys (Shimizu ¶0009: "This figure shows the external appearance of an electronic keyboard device according to one embodiment of the present invention… This figure shows the configuration of the gain control function in one embodiment of the present invention."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the electronic device of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the plurality of keys of Shimizu to generate a sound signal in response to a key operation by a user (Shimizu ¶0011). Regarding claim 18, Takahashi (in view of Sjursen, Moertel, and CD) teaches a method comprising the features of claim 10 as discussed above. Takahashi (in view of Sjursen, Moertel, and CD) does not explicitly disclose that the at least one processor is included in an electronic musical instrument having a plurality of keys. However, Shimizu teaches that the at least one processor is included in an electronic musical instrument having a plurality of keys (Shimizu ¶0009: "This figure shows the external appearance of an electronic keyboard device according to one embodiment of the present invention… This figure shows the configuration of the gain control function in one embodiment of the present invention."). It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the electronic device of Takahashi (as modified by Sjursen, Moertel, and CD) by adding the plurality of keys of Shimizu to generate a sound signal in response to a key operation by a user (Shimizu ¶0011). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHILIP SCOLES whose telephone number is (703)756-1831. The examiner can normally be reached Monday-Friday 8:30-4:30 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dedei Hammond can be reached on 571-270-7938. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHILIP G SCOLES/ Examiner, Art Unit 2837 /DEDEI K HAMMOND/Supervisory Patent Examiner, Art Unit 2837
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Prosecution Timeline

Jun 02, 2023
Application Filed
May 05, 2026
Non-Final Rejection mailed — §103
Jul 24, 2026
Response Filed
Oct 15, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
56%
Grant Probability
72%
With Interview (+16.7%)
3y 7m (~2m remaining)
Median Time to Grant
Moderate
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