DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 04/02/2026 has been acknowledged. Claims 1 and 20 have been amended. Claim 19 is canceled. Claim 21 is added. No new matter has been added.
This office action considers claims 1-18 and 20-21 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 04/02/2026 with respect to the rejection of claim 1 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-3, 5-8, 10, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ding et al. (US 20240251611 A1 - hereinafter Ding) in
view of Miyajima et al. (US 20020171086 A1 – hereinafter Miyajima) and An et al. (US 20210280664 A1 – hereinafter An).
Regarding independent claim 1, Ding teaches
(Currently amended) A display ([Title] – “Display Apparatus” –
hereinafter ‘DIS’) comprising:
a plurality of pixels (Fig. 1 – [0059] – “pixel array may include a plurality of sub-
pixels Pxij” – a plurality of sub-pixels implies a plurality of pixels – hereinafter ‘PIX’) arranged in a first area (100 – Fig. 2 – [0060] – “display region 100 may be referred to as an active area (AA)”);
display driver circuitry ([0070] – “shown in FIG. 5, the pixel drive circuit may
include seven transistors (a first transistor T1 to a seventh transistor T7), one storage capacitor C” – hereinafter ‘PDC’) in a second area (300 – Fig. 7 – [0062] – “the bezel region 300 may include a circuit zone, a power supply line zone, and a crack dam zone and a cutting zone which are sequentially disposed along the direction away from the display region 100”);
a plurality of data lines (60 – Fig. 7 – [0099] – “plurality of data signal lines 60”)
for the plurality of pixels (PIX), wherein the plurality of data lines (60) is in the first area (100 – Fig. 7 shows this);
a plurality of gate lines (23 – Fig. 12b – [0140] – “each sub-pixel may at least include the first scanning signal line 21, the second scanning signal line 22, the light emitting control line 23” – this is considered a gate line as per applicant’s specification [0035 ] “Horizontal control lines G (sometimes referred to as gate lines, scan lines, emission control lines, etc.) run horizontally through display 14”) for the plurality of pixels (PIX); and
a plurality of fanout lines (70 – Fig. 7 – [0099] – “plurality of data fan-out lines 70”) that are routed through the first area (100 – Fig. 7 shows this), wherein each fanout line (70) of the plurality of fanout lines (70) electrically connects the display driver circuitry (PDC – [0102] – “first ends of the plurality of data fan-out lines 70 are connected correspondingly with the plurality of lead lines 220 in the lead line zone 210, the second ends of the plurality of data fan-out lines 70 are correspondingly connected with the plurality of data signal lines 60 through a plurality of lapping vias K after extending towards a direction away from the bonding region 200 in the display region 10, so that the plurality of data signal lines 60 in the display region 100 are correspondingly connected with the plurality of lead lines 220 in the bonding region 200 through the plurality of data fan-out lines 70 in the display region 100” – Fig. 1 shows this) to a respective data line (60) of the plurality of data lines (60 – Fig. 7 shows) and wherein a pixel (PIX) in the plurality of pixels (PIX) comprises:
a first power supply terminal (VDD – Fig. 5 – [0061] – “first power supply line (VDD)” – this is interpreted as the terminal);
a second power supply terminal (VSS – Fig 5 – [0061] – “second power supply line (VSS)” – this is interpreted as the terminal);
a drive transistor (T3 – Fig. 5 – [0075] – “third transistor T3 may be referred to as a drive transistor”) and a light-emitting diode (OLED – Fig. 5 – [0079] – “light emitting device may be an OLED”) that are connected in series (Fig. 5 shows this) between the first power supply terminal (VDD) and the second power supply terminal (VSS);
a conductive layer that forms a first terminal for the drive transistor; and
a conductive shielding layer that is interposed between the conductive
layer and a fanout line of the plurality of fanout lines (70), wherein the conductive layer is interposed between a gate line of the plurality of gate lines and the conductive shielding layer.
Ding does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Miyajima teaches
a conductive layer (30 – Fig. 15 – [0115] – “first electrode 30 of the storage
capacitor, which is integral with the TFT active layer” – this is a conducive layer as it is integral with the active layer of the transistor) that forms a first terminal for the drive transistor ([0125] – “when the driver TFT not using the storage capacitor Csc is built into the same substrate as the TFT of the pixel section having the storage capacitor Csc and the channel region of the pixel section TFT of the second electrode 32 is open” – Fig. 17 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer structure as taught by Miyajima into Ding.
An ordinary artisan would have been motivated to use the known technique of Miyajima in the manner set forth above to produce the predictable result of [0029] – “Lowering of the aperture ratio due to the formation of the storage capacitor can be minimized by disposing the first electrode and the second electrode of the storage capacitor below the data line forming region, and coupling between the first electrode and the data line can be prevented by disposing the conductive shield layer between the data line and the first electrode.”
Ding and Miyajima do not expressly disclose the other limitations of claim 1.
However, in an analogous art, An teaches
wherein the conductive layer (1510 – Fig. 17 – [0171] – “connecting pattern 1510”) is interposed between a gate line (1330 – Fig. 17 – [0171] – “fourth gate line 1330”) of the plurality of gate lines ({[0170] – “third gate line 1320”}, {[0171] – “fourth gate line 1330” – this is a plurality of gate lines) and the conductive shielding layer (1610 – Fig. 17 – [0171] – “horizontal transmitting line 1610”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer and conductive shielding layer structure as taught by An into Ding and Miyajima.
An ordinary artisan would have been motivated to use the known technique of An in the manner set forth above to produce the predictable result of [0171] – “gate line 1330 and the horizontal transmitting line 1610, and may prevent or reduce a crosstalk between the fourth gate line 1330 and the vertical transmitting line 1720.”
Regarding claim 2, Ding, as modified by Miyajima and An, teaches claim 1 from which claim 2 depends. Ding further teaches
(Previously presented) The display defined in claim 1, wherein the
first terminal ([0053] – “transistor refers to a component which includes at least three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source”) is a source terminal, a gate terminal or a drain terminal ([0054] – “In the specification, a first electrode may be a drain electrode, and a second electrode may be a source electrode. Or, the first electrode may be the source electrode, and the second electrode may be the drain electrode. In cases that transistors with opposite polarities are used, a current direction changes during operation of a circuit, or the like, functions of the “source electrode” and the “drain electrode” are sometimes interchangeable. Therefore, the “source electrode” and the “drain electrode”, as well as the “source terminal” and the “drain terminal” are interchangeable in the specification”).
Regarding claim 3, Ding, as modified by Miyajima and An, teaches claim 1 from which claim 3 depends. Ding and An do not expressly disclose the limitations of claim 3.
However, in an analogous art, Miyajima teaches
(Previously presented) The display defined in claim 1, wherein the
conductive shielding layer (20e) is formed above the conductive layer (30) and below the fanout line (22 – Fig. 15 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer and conductive shielding layer structure as taught by Miyajima into Ding and An.
An ordinary artisan would have been motivated to use the known technique of Miyajima in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 5, Ding, as modified by Miyajima and An, teaches claim 1 from which claim 5 depends. Ding and An do not expressly disclose the limitations of claim 5.
However, in an analogous art, Miyajima teaches
(Original) The display defined in claim 1, wherein the pixel further
comprises:
a first dielectric layer (17 – Fig. 15 – [0116] – “interlayer insulating film 17 is formed on the shielding layer 20e, and the data line 22 is formed on the insulating film 17” – this is a dielectric layer) that is interposed between the conductive shielding layer (20e) and the fanout line (22); and
a second dielectric layer (16 – Fig. 15 – {[0116] – “first electrode 30 is covered with the gate insulating film 16, the shielding layer 20e extended from the gate line 20 of the next stage is formed on the gate insulating film 16”}, {0087] – “gate insulating film 16 formed of SiO.sub.2”} – this is a dielectric) that is interposed between the conductive layer (30) and the conductive shielding layer (20e).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dielectric layers structure as taught by Miyajima into Ding and An.
An ordinary artisan would have been motivated to use the known technique of Miyajima in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 6, Ding, as modified by Miyajima and An, teaches claim 5 from which claim 6 depends. Ding further teaches
(Original) The display defined in claim 5, wherein the first dielectric
layer (92 – Fig. 24 – [0228] – “second planarization layer 92”) is an organic planarization layer ([0193] – “first planarization layer and the second planarization layer may be made of an organic material such as a resin”).
Regarding claim 7, Ding, as modified by Miyajima and An, teaches claim 5 from which claim 7 depends. Ding and An do not expressly disclose the limitations of claim 7.
However, in an analogous art, Miyajima teaches
(Original) The display defined in claim 5, wherein the first dielectric layer
(17) is in direct contact with both the conductive shielding layer (20e) and the fanout line (22) and wherein the second dielectric layer (16) is in direct contact with both the conductive layer (30) and the conductive shielding layer (20e – Fig. 15 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dielectric layers structure as taught by Miyajima into Ding and An.
An ordinary artisan would have been motivated to use the known technique of Miyajima in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 8, Ding, as modified by Miyajima and An, teaches claim 5 from which claim 8 depends. Ding further teaches
(Original) The display defined in claim 5, wherein the pixel further
comprises:
a third dielectric layer (85 – Fig. 24 – [0228] – “a fifth insulation layer 85, a third conductive layer”);
a fourth dielectric layer (84 – Fig. 24 – [0228] – “fourth insulation layer 84, a second semiconductor layer”); and
a fifth dielectric layer (82 – Fig. 24 – [0228] – “a second insulation layer 82, a first conductive layer”), wherein a gate line (Fig. 24 annotated, see below – [0230] – “the first conductive layer at least includes the gate electrode of the LTPS transistor”) is interposed between the fourth (84) and fifth (82) dielectric layers.
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Regarding claim 10, Ding, as modified by Miyajima and An, teaches claim 5 from which claim 10 depends. Ding further teaches
(Original) The display defined in claim 5, wherein the first dielectric
layer (92 – Fig. 24 – [0213] – “second planarization layer 92”) is a first organic planarization layer and wherein the second dielectric layer (91 – Fig. 24 – [0213] – “first planarization layer 91”) is a second organic planarization layer ([0193] – “first planarization layer and the second planarization layer may be made of an organic material such as a resin”).
Regarding claim 13, Ding, as modified by Miyajima and An, teaches claim 1 from which claim 13 depends. Ding further teaches
(Original) The display defined in claim 1, wherein the pixel (PIX)
further comprises:
an additional conductive layer (Fig. 24 annotated, see above – hereinafter
‘ACL’) that forms a second terminal for the drive transistor (T3) , wherein the conductive shielding layer is interposed between the additional conductive layer (ACL) and the fanout line.
Ding and An do not expressly disclose the other limitations of claim 13.
However, in an analogous art, Miyajima teaches
the conductive shielding layer (20e – Fig. 15 – {[0116] – “conductive shielding layer 20e”}, {[0115] – “in order to prevent coupling, a conductive shielding layer is formed between the layers in the superimposed region of the first electrode 30 and the data line. This conductive shielding layer may be any layer to which a prescribed voltage is applied”}) is interposed between the additional conductive layer and the fanout line (22 – Fig. 15 – [0115] – “the data line 22” – this is considered a fanout line as it is connected to each pixel).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive shielding layer position as taught by Miyajima into Ding and An.
An ordinary artisan would have been motivated to use the known technique of Miyajima in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 14, Ding, as modified by Miyajima and An, teaches claim 13 from which claim 14 depends. Ding further teaches
(Original) The display defined in claim 13, wherein the additional
conductive layer (ACL) is coplanar with the conductive layer (CL – Fig. 24 annotated, see above, shows this).
Regarding claim 15, Ding, as modified by Miyajima and An, teaches claim 14 from which claim 15 depends. Ding further teaches
(Original) The display defined in claim 14, wherein the first terminal
is a gate terminal ([0053] – “transistor refers to a component which includes at least three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source”) and wherein the second terminal is a drain terminal ([0054] – “In the specification, a first electrode may be a drain electrode, and a second electrode may be a source electrode. Or, the first electrode may be the source electrode, and the second electrode may be the drain electrode. In cases that transistors with opposite polarities are used, a current direction changes during operation of a circuit, or the like, functions of the “source electrode” and the “drain electrode” are sometimes interchangeable. Therefore, the “source electrode” and the “drain electrode”, as well as the “source terminal” and the “drain terminal” are interchangeable in the specification”).
Regarding claim 16, Ding, as modified by Miyajima and An, teaches claim 1 from which claim 16 depends. Ding and An do not expressly disclose the limitations of claim 16.
However, in an analogous art, Miyajima teaches
(Original) The display defined in claim 1, wherein the conductive shielding
layer (20e) is electrically connected to the first power supply terminal (20e – Fig. 15 – {[0116] – “conductive shielding layer 20e”}, {[0115] – “in order to prevent coupling, a conductive shielding layer is formed between the layers in the superimposed region of the first electrode 30 and the data line. This conductive shielding layer may be any layer to which a prescribed voltage is applied”}).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive shielding connection as taught by Miyajima into Ding and An.
An ordinary artisan would have been motivated to use the known technique of Miyajima in the manner set forth above to produce the predictable result as stated above in claim 1.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ding in
view of Miyajima, An, and Yi (US 20240040866 A1 - hereinafter Yi ).
Regarding claim 4, Ding, as modified by Miyajima and An, teaches claim 1 from which claim 4 depends. Ding, Miyajima, and An do not expressly disclose the limitations of claim 4.
However, in an analogous art, Yi teaches
(Previously presented) The display defined in claim 1, wherein the fanout
line (21 – Fig. 7 – [0060] – “fanout lines 210”) is coplanar ([0060] – “fanout lines 210 are arranged at a same layer, and made of a same material, as the scanning lines 101, and the second data fanout lines 211 are arranged at a same layer, and made of a same material, as the data lines 102” – this is coplanar) with a data line of the plurality of data lines (102 – Fig. 7 – [0060] – “data line 102”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the fanout and data line positions as taught by Yi into Ding, Miyajima, and An.
An ordinary artisan would have been motivated to use the known technique of Yi in the manner set forth above to produce the predictable result of [0002] – “display panel has such advantages as more rapid response, higher contrast and larger viewing angle.” This is achieved by placing lines in the same plane, in the same layer, and sharing the same location.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claims 9, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ding in view of Miyajima, An, and Yu et al. (US 20230094885 A1 – hereinafter Yu).
Regarding claim 9, Ding as modified by Miyajima and An, teaches claim 8 from which claim 9 depends. Ding further teaches
wherein the pixel (PIX) further comprises:
first (Fig. 24 annotated, see below – [0098] – “gate electrodes of a plurality of
low temperature polysilicon transistors” – hereinafter ‘FPE’) and second polysilicon layers (Fig. 24 annotated, see below – [0098] – “gate electrodes of a plurality of low temperature polysilicon transistors” - hereinafter ‘SPE’); and
first (Fig. 24 annotated, see below – [0098] – “gate electrodes of a plurality of
low temperature polysilicon transistors” - hereinafter ‘FV’) and second vias (Fig. 24 annotated, see below – [0098] – “gate electrodes of a plurality of low temperature polysilicon transistors” - hereinafter ‘SV’) that extend through the third (85), fourth (84), and fifth (82 – Fig. 24 annotated shows this) dielectric layers.
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Ding, Miyajima, and An do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Yu teaches
to electrically connect the conductive layer (2021 – Fig. 3 – [0040] – “conductive line 2021”) to the first (11 – Fig. 24 – [0032] – “transistor 20 is electrically connected to the data line 11”) and second (201b – Fig. 3 – [0038] – “The conductive line may be a source electrically connected to a part of the patterned active layer 201 corresponding to the source contact area 201b”) polysilicon ([0032] – “transistor 20 is a low temperature polysilicon transistor”) layers, wherein the conductive layer (2021), the first (11) and second polysilicon layers (201b), and the first (13a – Fig. 3 – [0042] – “first via hole 13a”) and second vias (13b – Fig. 3 – [0043] – “second via 13b”) collectively make up the first terminal ([0042] – “the first conductive line 2021 is electrically connected to a part of the patterned active layer 201 corresponding to the source contact region 201b through the first via hole, and the first via hole 13a is defined in a region corresponding to the data line 11”) for the drive transistor (20 – Fig. 3 – [0032] – “transistor 20 is a low temperature polysilicon transistor”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer structure as taught by Yu into Ding, Miyajima, and An.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result of [0007] – “A patterned active layer of a transistor electrically connected to a data line is disposed in a region corresponding to the data line, so that the patterned active layer and the data line are overlapped to reduce the layout space required for the two, and the width of the repeating unit is reduced, which is beneficial to the display panel to realize high-resolution display.”
Regarding claim 11, Ding as modified by Miyajima and An, teaches claim 5 from which claim 11 depends. Ding further teaches
wherein the pixel (PIX) further comprises:
a third dielectric layer (85);
a fourth dielectric layer (84);
a fifth dielectric layer (83);
a sixth dielectric layer (82 – Fig. 24 – [0213] – “second insulation layer 82, a first conductive layer”);
a first polysilicon layer (FPE); and
a first via (FV) that extends through the third (85), fourth (84), fifth (83), and sixth dielectric (82) layers.
Ding, Miyajima, and An do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Yu teaches
to electrically connect the conductive layer (2021) to the first polysilicon layer (11), wherein the conductive layer (2021), the first polysilicon layer (11), and the first via (13a) collectively make up the first terminal for the drive transistor (20).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer structure as taught by Yu into Ding, Miyajima, and An.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result as stated above in claim 9.
Regarding claim 12, Ding as modified by Miyajima and An, teaches claim 11 from which claim 12 depends. Ding further teaches
the pixel (PIX),
a second via (SV) that extends through the third (85), fourth (84), fifth
(83), and sixth (82) dielectric layers.
Ding, Miyajima, and An do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Yu teaches
wherein the pixel further comprises:
an additional conductive layer (2022 – Fig. 3 – [0039] – “second conductive line 2022”);
a second polysilicon layer (201c – Fig. 3 – [0038] – “drain contact area 201c”); and
a second via that extends through the third, fourth, fifth, and sixth dielectric layers
to electrically connect the additional conductive layer (2022) to the second polysilicon layer (201c), wherein the additional conductive layer (2022), the second polysilicon layer (201c), and the second via (a4a – Fig. 3 – [0047] – “via 14a”) collectively make up a second terminal ([0039] – “The second conductive line 2022 serves as a drain and being electrically connected to the pixel electrode 17 and a part of the patterned active layer 201 corresponding to the drain contact region 201c”) for the drive transistor (20).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer structure as taught by Yu into Ding, Miyajima, and An.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result as stated above in claim 9.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ding in view of Miyajima and Zhang et al. (US 20230354655 A1 – hereinafter Zhang).
Regarding claim 17, Ding as modified by Miyajima and An, teaches claim 1 from which claim 17 depends. Ding further teaches
(Original) The display defined in claim 1, wherein the plurality of
pixels (PIX) is arranged in rows and columns ([0100] – “Each pixel row may include a plurality of sub-pixels sequentially disposed along a first direction X, the plurality of pixel rows may be sequentially disposed along a second direction Y, and each pixel column may include a plurality of sub-pixels sequentially disposed along the second direction Y, the plurality of pixel columns may be sequentially disposed along he first direction X, and the first direction X intersects with the second direction Y”), wherein each column has a respective data line (D1 – Fig. 1 – [0059] – “plurality of data signal lines (D1 to Dn)” plurality of data signal lines (D1 to Dn)”) of the plurality of data lines (Dn – Fig. 1 shows this), and wherein each
Ding, Miyajima, and An do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Zhang teaches
fanout line (700 – Fig. 15 – [0105] – “fanout lines 700”) of the plurality of fanout lines (700) has a vertical portion (700b – Fig. 16 – [0137] – “extending segment 700b” – this is a vertical portion of 700) that extends along at least a portion of a respective column (Fig. 1 shows rows and columns) and a horizontal portion (700c – Fig. 16 – [0137] – “extending segment 700b” – this is a horizontal portion of 700) that extends along at least a portion of a respective row (Fig. 1 shows rows and columns).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the fanout line structure as taught by Zhang into Ding, Miyajima, and An.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result of connecting pixel within the display area.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 18, Ding as modified by Miyajima and An, teaches claim 17 from which claim 18 depends. Ding further teaches
(Original) The display defined in claim 17, further comprising:
a power supply mesh ([0012] – “the power supply electrode is in an entire
surface structure or a mesh structure” – hereinafter ‘MESH’) that includes the second power supply terminal (VSS – Fig 5 – [0061] – “second power supply line (VSS)”),
wherein the power supply mesh (MESH).
Ding, Miyajima, and An do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Zhang teaches
includes a plurality of vertical portions (VDD4 – Fig. 16 – [0136] – “first power supply lines VDD and plate connection lines 35, wherein the first power supply lines VDD extend along the first direction D1 and the plate connection lines 35 extend along the second direction D2”) that are aligned with vertical portions of the fanout lines (700b) and wherein the power supply mesh includes a plurality of horizontal portions (35 – Fig. 16 – [0136] – “first power supply lines VDD and plate connection lines 35, wherein the first power supply lines VDD extend along the first direction D1 and the plate connection lines 35 extend along the second direction D2”) that are aligned with horizontal portions of the fanout lines (700c – Fig. 16 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power line structure as taught by Zhang into Ding, Miyajima, and An.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result of connecting pixel within the display area.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ding in
view of Miyajima.
Regarding independent claim 20, Ding teaches
(Original) A display ([Title] – “Display Apparatus” – hereinafter ‘DIS’)
comprising:
a plurality of pixels (Fig. 1 – [0059] – “pixel array may include a plurality of sub-
pixels Pxij” – a plurality of sub-pixels implies a plurality of pixels – hereinafter ‘PIX’) arranged in a light-emitting area (100 – Fig. 2 – [0060] – “display region 100 may be referred to as an active area (AA)”);
a plurality of data lines (60 – Fig. 7 – [0099] – “plurality of data signal lines 60”)
in the light-emitting area (AA);
a plurality of fanout lines (70 – Fig. 7 – [0099] – “plurality of data fan-out lines
70”) in the light-emitting area (AA), wherein each fanout line (70) of the plurality of fanout lines (70) is electrically connected to a respective data line (60) of the plurality of data lines (60 – Fig. 7 shows this);
a transistor (T3 – Fig. 5 – [0075] – “third transistor T3 may be referred to as a drive transistor”) having first, second, and third terminals ([0053] – “transistor refers to a component which includes at least three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source”); and
a conductive shielding layer that is interposed between a fanout line of the plurality of fanout lines (70) and at least two of the first, second, and third terminals.
Ding does not expressly disclose the limitations of claim 16.
However, in an analogous art, Miyajima teaches
a conductive shielding layer (20e – Fig. 15 – {[0116] – “conductive shielding layer 20e”}, {[0115] – “in order to prevent coupling, a conductive shielding layer is formed between the layers in the superimposed region of the first electrode 30 and the data line. This conductive shielding layer may be any layer to which a prescribed voltage is applied”}) that is interposed between a fanout line (22 – Fig. 15 – [0115] – “the data line 22” – this is considered a fanout line as it is connected to each pixel) of the plurality of fanout lines and at least two of the first, second, and third terminals ([0125] – “when the driver TFT not using the storage capacitor Csc is built into the same substrate as the TFT of the pixel section having the storage capacitor Csc and the channel region of the pixel section TFT of the second electrode 32 is open” – Fig. 17 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer and conductive shielding layer structure as taught by Miyajima into Ding.
An ordinary artisan would have been motivated to use the known technique of Miyajima in the manner set forth above to produce the predictable result as stated above in claim 1.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Ding in
view of An.
Regarding independent claim 21, Ding teaches
(New) A display ([Title] – “Display Apparatus” – hereinafter ‘DIS’)
comprising:
a plurality of pixels (Fig. 1 – [0059] – “pixel array may include a plurality of sub-
pixels Pxij” – a plurality of sub-pixels implies a plurality of pixels – hereinafter ‘PIX’) arranged in a light-emitting area (100 – Fig. 2 – [0060] – “display region 100 may be referred to as an active area (AA)” – this is a light-emitting area), wherein a given pixel of the plurality of pixels (PIX) has a transistor;
a plurality of data lines (Fig. 7 – [0099] – “plurality of data signal lines 60” – hereinafter ‘P60’) in the light-emitting area (100);
a plurality of fanout lines (Fig. 7 – [0099] – “plurality of data fan-out lines 70” – hereinafter ‘P70’) in the light-emitting area (100), wherein each fanout line (70 – Fig. 7 – [0099] – “data fan-out lines 70”) of the plurality of fanout lines (P70) is electrically connected ([0102] – “so that the plurality of data signal lines 60 in the display region 100 are correspondingly connected with the plurality of lead lines 220 in the bonding region 200 through the plurality of data fan-out lines 70 in the display region 100” – Fig. 1 shows this) to a respective data line (60 – Fig. 7 – [0099] – “data signal lines 60”) of the plurality of data lines (P60);
a transistor (T3 – Fig. 5 – [0075] – “third transistor T3 may be referred to as a drive transistor”) with a terminal ([0053] – “transistor refers to a component which includes at least three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source”); and
a conductive shielding layer that is interposed between a fanout line of the plurality of fanout lines and the terminal.
Ding does not expressly disclose the limitations of claim 16.
However, in an analogous art, An teaches
a conductive shielding layer (1610 – Fig. 17 – [0171] – “horizontal transmitting line 1610”) that is interposed between a fanout line (1720 – Fig. 17 – {[0132] – “vertical transmitting line 1720”}, {[0069] – “transmitting line FL may be a fan-out line” – this is considered a fanout line) of the plurality of fanout lines ([0069] – “first to fourth data lines DL1, DL2, DL3, and DL4, a first transmitting line FL1, and a second transmitting line FL2 may be located in the display area DA. For example, the transmitting line FL may be a fan-out line electrically connecting the data driver DDV and the data line DL” – this describes a plurality of fanout lines) and the terminal ({[0138] – “the horizontal transmitting line 1610 may transmit the data voltage DATA to the second transistor T2”}, {[0090] – “first terminal of the second transistor T2 may receive the data voltage DATA through the data line DL” – terminals are on the transistors).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer and conductive shielding layer structure as taught by An into Ding.
An ordinary artisan would have been motivated to use the known technique of An in the manner set forth above to produce the predictable result as stated above in claim 1.
Pertinent Art
For the benefits of the Applicant, US 10707282 B1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the specified dielectric layer structure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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