DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/22/2026 has been entered.
Response to Amendments
Applicant's response of 06/22/2026 has been acknowledged. Claims 1, 20-21 have been amended. No new matter has been added.
This office action considers claims 1-18 and 20-21 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 06/22/2026 with respect to the rejections of claims have
been fully considered, and are persuasive. Therefore, the rejection of claims 1-18, and 20-21 have been withdrawn.
Applicant’s arguments with respect to claims 1-18 have been fully considered and are persuasive.
Applicant's arguments with respect to claims 20-21 have been fully considered
but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ding et al. (US 20240251611 A1 - hereinafter Ding) in view of Choi et al. (US 20220208924 A1 – hereinafter Choi-924).
Regarding independent claim 20, Ding teaches
(Currently Amended) A display ([Title] – “Display Apparatus” –
hereinafter ‘DIS’) that emits light in a direction ([0004] – “A display may include a plurality of pixels arranged in a first area, display driver circuitry in a second area, a plurality of data lines for the plurality of pixels that is in the first area, and a plurality of fanout lines that are routed through the first area. Each fanout line of the plurality of fanout lines may electrically connect the display driver circuitry to a respective data line of the plurality of data lines and a pixel in the plurality of pixels may include a first power supply terminal, a second power supply terminal, a drive transistor and a light-emitting diode that are connected” – a light-emitting diode does this), the display (DIS) comprising:
a plurality of pixels (Fig. 1 – [0059] – “pixel array may include a plurality of sub-
pixels Pxij” – a plurality of sub-pixels implies a plurality of pixels – hereinafter ‘PIX’) arranged in a light-emitting area (100 – Fig. 2 – [0060] – “display region 100 may be referred to as an active area (AA)”);
a plurality of data lines (60 – Fig. 7 – [0099] – “plurality of data signal lines 60”)
in the light-emitting area (AA);
a plurality of fanout lines (70 – Fig. 7 – [0099] – “plurality of data fan-out lines
70”) in the light-emitting area (AA), wherein each fanout line (70) of the plurality of fanout lines (70) is electrically connected to a respective data line (60) of the plurality of data lines (60 – Fig. 7 shows this);
a transistor (T3 – Fig. 5 – [0075] – “third transistor T3 may be referred to as a drive transistor”) having first, second, and third terminals ([0053] – “transistor refers to a component which includes at least three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source”); and
a conductive shielding layer that is interposed between a fanout line of the plurality of fanout lines and at least two of the first, second, and third terminals, wherein the conductive shielding layer overlaps the at least two of the first, second, and third terminals in the direction.
Ding does not expressly disclose the limitations of claim 16.
However, in an analogous art, Choi-924 teaches
a conductive shielding layer (SHL – Fig. 16 – [0164] – “second electrode CE2 may be connected to the driving voltage line PL through a shielding layer SHL” – this is a conductive shielding layer) that is interposed between a fanout line (HCL – Fig. 16 – {[0081] – “because data signals are transmitted through the plurality of connection lines CL located in the display area DA without fan-out lines, the area of the peripheral area PA may be effectively reduced, and thus, the dead space of the display panel 10 may be effectively reduced”}, {[0091] – “the plurality of connection lines CL may have a shape bent at least twice in a plan view. In an embodiment, the first portion CLa may include a vertical connection line VCL extending in the first direction (e.g., the +y direction) and a horizontal connection line HCL extending in the second direction (e.g., the +x direction) crossing the first direction”} – element CL are fanout lines and element HCL is a horizontal CL lines) of the plurality of fanout lines ([0078] – “a plurality of connection lines CL” – these are fanout lines) and at least two of the first, second, and third terminals ([0146] – “driving semiconductor layer A1 … may include a source region and a drain region” – Fig. 16 shows this), wherein the conductive shielding layer (SHL) overlaps the at least two of the first, second, and third terminals in the direction (Fig. 16 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer and conductive shielding layer structure as taught by Choi-924 into Ding.
An ordinary artisan would have been motivated to use the known technique of Choi-924 in the manner set forth above to produce the predictable result [0244] – “Because the shielding layer SHL is located between the connection line CL and the driving thin-film transistor T1 and receives a constant voltage, the parasitic capacitance and the coupling phenomenon between the connection line CL and the driving thin-film transistor T1 may be prevented. Accordingly, the deterioration of the display quality of the display panel 10 may be prevented.”
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Ding in
view of An et al. (US 20210280664 A1 – hereinafter An-664).
Regarding independent claim 21, Ding teaches
(Currently amended) A display ([Title] – “Display Apparatus” –
hereinafter ‘DIS’) that emits light in a direction ([0004] – “A display may include a plurality of pixels arranged in a first area, display driver circuitry in a second area, a plurality of data lines for the plurality of pixels that is in the first area, and a plurality of fanout lines that are routed through the first area. Each fanout line of the plurality of fanout lines may electrically connect the display driver circuitry to a respective data line of the plurality of data lines and a pixel in the plurality of pixels may include a first power supply terminal, a second power supply terminal, a drive transistor and a light-emitting diode that are connected” – a light-emitting diode does this), the display (DIS) comprising:
a plurality of pixels (Fig. 1 – [0059] – “pixel array may include a plurality of sub-
pixels Pxij” – a plurality of sub-pixels implies a plurality of pixels – hereinafter ‘PIX’) arranged in a light-emitting area (100 – Fig. 2 – [0060] – “display region 100 may be referred to as an active area (AA)” – this is a light-emitting area), wherein a given pixel of the plurality of pixels (PIX) has a transistor with a terminal ([0053] – “transistor refers to a component which includes at least three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the
source electrode (source electrode terminal, source region, or source)”);
a plurality of data lines (Fig. 7 – [0099] – “plurality of data signal lines 60” – hereinafter ‘P60’) in the light-emitting area (100);
a plurality of fanout lines (Fig. 7 – [0099] – “plurality of data fan-out lines 70” – hereinafter ‘P70’) in the light-emitting area (100), wherein each fanout line (70 – Fig. 7 – [0099] – “data fan-out lines 70”) of the plurality of fanout lines (P70) is electrically connected ([0102] – “so that the plurality of data signal lines 60 in the display region 100 are correspondingly connected with the plurality of lead lines 220 in the bonding region 200 through the plurality of data fan-out lines 70 in the display region 100” – Fig. 1 shows this) to a respective data line (60 – Fig. 7 – [0099] – “data signal lines 60”) of the plurality of data lines (P60);
a plurality of gate lines ([0097] – “semiconductor layer at least includes an active layer of a plurality of transistors, the first conductive layer at least includes gate electrodes of a plurality of transistors” – each gate is connected to a gate line) in the light-emitting area (100 – Fig. 2 – [0060] – “display region 100 may be referred to as an active area (AA” – this is a light-emitting area); and
a conductive shielding layer that is interposed between a fanout line of the plurality of fanout lines and a conductive portion of the terminal, wherein the conductive portion of the terminal is interposed between the conductive shielding layer and a gate line of the plurality of gate lines and wherein the conductive portion of the terminal overlaps the gate line in the direction.
Ding does not expressly disclose the limitations of claim 16.
However, in an analogous art, An-664 teaches
a conductive shielding layer (1630 – Fig. 17 – [0169] – “the first connecting pattern 1510 and the second connecting pattern 1630 may prevent or reduce a crosstalk between the first gate line 1220 and the vertical transmitting line 1720” – this is interpreted as a shielding layer as one of the purposes of a shielding layer is to prevent crosstalk between lines, element 1220 is the electrode of gate line 1210) that is interposed between a fanout line (1720 – Fig. 17 – {[0132] – “vertical transmitting line 1720”}, {[0069] – “transmitting line FL may be a fan-out line” – this is considered a fanout line) of the plurality of fanout lines ([0069] – “first to fourth data lines DL1, DL2, DL3, and DL4, a first transmitting line FL1, and a second transmitting line FL2 may be located in the display area DA. For example, the transmitting line FL may be a fan-out line electrically connecting the data driver DDV and the data line DL” – this describes a plurality of fanout lines) and a conductive portion of the terminal (1510 – Fig. 17 – {[0130] – “third conductive pattern 1500 may include a first connecting pattern 1510”}, {[0131] – “first connecting pattern 1510 may transmit the initialization voltage AINT to the seventh transistor T7” – this is interpreted as a conductive portion of the terminal) , wherein the conductive portion of the terminal (1510) is interposed between the conductive shielding layer and a gate line (1210 – Fig. 17 – [0165] – “first gate line 1210”) of the plurality of gate lines ([0132] – “the first connecting pattern 1510 may overlap the first gate line 1210, the fourth gate line 1330” – this is a plurality of gate lines) and wherein the conductive portion of the terminal (1510) overlaps the gate line in the direction ([0169] – “the first gate line 1210, the first connecting pattern 1510, the second connecting pattern 1630, and the vertical transmitting line 1720 may overlap each other in region C of FIG. 17. For example, the first connecting pattern 1510 and the second connecting pattern 1630 may prevent or reduce a crosstalk between the first gate line 1220 and the vertical transmitting line 1720”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer and conductive shielding layer structure as taught by An into Ding.
An ordinary artisan would have been motivated to use the known technique of An in the manner set forth above to produce the predictable result [0169] – “the first gate line 1210, the first connecting pattern 1510, the second connecting pattern 1630, and the vertical transmitting line 1720 may overlap each other in region C of FIG. 17. For example, the first connecting pattern 1510 and the second connecting pattern 1630 may prevent or reduce a crosstalk between the first gate line 1220 and the vertical transmitting line 1720.”
Allowable Subject Matter
Claims 1-18 are allowable.
Regarding claim 1, prior art of record fails to teach or suggest a conductive that forms a first terminal for the drive transistor; and
a conductive shielding layer that is interposed between the conductive layer and a fanout line of the plurality of fanout lines in the direction, wherein the conductive layer is interposed between a gate line of the plurality of gate lines and the conductive shielding layer in the direction.
Claims 2 – 18 depend on claim 1 and are therefore allowable.
Pertinent Art
For the benefits of the Applicant, US-20240040866-A1, US-20230094885-A1, US-20230354655-A1, US-10707282-B1, and US-20020171086-A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the conductive and shielding layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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