Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 16, 25 and 29 have been considered, a new rejection has been made. Claims 1, 16, 25 and 29 are rejected under 35 U.S.C 103 (See 103
rejection of claims 1 and 16 below).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 16, 19, 25, 27, 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over T. Richardson et al., “Design of Low-Density Parity Check Codes for 5G New Radio”, IEEE Communications Magazine, 56(3), 28-34, March 2018 (hereinafter Richardson), in view of US 20050152408 A1 (hereinafter Jeong) and WO 2019038698 A1 (hereinafter Sandberg).
Regarding claim 1, Richardson teaches generate a low-density parity-check code according to a
base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein a first set of information nodes of the plurality of variable nodes comprise second degree nodes corresponding to two check nodes of the plurality of check nodes (Richardson Fig. 4 and 5; page 29, LDPC Tanner graphs are bipartite graphs where one set of nodes, the variable nodes, correspond to bits in the codeword, and the other set of nodes, the check nodes, correspond to the parity checks that the bits must satisfy; page 30, The base graph for the core has a small number (e.g., mcore = 4) of parity checks and some number (e.g., kbmax =22) of information variable nodes and mcore parity variable nodes. page32, The base core information bits other than the two puncture variable nodes discussed above will typically have low core degree. in BG2 some degree 2s have been included. page 29, degree two variable nodes, which simplifies encoding and improves performance. page33, LDPC codes generated using the design philosophy described. ),
encode a plurality of information nodes and a plurality of parity nodes according to the base graph (Richardson Fig. 5 Sketch of base parity check structure for the 5G NR LDPC code, information columns (i.e. information nodes), core parity columns (parity nodes); Fig. 6, page 33, The performance of LDPC codes generated using the design philosophy described is shown in Fig. 6. Note: this implies encoding. ),
Richardson does not explicitly teach LDPC base graph is selected based at least in part on a modulation order satisfying a threshold.
Sandberg in the same or similar field of endeavor teaches LDPC base graph is selected based at least in part on a modulation order satisfying a threshold (Sandberg page 13, In a sixth group of embodiments, instead of specifying a base graph for each MCS index, a rule can be specified to use BG2 if the MCS index is smaller (or larger) than a certain value, otherwise use BG1.).
By modifying Richardson’s teachings of generate a low-density parity-check code according to a base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein a first set of information nodes of the plurality of variable nodes comprise second degree nodes corresponding to two check nodes of the plurality of check nodes, encode a plurality of information nodes and a plurality of parity nodes according to the base graph with Sandberg’s teachings of LDPC base graph is selected based at least in part on a modulation order satisfying a threshold, the modification results in
generate, based at least in part on a modulation order satisfying a threshold, a low-density parity-check code according to a base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein a first set of information nodes of the plurality of variable nodes comprise second degree nodes corresponding to two check nodes of the plurality of check nodes, encode a plurality of information nodes and a plurality of parity nodes according to the base graph.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Richardson with Sandberg’s above teachings. The motivation is achieving large performance gain (Sandberg page 11).
Richardson in view of Sandberg does not explicitly teach An apparatus for wireless communications at a transmitting device, comprising: at least one processor; and at least one memory coupled with the at least one processor, the at least one memory storing instructions executable by the at least one processor, individually or in any combination, to cause the apparatus to:
wherein a first quantity of the first set of information nodes corresponds to a first significance level of a plurality of significance levels, and a second quantity of the first set of information nodes less than the first quantity corresponds to a second significance level of the plurality of significance levels, the first significance level greater than the second significance level; and transmit a signal comprising a plurality of information bits and a plurality of parity bits based at least in part on the encoding the plurality of information nodes and the plurality of parity nodes.
Jeong in the same or similar field of endeavor teaches An apparatus for wireless
communications at a transmitting device, comprising (Jeong Fig. 5, [0087] FIG. 5 is a block diagram of a data transmission apparatus. [0017]an apparatus for transmitting information bits after coding the information bits with Low Density Parity Check (LDPC) codes having unequal error probability values in a wireless communication system.):
at least one processor (Jeong [0088] a data transmission apparatus includes a channel encoder 501, a signal mapper 503 and a modulator 505. [0089] The channel encoder 501 can be an LDPC encoder in a typical mobile communication system. [0091] The data transmission apparatus includes a bit arrangement controller 507.); and
at least one memory coupled with the at least one processor, the at least one memory storing instructions executable by the at least one processor, individually or in any combination, to cause the apparatus to (Jeong [0024] a memory … for coding the information bits.):
wherein a first quantity of the first set of information nodes corresponds to a first significance level of a plurality of significance levels, and a second quantity of the first set of information
nodes less than the first quantity corresponds to a second significance level of the plurality of significance levels, the first significance level greater than the second significance level (Jeong [0017]The apparatus comprises a LDPC encoder for mapping high information bits to low variable nodes and low information bits to high variable nodes, the high information bits having high importance priorities and the low information bits having low importance priorities from among the information bits, wherein the low variable nodes are variable nodes having low error probability values and the high variable nodes are variable nodes having high error probability values.
[0064] effectively coding information having bits of different degrees of importance by using the difference between error probability values of the nodes.
[0065] FIG. 3 is a diagram illustrating a factor graph of an LDPC code having unequal error probability values according to an embodiment of the present invention.
[0067] V.N1 303, V.N2 305, V.N3 307 and V.N4 309 are variable nodes of an information part 301 in which information bits are mapped.
[0068] The lines connected to each variable node represents edges connected to multiple check nodes and the number of edges connected to each node implies the degree of the node. That is, V.N1 303 has a degree of 6 because 6 edges are connected to V.N1 303, and V.N2 305 has a degree of 5 because 5 edges are connected to V.N2 305. As described above, the higher the degree is, the smaller the error probability value of the information bits mapped to the corresponding node is.
Note: as shown in Fig. 3, V.N2 and V.N3 are degree 5 nodes, V.N4 is degree 4 node. The significance level is associated with the error probability. The smaller the error probability is, the higher the significance level is. The significance level of V.N2 and V.N3 (i.e. the first significance level) is higher than the significance level of V.N4 (i.e. the second significance level). The first quantity is 2, the second quantity is 1.); and
transmit a signal comprising a plurality of information bits and a plurality of parity bits based at least in part on the encoding the plurality of information nodes and the plurality of parity nodes (Jeong Fig. 3, Information part 301, Parity part 311; [0067] variable nodes of an information part 301 in which information bits are mapped. variable nodes of a parity part 311 in which parity bits generated by mapping the information bits are mapped.
Fig. 5, Transmission signal. [0093] The modulator 505 ...transmitting the signal to a transmission link. ).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Richardson as modified by Sandberg with Jeong’s above teachings. The motivation is improving the performance of the system (Jeong [0122]).
Regarding claim 16, Richardson teaches generate the low-density parity-check code according
to a base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein a first set of information nodes of the plurality of variable nodes comprise second degree nodes corresponding to two check nodes of the plurality of check nodes (Richardson Fig. 4 and 5; page 29, LDPC Tanner graphs are bipartite graphs where one set of nodes, the variable nodes, correspond to bits in the codeword, and the other set of nodes, the check nodes, correspond to the parity checks that the bits must satisfy; page 30, The base graph for the core has a small number (e.g., mcore = 4) of parity checks and some number (e.g., kbmax =22) of information variable nodes and mcore parity variable nodes. page32, The base core information bits other than the two puncture variable nodes discussed above will typically have low core degree. in BG2 some degree 2s have been included. page 29, degree two variable nodes, which simplifies encoding and improves performance. page33, LDPC codes generated using the design philosophy described.); and
decode the plurality of information bits based at least in part on the plurality of parity bits, a plurality of information nodes, and a plurality of parity nodes, the plurality of information nodes and the plurality of parity nodes corresponding to the base graph (Richardson Fig. 5 Sketch of base parity check structure for the 5G NR LDPC code, information columns (i.e. information nodes), core parity columns (parity nodes); page 30, The base graph for the core has a small number (e.g., mcore = 4) of parity checks and some number (e.g., kbmax =22) of information variable nodes and mcore parity variable nodes; page 28, LDPC decoders operate by repeatedly decoding single parity check codes involving a small number of bits. Decoding of these parity checks is operationally independent and hence easily parallelized. page 29, Figure 4 provides an example of the two representations. The graphical representation is useful for visualization since decoding is best understood as a computational process that passes messages along the edges of graph, where the messages represent probability distributions on the associated bit, while processing and updating the messages at the nodes; page32, The base core information bits other than the two puncture variable nodes discussed above will typically have low core degree. in BG2 some degree 2s have been included; ), Richardson does not explicitly teach LDPC base graph is selected based at least in part on a modulation order satisfying a threshold.
Sandberg in the same or similar field of endeavor teaches LDPC base graph is selected based at least in part on a modulation order satisfying a threshold (Sandberg page 13, In a sixth group of embodiments, instead of specifying a base graph for each MCS index, a rule can be specified to use BG2 if the MCS index is smaller (or larger) than a certain value, otherwise use BG1.).
By modifying Richardson’s teachings of generate the low-density parity-check code according to a base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein a first set of information nodes of the plurality of variable nodes comprise second degree nodes corresponding to two check nodes of the plurality of check nodes; and decode the plurality of information bits based at least in part on the plurality of parity bits, a plurality of information nodes, and a plurality of parity nodes, the plurality of information nodes and the plurality of parity nodes corresponding to the base graph with Sandberg’s teachings of LDPC base graph is selected based at least in part on a modulation order satisfying a threshold, the modification results in
generate, based at least in part on a modulation order satisfying a threshold, the low-density parity-check code according to a base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein a first set of information nodes of the plurality of variable nodes comprise second degree nodes corresponding to two check nodes of the plurality of check nodes; and decode the plurality of information bits based at least in part on the plurality of parity bits, a plurality of information nodes, and a plurality of parity nodes, the plurality of information nodes and the plurality of parity nodes corresponding to the base graph.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Richardson with Sandberg’s above teachings. The motivation is achieving large performance gain (Sandberg page 11).
Richardson in view of Sandberg does not explicitly teach An apparatus for wireless communications at a receiving device, comprising: at least one processor; and at least one memory coupled with the at least one processor, the at least one memory storing instructions executable by the at least one processor, individually or in any combination, to cause the apparatus to:
receive a signal comprising a plurality of information bits and a plurality of parity bits corresponding to a low-density parity-check code;
wherein a first quantity of the first set of information nodes corresponds to a first significance level of a plurality of significance levels, and a second quantity of the first set of information nodes less than the first quantity corresponds to a second significance level of the plurality of significance levels, the first significance level greater than the second significance level.
Jeong in the same or similar field of endeavor teaches An apparatus for
wireless communications at a receiving device, comprising (Jeong Fig. 6, [0095] FIG. 6 is a block diagram of a data reception apparatus. [0018]an apparatus for receiving information bits coded with Low Density Priority Check (LDPC) codes having unequal error probability values in a wireless communication system which channel-codes and transmits the information bits. ):
at least one processor (Jeong [0096] a data reception apparatus includes a demodulator 601, an inverse signal mapper 603, and a channel decoder 605. [0097] a signal received by an antenna (not shown) through a wireless channel is input to the demodulator 601 after being radio-processed by a radio-processor (not shown). The channel decoder 605 is an LDPC decoder. ); and
at least one memory coupled with the at least one processor, the at least one memory storing instructions executable by the at least one processor, individually or in any combination, to cause the apparatus to (Jeong [0024] a memory … for decoding the information bits.):
receive a signal comprising a plurality of information bits and a plurality of parity bits corresponding to a low-density parity-check code (Jeong [0018]an apparatus for receiving information bits coded with Low Density Priority Check (LDPC) codes having unequal error probability values in a wireless communication system which channel-codes and transmits the information bits.
Fig. 6, Transmission signal; [0097] a signal received by an antenna (not shown) through a wireless channel. Note: tranmission signal in Fig. 6 is received from the transmitting appratus in Fig. 5.
Fig. 3, Information part 301, Parity part 311; [0067] variable nodes of an information part 301 in which information bits are mapped. variable nodes of a parity part 311 in which parity bits generated by mapping the information bits are mapped. );
wherein a first quantity of the first set of information nodes corresponds to a first significance level of a plurality of significance levels, and a second quantity of the first set of information nodes less than the first quantity corresponds to a second significance level of the plurality of significance levels, the first significance level greater than the second significance level (Jeong [0018] The apparatus comprises a LDPC decoder for de-mapping corresponding to a predetermined encoder for mapping high information bits to low variable nodes and low information bits to high variable nodes, the high information bits having high importance priorities and the low information bits having low importance priorities from among the information bits, wherein the low variable nodes are variable nodes having low error probability values and the high variable nodes are variable nodes having high error probability values in a factor graph of the LDPC codes.
[0064] effectively decoding information having bits of different degrees of importance by using the difference between error probability values of the nodes.
[0064] effectively coding information having bits of different degrees of importance by using the difference between error probability values of the nodes.
[0065] FIG. 3 is a diagram illustrating a factor graph of an LDPC code having unequal error probability values according to an embodiment of the present invention.
[0067] V.N1 303, V.N2 305, V.N3 307 and V.N4 309 are variable nodes of an information part 301 in which information bits are mapped.
[0068] The lines connected to each variable node represents edges connected to multiple check nodes and the number of edges connected to each node implies the degree of the node. That is, V.N1 303 has a degree of 6 because 6 edges are connected to V.N1 303, and V.N2 305 has a degree of 5 because 5 edges are connected to V.N2 305. As described above, the higher the degree is, the smaller the error probability value of the information bits mapped to the corresponding node is.
Note: as shown in Fig. 3, V.N2 and V.N3 are degree 5 nodes, V.N4 is degree 4 node. The significance level is associated with the error probability. The smaller the error probability is, the higher the significance level is. The significance level of V.N2 and V.N3 (i.e. the first significance level) is higher than the significance level of V.N4 (i.e. the second significance level). The first quantity is 2, the second quantity is 1.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Richardson as modified by Sandberg with Jeong’s above teachings. The motivation is improving the performance of the system (Jeong [0122]).
Claims 25 and 29 recite similar limitations of claims 1 and 16 respectively, are thus rejected under similar rational.
Regarding claim 3, Richardson in view of Sandberg and Jeong (hereinafter combination)
discloses The apparatus of claim 1.
Jeong teaches wherein each significance level of the plurality of significance levels corresponds to a respective channel reliability, where a higher significance level corresponds to a higher channel reliability (Jeong [0017] mapping high information bits to low variable nodes and low information bits to high variable nodes, the high information bits having high importance priorities and the low information bits having low importance priorities from among the information bits, wherein the low variable nodes are variable nodes having low error probability values and the high variable nodes are variable nodes having high error probability values in a factor graph of the LDPC codes. Note: a low error probability value corresponds to high channel reliability. ).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Jeong’s above teachings. The motivation is improving the performance of the system (Jeong [0122]).
Claim 19 and 27 recite similar limitations of claim 3, are thus rejected under similar rational.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Richardson in view of Sandberg and Jeong as applied to claim 1 above, and further in view of US 20160308557 A1 (hereinafter Raimondi).
Regarding claim 5, the combination discloses The apparatus of claim 1.
The combination does not explicitly teach wherein the instructions are further executable by the
at least one processor to cause the apparatus to: map the plurality of information nodes to a plurality of bits according to an interleaver indicating an inverse relationship between a degree and a significance level of each respective information node of the plurality of information nodes.
Raimondi in the same or similar field of endeavor teaches wherein the instructions are further
executable by the at least one processor to cause the apparatus to:
map the plurality of information nodes to a plurality of bits according to an interleaver indicating an inverse relationship between a degree and a significance level of each respective information node of the plurality of information nodes (Raimondi [0067] the subframes coded by application of an algebraic correcting code in the step 104 are interleaved using an interleaver, the function of which is to correlate the bits of the coded subframes with the systematic variable nodes of the bipartite graph of the LDPC systematic correcting code. The correlation depends, on the one hand, on the average priority level of the subframe and, on the other hand, on the degree of the systematic variable nodes.
[0072] associating the subframes of highest priority levels with the systematic variable nodes of lowest degrees.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Raimondi’s above teachings. The motivation is providing a differentiated protection to the data to be transmitted as a function of different priority levels (Raimondi [0004]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Richardson in view of Sandberg and Jeong as applied to claim 1 above, and further in view of F. Steiner et al., “Design of robust, protograph based LDPC codes for Rate-Adaptation via probabilistic shaping.”, Proceedings of 2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), 2016 (hereinafter Steiner).
Regarding claim 8, the combination discloses The apparatus of claim 1.
The combination does not explicitly teach wherein the instructions are further executable by the
at least one processor to cause the apparatus to: select a uniform modulation constellation or a probabilistic shaping modulation constellation, wherein the base graph and generating the low-density parity-check code are based at least in part on the selecting.
Steiner in the same or similar field of endeavor teaches wherein the instructions are further
executable by the at least one processor to cause the apparatus to:
select a uniform modulation constellation or a probabilistic shaping modulation constellation, wherein the base graph and generating the low-density parity-check code are based at least in part on the selecting (Steiner Abstract, the design of robust, protograph based low-density parity-check (LOPC) codes for rate-adaptive communication via probabilistic shaping is considered. The considered design uses a single 16 amplitude-shift keying ( ASK) constellation and a robust 13/16 0.813 rate
LDPC code to operate between 0.7 to 2.7 bits per channel use. ).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Steiner’s above teachings. The motivation is supporting robust LDPC code design for rate adaptive communication (Steiner Abstract).
Claim(s) 11, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Richardson in view of Sandberg and Jeong as applied to claims 1 and 16 above, and further in view of US 20190013900 A1 (hereinafter Patel).
Regarding claim 11, the combination discloses The apparatus of claim 1.
Although The combination teaches wherein the instructions are further executable by the
at least one processor to cause the apparatus to: wherein generating the base graph is based at least in part on the modulation order satisfying a modulation order threshold (Richardson Fig. 4 and 5; page 29, 30, 32 and 33; Sandberg page 13 cited in claim 1 rejection above.), the combination does not explicitly teach receive control signaling indicating a modulation order.
Patel in the same or similar field of endeavor teaches receive control signaling indicating a modulation order (Patel [0149] UE 120a receives control information (e.g., a DCI from BS 110a) indicating an MCS.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Patel’s above teachings. The motivation is improving communication efficiency (Patel [0063]).
Claim 21 recites similar limitations of claim 11, is thus rejected under similar rational.
Allowable Subject Matter
Claims 2, 6-7, 9-10, 12-15, 17, 20, 22-24, 26 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Z Sun whose telephone number is (571)270-0750. The examiner can normally be reached Monday-Friday 0800am-0500pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Moo Jeong can be reached at 571-272-9617. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.Z.S./Examiner, Art Unit 2418
/Moo Jeong/Supervisory Patent Examiner, Art Unit 2418