DETAILED ACTION
This action is in response to the claims filed 07/13/2026 for Application number 18/328,629. Claim 1 has been amended and claims 9-20 are new. Thus, claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 7-8, 14-17 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1,
Step 1 Analysis: Claim 1 is directed to a process, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 1 recites, in part, the limitations of:
generating a list of activation memory matrixes (AMM) addresses, wherein each address in the list of addresses points to an activations row that each one of its activation components needs to be multiplied by a given non-zero weight and to be accumulated in a different vector multiplication calculations can be considered to be a mathematical calculation
implementing vector multiplication on the rows of activations and non-zero weights, including removing weight sparsity from the vector multiplications can be considered to be a mathematical calculation
These limitations as drafted, are processes that, under broadest reasonable interpretation, covers the recitation of mathematical calculations which falls within the “Mathematical concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A Prong 2 Analysis: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements - “scalable deep neural networks, multiple neural processing units (NPUs), weight map memory, and a routing multiplexer”. Thus, these elements in the claim is recited at a high level of generality such that they amount to no more than mere instructions to apply the exception using a generic computer component. Please see MPEP 2106.05(f). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claim further recites:
the method performed in the sDNA comprising multiple neural processing units (NPUs), the sDNA including an activation map memory configured to store activation map words indicating positions of non-zero activation values and a weight map memory configured to store weight map words indicating positions of non-zero weight values. This limitation is an insignificant extra-solution activity.
storing in the AMM rows of activations, each row of activations including a corresponding plurality of activations to be multiplied with a same non-zero weight. This limitation is an insignificant extra-solution activity.
fetching activations from a compressed activation memory and weights from a pruned weight memory based on the activation map words and the weight map words This limitation is an insignificant extra-solution activity.
wherein control logic controls a routing multiplexer to route the fetched activations and weights to multiply-accumulate (MAC) units of the multiple NPUs and balance calculation load among the MAC units.
This limitation is an insignificant extra-solution activity.
Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim as a whole is directed to an abstract idea.
Step 2B Analysis: The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of utilizing scalable deep neural networks to perform the steps of the claimed process amount to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Furthermore, the limitations of:
the method performed in the sDNA comprising multiple neural processing units (NPUs), the sDNA including an activation map memory configured to store activation map words indicating positions of non-zero activation values and a weight map memory configured to store weight map words indicating positions of non-zero weight values.
storing in the AMM rows of activations, each row of activations including a corresponding plurality of activations to be multiplied with a same non-zero weight
fetching activations from a compressed activation memory and weights from a pruned weight memory based on the activation map words and the weight map words
are well-understood, routine, and conventional, as evidenced by MPEP §2106.05(d)(II)(iv), “Storing and retrieving information in memory”.
Additionally, the limitation of:
wherein control logic controls a routing multiplexer to route the fetched activations and weights to multiply-accumulate (MAC) units of the multiple NPUs and balance calculation load among the MAC units is well-understood, routine, and conventional, as evidenced by MPEP §2106.05(d)(II)(I), “receiving or transmitting data over a network”.
These limitations therefore remain insignificant extra-solution activity even upon reconsideration, and does not amount to significantly more. Even when considered in combination, these additional elements amount to mere instructions to apply the exception using generic computer components and insignificant extra-solution activity, which cannot provide an inventive concept. The claim is not patent eligible.
Regarding claim 2, the rejection of claim 1 is further incorporated, and further, the claim recites: generating different combinations of vector multiplication tensors for machine learning models or algorithms. This claim recites additional mathematical steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 3, the rejection of claim 1 is further incorporated, and further, the claim recites: supporting at least one of multiple different parallel modes including at least one of: a multiple points (pixels) parallel scheme, a lines parallel scheme, a multiple input channels parallel scheme, or a multiple output channels parallel scheme. This limitation amounts to generally linking the judicial exception to a field of use or technological environment. Please see MPEP 2106.05(h).
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 4, the rejection of claim 1 is further incorporated, and further, the claim recites: implementing a sequential execution NPU, a concurrent execution NPU, or a combination of a sequential execution NPU and a concurrent execution NPU to implement the vector multiplication. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 7, the rejection of claim 1 is further incorporated, and further, the claim recites: further comprising supporting different size convolution operations. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 8, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein supporting different size convolution operations comprises supporting two different n*n convolution operations, and wherein n in a first of the convolution operations has a first value that is different than a second value of n in a second of the convolution operations. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding Claims 14-17 and 20, they recite features similar to claims 1-4 and 7 and are rejected for at least the same reasons therein.
Claims 5, 6, 18 and 19 recite patent eligible subject matter thus would integrate the judicial exception into a practical application and amount to significantly more.
Allowable Subject Matter
Claims 9-13 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9:
No prior art was uncovered which fairly discloses all of the limitations of claim 9, specifically, the combination of limitations of:
the method performed in the sDNA comprising multiple neural processing units (NPUs), the sDNA including an activation map memory configured to store activation map words indicating positions of non-zero activation values and a weight map memory configured to store weight map words indicating positions of non-zero weight values, the method comprising:
generating a list of activation memory matrixes (AMM) addresses, wherein each address in the list of addresses points to an activations row that each one of its activation components needs to be multiplied by a given non-zero weight and to be accumulated in different vector multiplication calculations;
storing in the AMM rows of activations, each row of activations including a corresponding plurality of activations to be multiplied with a same non-zero weight;
fetching activations from a compressed activation memory and weights from a pruned weight memory based on the activation map words and the weight map words;
implementing vector multiplication on the rows of activations and non-zero weights, including removing weight sparsity from the vector multiplications, wherein control logic controls a routing multiplexer to route the fetched activations and weights to multiply-accumulate (MAC) units of the multiple NPUs and balance calculation load among the MAC units; and
implementing a sequential execution NPU, a concurrent execution NPU, or a combination of a sequential execution NPU and a concurrent execution NPU to implement the vector multiplication, wherein:
implementing a sequential execution NPU comprises storing back (feedback) an output of each neural network layer to a current AMM layer; and
implementing a concurrent execution NPU comprises allocating different hardware resources to different DNN layers to process the DNN layers in parallel (concurrently).
The closest prior art of record is Woo et al. (“US 20200012608 A1”) which discloses exploiting input data sparsity in convolutional neural networks, however the prior art does not explicitly disclose the specific sDNA/AMM architecture required by the claims particularly, the method performed in the sDNA comprising multiple neural processing units (NPUs), the sDNA including an activation map memory configured to store activation map words indicating positions of non-zero activation values and a weight map memory configured to store weight map words indicating positions of non-zero weight values, the method comprising:
generating a list of activation memory matrixes (AMM) addresses, wherein each address in the list of addresses points to an activations row that each one of its activation components needs to be multiplied by a given non-zero weight and to be accumulated in different vector multiplication calculations;
The specific details regarding the generation of AMM addresses was not disclosed in the prior art of Woo or found in an updated prior art search.
Claims 1-4, 7-8, 14-17 and 20 are objected to as being allowable over prior art if the outstanding 101 rejection were to be withdrawn. None of the prior art, either alone or in combination, fairly discloses limitations of claims 1 and 14 for the same reasons set forth above as claim 9.
Claims 5, 6, 18 and 19 are objected to as being allowable as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
In light of applicant’s amendments and remarks regarding the prior art rejection, the rejection has been withdrawn.
Regarding the 35 U.S.C. §101 Rejection:
Applicant appears to assert that amended claim 1 requires a specific architecture and control behavior and is part of a hardware dataflow implementation thus is not directed towards a mathematical concept anymore. Examiner respectfully disagrees. The newly amended limitations all recite insignificant extra-solution activities and are considered to be well-understood, routine and conventional steps as laid out in MPEP §2106.05(d)(II)(iv), “Storing and retrieving information in memory” and MPEP §2106.05(d)(II)(I), “receiving or transmitting data over a network”. Applicant further asserts the control logic and routing multiplexer are not generic computer components but are specific hardware structures that implement the sDNA algorithm. Examiner respectfully disagrees. These additional elements that are in the claim are recited in a broad and generic manner and merely used as tools to perform generic computer functions (i.e. storing data, routing data, etc…). Therefore, examiner asserts that these additional elements do not integrate the judicial exception into a practical application nor amount to significantly more.
Applicant asserts that the specific architecture recited in the claim amounts to concrete technological improvements. Examiner respectfully disagrees. As noted above, the claims only recite broad and generic computer components that are merely used as tools to apply the judicial exception. No specific details are recited in the claim that would reflect such a technological improvement as the claims only broadly recite storing data in memory, routing data, etc... which are well-understood, routine and conventional computer functions. Therefore, applicant’s arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL H HOANG whose telephone number is (571)272-8491. The examiner can normally be reached Mon-Fri 8:30AM-4:30PM.
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/MICHAEL H HOANG/PRIMARY EXAMINER, Art Unit 2122
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