DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
THIS ACTION IS MADE FINAL.
Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Status of the Application
The following is a Final Office Action in response to Examiner's communication of 05/12/2026, Applicant, on 08/11/2026.
Status of Claims
Claims 1 is currently amended.
Claims 2, 3, 5, 6, 9, 10, 12, 13, and 16-20 were previously presented.
Claims 4-6 are canceled.
Claims 9-23 are new.
Claims 1-3 and 7-23 are currently pending following this response.
New matter
No new matter has been added to the amended claims.
Response to Arguments - 35 USC § 101
The arguments have been fully considered and found to be persuasive.
The mathematical operation of claim 1 is being used as part of a specific neural processing architecture to alter how the NPU performs neural network computation which is regarded as an improvement to computer functionality or other technology. See Enfish, McRO, Finjan…
In conclusion, the Examiner withdraws the rejections of the pending claims under 35 USC § 101 in the present office action.
Response to Arguments - 35 USC § 103
The arguments have been fully considered, but they are not persuasive.
Applicant’s arguments are moot in view of the new references cited and used by the Examiner.
In conclusion, the Examiner maintains the rejections of the pending claims under 35 USC § 103 in the present office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 9, 13, 18, and 22 are rejected under 35 U.S.C. 103 as being un-patentable over Hegde et al., “UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition,” ISCA 2018 in view of Huynh (US 20210247984A1) and in further view of Venkatesh at al. (US 20210012186A1)
Regarding claim 1. A method of removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together, comprising: adding all activations that need to be multiplied with a common weight to generate a sum of activations; multiplying the sum of activations with the common weight, and implementing a sequential execution neural processing unit (NPU), a concurrent execution NPU, or a combination of a sequential execution NPU and a concurrent execution NPU to implement vector multiplication, wherein: implementing the sequential execution NPU comprises storing back (feedback) an output of each neural network layer to a current Activation Memory Matrix (AMM) layer and reusing hardware resources to calculate different layers of a same neural network; and implementing the concurrent execution NPU comprises allocating different hardware resources to different deep neural network (DNN) layers to process the DNN layers in parallel (concurrently) and providing results of each DNN layer to another hardware logic that executes a next DNN layer.
Hegde teaches removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together. Hegde states that repeated weights can be exploited through dot-product factorization. Activations that would be multiplied by the same weight are grouped together and locally summed, after which the sum is multiplied by the repeated weight, see Abstract and page 8 “removing redundant weight”, see also page 3 “factorizing common weight”.
Hegde does not specifically teach; however, Huynh teaches a neural-network accelerator in which intermediate layer outputs are stored in memory and then supplied back into the processing-engine array for computation of the next layer see para. 0044 “input to a next layer”.
Hegde in view of Huynh does not specifically teach; however, Venkatesh teaches different PE groups operating on different neural-network layers, with output from one layer fed to the next and operations for multiple layers executing in parallel in a pipeline see summary and para. 0042. Venkatesh also describes corresponding groups of PE circuits are allocated to different layers, see Abstract.
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together of Hegde with the intermediate layer outputs are supplied back into the processing-engine of Huynh, and the output from one layer fed to the next and operations for multiple layers executing in parallel in a pipeline of Venkatesh since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing neural network redundancy removal processing.
Regarding claim 9. Hegde in view of Huynh, in further view of Venkatesh teaches all of the limitations of claim 1 (as above). Further, Hegde teaches wherein adding all activations that need to be multiplied with a common weight to generate a sum of activations comprises accumulating, at an activation lookup table (ALUT) memory location pointed to by an output of a pruned weight memory, all activation values that need to be multiplied with a specific weight value; and multiplying the sum of activations with the common weight comprises multiplying the accumulated intermediate result with a matching weight or de-quantized weight that resides in a weight lookup table (WLUT) memory. Hegde teaches using the weight identity/index to determine which activation group is accumulated, see page 14 second paragraph “indexed by activation”.
Regarding claim 13, the claim recites analogous limitations to claim 1 above and is therefore rejected on the same premise.
Regarding claim 18, the claim recites analogous limitations to claim 9 above and is therefore rejected on the same premise.
Regarding claim 22, the claim recites analogous limitations to claim 1 above and is therefore rejected on the same premise.
Claims 2-3, 7-8, 14-15, and 16-17 are rejected under 35 U.S.C. 103 as being un-patentable over Hegde in view of Huynh, in further view of Venkatesh, and in further view of Yu et al. (US 20200151019 A1)
Regarding claim 2. Hegde in view of Huynh, in further view of Venkatesh teaches all of the limitations of claim 1 (as above). Hegde in view of Huynh and in further view of Venkatesh does not specifically teach; however, Yu teaches further comprising generating different combinations of vector multiplication tensors for machine learning models or algorithms.
Yu teaches a configurable CNN accelerator that maps CNNs of different structures onto configurable parallel computation modes. Its calculation hardware can perform different combinations of vector inner products, including one long vector or multiple shorter vectors, see at least para. 0112.
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together of Hegde with the intermediate layer outputs are supplied back into the processing-engine of Huynh, the output from one layer fed to the next and operations for multiple layers executing in parallel in a pipeline of Venkatesh, and generating different combinations of vector multiplication tensors of Yu since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing neural network redundancy removal processing.
Regarding claim 3. (Hegde in view of Huynh, in further view of Venkatesh teaches all of the limitations of claim 1 (as above). Hegde in view of Huynh and in further view of Venkatesh does not specifically teach; however, Yu teaches further comprising supporting at least one of multiple different parallel modes including at least one of: a multiple points (pixels) parallel scheme, a lines parallel scheme, a multiple input channels parallel scheme, or a multiple output channels parallel scheme.
Yu teaches selecting CNN parallel-computation modes and particularly teaches parallel input and output channel computing. It states that the architecture can vary the number of parallel input channels versus output channels and describes channel-level parallelism as providing flexibility in resource utilization, para. 0051-0052 multiple channels.
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together of Hegde with the intermediate layer outputs are supplied back into the processing-engine of Huynh, the output from one layer fed to the next and operations for multiple layers executing in parallel in a pipeline of Venkatesh, and supporting parallel scheme of Yu since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing neural network redundancy removal processing.
Regarding claim 7-8. Hegde in view of Huynh, in further view of Venkatesh teaches all of the limitations of claim 1 (as above). Hegde in view of Huynh and in further view of Venkatesh does not specifically teach; however, Yu teaches further comprising supporting different size convolution operations, wherein supporting different size convolution operationscomprises supporting two different n*n convolution operations, and wherein n in a first of the convolution operations has a first value that is different than a second value of n in a second of the convolution operations.
Yu teaches hardware intended to support CNN kernels of different sizes and a unified data-acquisition scheme applicable to arbitrary kernel sizes, see para. 0132.
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together of Hegde with the intermediate layer outputs are supplied back into the processing-engine of Huynh, the output from one layer fed to the next and operations for multiple layers executing in parallel in a pipeline of Venkatesh, and supporting different size convolution operations of Yu since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing neural network redundancy removal processing.
Regarding claims 14-15, claims 14-15 recite substantially similar limitations as claim 2-3, respectively; therefore, claims 14-15 are rejected with the same rationale, reasoning, and motivation provided above for claims 2-3, respectively.
Regarding claims 16-17, claims 16-17 recite substantially similar limitations as claim 7-8, respectively; therefore, claims 16-17 are rejected with the same rationale, reasoning, and motivation provided above for claims 7-8, respectively.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being un-patentable over Hegde in view of Huynh, in further view of Venkatesh, and in further view of Yoshida (US 20220100470 A1)
Regarding claim 10. Hegde in view of Huynh, in further view of Venkatesh teaches all of the limitations of claim 1 (as above). Hegde in view of Huynh and in further view of Venkatesh does not specifically teach; however, Yoshida teaches further comprising gathering activations that need to be multiplied by a weight W and activations that need to be multiplied by a weight -W, reading a pair of the activations simultaneously, subtracting the activation to be multiplied with the negative weight from the activation to be multiplied with the positive weight to generate a subtraction result, and multiplying the subtraction result by the weight W. Yoshida teaches MAC circuitry separately handling positive and negative weights and computing the overall result from positive and negative weighted contributions, Abstract.
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together of Hegde with the intermediate layer outputs are supplied back into the processing-engine of Huynh, the output from one layer fed to the next and operations for multiple layers executing in parallel in a pipeline of Venkatesh, and handling positive and negative weights of Yoshida since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing neural network redundancy removal processing.
Regarding claim 19, the claim recites analogous limitations to claim 10 above and is therefore rejected on the same premise.
Claims 11 and 20 are rejected under 35 U.S.C. 103 as being un-patentable over Hegde in view of Huynh, in further view of Venkatesh, and in further view of Akhlaghi et al., “SnaPEA: Predictive Early Activation for Reducing Computation in Deep CNNs,” ISCA 2018.
Regarding claim 11. Hegde in view of Huynh, in further view of Venkatesh teaches all of the limitations of claim 1 (as above). Hegde in view of Huynh and in further view of Venkatesh does not specifically teach; however, Akhlaghi teaches further comprising, for a neural network using a ReLU non- linear output function, accumulating products having positive weights and thereafter accumulating products having negative weights, and suspending a multiply-accumulate operation when an intermediate accumulation result reaches a negative value. Akhlaghi teaches reorders the weights so the positive contributions are processed first, then processes negative weights while monitoring the partial sum. Once the partial sum becomes negative, computation can terminate because nonnegative activations combined with the remaining negative weights cannot make the sum positive again; ReLU will therefore output zero, see figure 4 “reordered weight”
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together of Hegde with the intermediate layer outputs are supplied back into the processing-engine of Huynh, the output from one layer fed to the next and operations for multiple layers executing in parallel in a pipeline of Venkatesh, and accumulating products having negative weights, and suspending a multiply-accumulate operation when an intermediate accumulation result reaches a negative value of Akhlaghi since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing neural network redundancy removal processing.
Regarding claim 20, the claim recites analogous limitations to claim 11 above and is therefore rejected on the same premise.
Claims 12, 21, and 23 are rejected under 35 U.S.C. 103 as being un-patentable over Hegde in view of Huynh, in further view of Venkatesh, and in further view of Dally et al. (US10528864B2).
Regarding claim 12. Hegde in view of Huynh, in further view of Venkatesh teaches all of the limitations of claim 1 (as above). Hegde in view of Huynh and in further view of Venkatesh does not specifically teach; however, Dally teaches further comprising mapping zero weights in a weight map memory and zero activations in an activation map memory, and skipping multiplications corresponding to the mapped zero weights and the mapped zero activations. Dally taches eliminates multiplications having a zero operand and uses compressed representations of both weights and activations; only non-zero weight/activation values are supplied to multipliers, column 3, lines 11-20.
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine removing redundancy of multiplications of a same weight with different activations before adding all multiplication results together of Hegde with the intermediate layer outputs are supplied back into the processing-engine of Huynh, the output from one layer fed to the next and operations for multiple layers executing in parallel in a pipeline of Venkatesh, and compressed representations of both weights and activations of Dally since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing neural network redundancy removal processing.
Regarding claim 21, the claim recites analogous limitations to claim 12 above and is therefore rejected on the same premise.
Regarding claim 23, the claim recites analogous limitations to claim 12 above and is therefore rejected on the same premise.
Conclusion
Applicant's amendments and arguments dated 08/11/2026 necessitated the withdrawal of the 35 USC § 101 and the updating 35 USC § 103 rejections of the pending claims presented in the present Office Action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication from the Examiner should be directed to Abdallah El-Hagehassan whose contact information is (571) 272-0819 and Abdallah.el-hagehassan@uspto.gov The Examiner can normally be reached on Monday- Friday 8 am to 5 pm.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Rutao Wu can be reached on (571) 272-6045. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ABDALLAH A EL-HAGE HASSAN/
Primary Examiner, Art Unit 3623
