DETAILED ACTION
This action is responsive to the communication filed 9 March 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election of Species 1 in the reply filed on 27 October 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 8, 9, and 13-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 27 October 2025.
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-7, 10-12, and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 5-7, 10-12, and 18-20 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Publication No. 2015/0221601 (filed Aug. 1, 2014) (hereinafter “Kim”) in view of U.S. Patent Publication No. 2024/0381530 (effectively filed Sept. 16, 2021) (hereinafter “Na”).
Regarding independent claim 1, Kim discloses: A semiconductor package (FIG. 1N, semiconductor device 100, [0062]), comprising:
a first wiring structure (FIGS. 1A-1N, depicting a lower multilayer wiring structure, [0026]) that includes a plurality of first redistribution patterns that include a plurality of first bottom connection pads (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of first redistributions 112, [0031]) and a plurality of first top connection pads (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of second redistributions 112, [0031]), and
a plurality of first redistribution insulating layers that surround the plurality of first redistribution patterns (FIGS. 1A-1N, first dielectric layer 111 formed as a plurality of layers surrounding the first and second redistributions 112, [0031]);
a second wiring structure (FIGS. 1A-1N, depicting an upper multilayer wiring structure, [0045]) that includes a plurality of second redistribution patterns that include a plurality of second bottom connection pads (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of first redistributions 122, [0045]) and a plurality of second top connection pads (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of second redistributions 122, [0045]), and
a plurality of second redistribution insulating layers that surround the plurality of second redistribution patterns (FIGS. 1A-1N, second dielectric layer 121 formed as a plurality of layers surrounding the first lower and second upper redistributions 122);
a semiconductor chip (FIG. 1N, semiconductor die 130, [0034]) interposed between the first wiring structure and the second wiring structure (FIG. 1N, depicting wherein the semiconductor die 130 is interposed between the upper and lower multilayer wiring structures);
an encapsulant (FIG. 1N, encapsulant 150, [0043]) that fills a space between the first wiring structure and the second wiring structure and that surrounds the semiconductor chip (FIG. 1N, depicting wherein the encapsulant fills a space between the upper and lower multilayer wiring structures and surrounds the semiconductor die 130); and
a plurality of connection structures (FIG. 1N, depicting a plurality of conductive pillars comprising a first conductive pillar 114, a second conductive pillar 124, and a solder cap 114a/124a, [0046], [0072]) that penetrate through the encapsulant and connect the plurality of first top connection pads to the plurality of second bottom connection pads and are arranged around the semiconductor chip (FIG. 1N, depicting wherein the plurality of conductive pillars penetrate through the encapsulant 150 and connect the redistributions 112, 122 of the upper and lower multilayer wiring structures, and are arranged around the semiconductor die 130),
wherein the plurality of connection structures include a plurality of lower connection structures (FIGS. 1A-1N, first conductive pillars 114) of which bottom surfaces contact top surfaces of the plurality of first top connection pads (FIGS. 1A-1N, depicting wherein the bottom of the first conductive pillar 114 contacts the top of the lower multilayer wiring structure),
a plurality of upper connection structures (FIGS. 1A-1N, second conductive pillars 124) of which top surfaces contact bottom surfaces of the plurality of second bottom connection pads (FIGS. 1A-1N, depicting wherein the top of the second conductive pillar 124 contacts the bottom of the upper multilayer wiring structure), and
a plurality of conductive connection layers (FIGS. 1A-1N, solder caps 114a/124a) that contact top surfaces of the plurality of lower connection structures and bottom surfaces of the plurality of upper connection structures (FIGS. 1A-1N, depicting wherein the solder caps 114a/124a contact the top of the first conductive pillars 114 and the bottom of the second conductive pillars 124), and
wherein the uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers and the lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers are in direct contact with the encapsulant (FIGS. 1A-1N, depicting wherein an uppermost dielectric layer 111 of the plurality of layers and a lowermost dielectric layer 121 of the plurality of layers are in direct contact with the encapsulant 150).
Kim does not specifically disclose wherein each of the plurality of first top connection pads protrudes from top surfaces of an uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers.
In the same field of endeavor, Na discloses a semiconductor package (FIG. 1A, depicting a circuit board, [0043]) including a connection pad (FIG. 1A, depicting bump 43, [0090]), wherein each of the plurality of connection pads protrudes from surfaces of a redistribution insulating layers (FIG. 1A, depicting wherein the bump 43 protrudes from a surface of a protective layer 30, [0091]). Regarding the bump 43, in [0090], Na states: “In addition, the width w5 of the second part 43-2 of the third bump 43 is greater than the width w3 of the third pad 23 and the width w4 of the first part 43-1. Accordingly, in the first comparative example, the bonding area with the solder is improved by using the second part 43-2 of the third bump 43.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Kim by adding the bumps 43 of Na to form top connection pads protruding from an uppermost surface of the dielectric layer 111 in order to improve the bonding area of the redistributions 112. See Na [0090].
Kim does not specifically disclose wherein each of the plurality of second bottom connection pads protrudes from bottom surfaces of a lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers.
In the same field of endeavor, Na discloses a semiconductor package (FIG. 1A, depicting a circuit board, [0043]) including a connection pad (FIG. 1A, depicting bump 43, [0090]), wherein each of the plurality of connection pads protrudes from surfaces of a redistribution insulating layers (FIG. 1A, depicting wherein the bump 43 protrudes from a surface of a protective layer 30, [0091]). Regarding the bump 43, in [0090], Na states: “In addition, the width w5 of the second part 43-2 of the third bump 43 is greater than the width w3 of the third pad 23 and the width w4 of the first part 43-1. Accordingly, in the first comparative example, the bonding area with the solder is improved by using the second part 43-2 of the third bump 43.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Kim by adding the bumps 43 of Na to form bottom connection pads protruding from a bottommost surface of the dielectric layer 121 in order to improve the bonding area of the redistributions 122. See Na [0090].
Regarding claim 2, Kim further discloses wherein
the plurality of first redistribution patterns (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of first redistributions 112, [0031]) include a plurality of first redistribution line patterns (FIGS. 1A-1N, the portions of the first redistributions 112 that are flat) and a plurality of first redistribution via patterns (FIGS. 1A-1N, the portions of the first redistributions 112 that are tapered),
wherein the plurality of second redistribution patterns (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of first redistributions 122, [0045]) include a plurality of second redistribution line patterns (FIGS. 1A-1N, the portions of the second redistributions 122 that are flat) and a plurality of second redistribution via patterns (FIGS. 1A-1N, the portions of the second redistributions 122 that are tapered), and
wherein the plurality of first redistribution via patterns and the plurality of second redistribution via patterns are tapered wherein horizontal widths thereof decrease in directions opposite to each other in a vertical direction (FIGS. 1A-1N, depicting wherein the tapered portions of the first and second redistributions 112/122 are tapered, and wherein the horizontal widths thereof decrease in directions opposite to each other in a vertical direction).
Regarding claim 3, Kim further discloses wherein horizontal widths of the plurality of first redistribution via patterns and the plurality of second redistribution via patterns increase toward the semiconductor chip (FIGS. 1A-1N, depicting wherein the tapered portions of the first and second redistributions 112/122 are tapered, and wherein the horizontal widths thereof increase toward the semiconductor die 130).
Regarding claim 5, Kim does not specifically disclose wherein the encapsulant covers side surfaces and at least a part of a top surface of each of the plurality of first top connection pads and side surfaces and at least a part of a bottom surface of each of the plurality of second bottom connection pads.
However, addition of the bumps 43 of Na to the device of Kim would result in a configuration wherein the encapsulant covers side surfaces and at least a part of a top surface of each of the plurality of first top connection pads and side surfaces and at least a part of a bottom surface of each of the plurality of second bottom connection pads (Kim FIGS. 1A-1N; Na FIG 1A, depicting wherein the encapsulant 150 would cover side surfaces and at least a part of a top surface of the bumps 43 forming the top connection pads, and the encapsulant 150 would cover side surfaces and at least a part of a top surface of the bumps 43 forming the bottom connection pads).
Regarding claim 6, Kim further discloses wherein bottom surfaces of the plurality of first bottom connection pads (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of first redistributions 112, [0031]) and a bottom surface of a lowermost first redistribution insulating layer (FIGS. 1A-1N, first dielectric layer 111 formed as a plurality of layers surrounding the first and second redistributions 112, [0031]) of the first redistribution insulating layers are coplanar (FIGS. 1A-1N, depicting wherein a bottom surface of the lower multilayer wiring structure is coplanar with a bottom surface of one of the plurality of dielectric layers 111 surrounding the first and second redistributions 112).
Regarding claim 7, Kim further discloses a plurality of conductive protective layers that cover the plurality of second top connection pads (FIGS. 1A-1N, disclosing wherein a seed layer may cover the plurality of first or second redistributions 122, [0059]: “Here, a seed layer (gold, silver, nickel, titanium, and/or tungsten) may be directly exposed to the outside through the second dielectric layer 121. Gold and/or silver may be directly exposed to the outside through the second dielectric layer 121 to facilitate a connection with a solder ball or another semiconductor device in a subsequent process.”), wherein a top surface of each of the plurality of conductive protective layers is coplanar with or lower than that of a top surface of an uppermost second redistribution insulating layer (FIGS. 1A-1N, depicting wherein the top surface of the plurality of first or second redistributions 122 is coplanar with a top surface of an uppermost one of the plurality of layers forming the second dielectric layer 121 formed as a plurality of layers surrounding the first lower and second upper redistributions 122).
Regarding claim 10, Kim further discloses wherein at least a part of the plurality of conductive connection layers (FIGS. 1A-1N, solder caps 114a/124a) is at a same vertical level as the semiconductor chip (FIG. 1N, depicting wherein the solder caps 114a/124a are at a same vertical level as the semiconductor die 130).
Regarding independent claim 11, Kim discloses: A semiconductor package (FIG. 1N, semiconductor device 100, [0062]), comprising:
a first wiring structure (FIGS. 1A-1N, depicting a lower multilayer wiring structure, [0026]) that includes a plurality of first redistribution patterns that include a plurality of first bottom connection pads (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of first redistributions 112, [0031]) and a plurality of first top connection pads (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of second redistributions 112, [0031]), and
a plurality of first redistribution insulating layers that surround the plurality of first redistribution patterns (FIGS. 1A-1N, first dielectric layer 111 formed as a plurality of layers surrounding the first and second redistributions 112, [0031]);
a semiconductor chip (FIG. 1N, semiconductor die 130, [0034]) attached onto the first wiring structure (FIG. 1N, depicting wherein the semiconductor die 130 is attached onto the lower multilayer wiring structure);
a second wiring structure (FIGS. 1A-1N, depicting an upper multilayer wiring structure, [0045]) disposed on the first wiring structure and the semiconductor chip (FIG. 1N, depicting wherein the upper multilayer wiring structure is disposed on the lower multilayer wiring structure and the semiconductor die 130),
wherein the second wiring structure (FIGS. 1A-1N, depicting an upper multilayer wiring structure, [0045]) includes a plurality of second redistribution patterns that include a plurality of second bottom connection pads (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of first redistributions 122, [0045]) and a plurality of second top connection pads (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of second redistributions 122, [0045]), and
a plurality of second redistribution insulating layers that surround the plurality of second redistribution patterns (FIGS. 1A-1N, second dielectric layer 121 formed as a plurality of layers surrounding the first lower and second upper redistributions 122);
a plurality of connection structures (FIG. 1N, depicting a plurality of conductive pillars comprising a first conductive pillar 114, a second conductive pillar 124, and a solder cap 114a/124a, [0046], [0072]) that include a plurality of lower connection structures (FIGS. 1A-1N, first conductive pillars 114) attached to the plurality of first top connection pads (FIGS. 1A-1N, depicting wherein the bottom of the first conductive pillar 114 is attached to the top of the lower multilayer wiring structure, including the first or second redistributions 112),
a plurality of upper connection structures (FIGS. 1A-1N, second conductive pillars 124) attached to the plurality of second bottom connection pads (FIGS. 1A-1N, depicting wherein the top of the second conductive pillar 124 is attached to the bottom of the upper multilayer wiring structure including the first or second redistributions 122), and
a plurality of conductive connection layers (FIGS. 1A-1N, solder caps 114a/124a) interposed between the plurality of lower connection structures and the plurality of upper connection structures and that connect the first wiring structure to the second wiring structure (FIGS. 1A-1N, depicting wherein the solder caps 114a/124a are interposed between the first and second conductive pillars 114 and 124, and connect the upper and lower multilayer wiring structures); and
an encapsulant (FIG. 1N, encapsulant 150, [0043]) that fills a space between the first wiring structure and the second wiring structure and surrounds the semiconductor chip and the plurality of connection structures (FIG. 1N, depicting wherein the encapsulant fills a space between the upper and lower multilayer wiring structures and surrounds the semiconductor die 130 and the plurality of conductive pillars comprising a first conductive pillar 114, a second conductive pillar 124, and a solder cap 114a/124a), and
wherein the uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers and the lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers are in direct contact with the encapsulant (FIGS. 1A-1N, depicting wherein an uppermost dielectric layer 111 of the plurality of layers and a lowermost dielectric layer 121 of the plurality of layers are in direct contact with the encapsulant 150).
Kim does not specifically disclose wherein each of the plurality of first top connection pads protrudes from top surfaces of an uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers.
In the same field of endeavor, Na discloses a semiconductor package (FIG. 1A, depicting a circuit board, [0043]) including a connection pad (FIG. 1A, depicting bump 43, [0090]), wherein each of the plurality of connection pads protrudes from surfaces of a redistribution insulating layers (FIG. 1A, depicting wherein the bump 43 protrudes from a surface of a protective layer 30, [0091]). Regarding the bump 43, in [0090], Na states: “In addition, the width w5 of the second part 43-2 of the third bump 43 is greater than the width w3 of the third pad 23 and the width w4 of the first part 43-1. Accordingly, in the first comparative example, the bonding area with the solder is improved by using the second part 43-2 of the third bump 43.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Kim by adding the bumps 43 of Na to form top connection pads protruding from an uppermost surface of the dielectric layer 111 in order to improve the bonding area of the redistributions 112. See Na [0090].
Kim does not specifically disclose wherein each of the plurality of second bottom connection pads protrudes from bottom surfaces of a lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers.
In the same field of endeavor, Na discloses a semiconductor package (FIG. 1A, depicting a circuit board, [0043]) including a connection pad (FIG. 1A, depicting bump 43, [0090]), wherein each of the plurality of connection pads protrudes from surfaces of a redistribution insulating layers (FIG. 1A, depicting wherein the bump 43 protrudes from a surface of a protective layer 30, [0091]). Regarding the bump 43, in [0090], Na states: “In addition, the width w5 of the second part 43-2 of the third bump 43 is greater than the width w3 of the third pad 23 and the width w4 of the first part 43-1. Accordingly, in the first comparative example, the bonding area with the solder is improved by using the second part 43-2 of the third bump 43.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Kim by adding the bumps 43 of Na to form bottom connection pads protruding from a bottommost surface of the dielectric layer 121 in order to improve the bonding area of the redistributions 122. See Na [0090].
Moreover, addition of the bumps 43 of Na to the device of Kim would result in a configuration wherein the encapsulant covers side surfaces and at least a part of a top surface of each of the plurality of first top connection pads and side surfaces and at least a part of a bottom surface of each of the plurality of second bottom connection pads (Kim FIGS. 1A-1N; Na FIG 1A, depicting wherein the encapsulant 150 would cover side surfaces and at least a part of a top surface of the bumps 43 forming the top connection pads, and the encapsulant 150 would cover side surfaces and at least a part of a top surface of the bumps 43 forming the bottom connection pads).
Regarding claim 12, Kim further discloses wherein a height of each of the plurality of lower connection structures is equal to that of each of the plurality of upper connection structures (FIGS. 1A-1N, depicting wherein the height of the first conductive pillars 114 and second conductive pillars 124 are equal).
Regarding claim 18, Kim further discloses wherein
the plurality of first redistribution patterns (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of first redistributions 112, [0031]) include a plurality of first redistribution line patterns (FIGS. 1A-1N, the portions of the first redistributions 112 that are flat) and a plurality of first redistribution via patterns (FIGS. 1A-1N, the portions of the first redistributions 112 that are tapered),
wherein the plurality of second redistribution patterns (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of first redistributions 122, [0045]) include a plurality of second redistribution line patterns (FIGS. 1A-1N, the portions of the second redistributions 122 that are flat) and a plurality of second redistribution via patterns (FIGS. 1A-1N, the portions of the second redistributions 122 that are tapered), and
wherein the plurality of first redistribution via patterns and the plurality of second redistribution via patterns are tapered such that horizontal widths thereof increase toward the semiconductor chip (FIGS. 1A-1N, depicting wherein the tapered portions of the first and second redistributions 112/122 are tapered, and wherein the horizontal widths thereof increase toward the semiconductor die 130).
Regarding independent claim 19, Kim discloses: A semiconductor package (FIG. 1N, semiconductor device 100, [0062]), comprising:
a first wiring structure (FIGS. 1A-1N, depicting a lower multilayer wiring structure, [0026]) that includes a plurality of first redistribution patterns (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of first and second redistributions 112, [0031]) that include a plurality of first redistribution line patterns (FIGS. 1A-1N, the portions of the first or second redistributions 112 that are flat) and a plurality of first redistribution via patterns (FIGS. 1A-1N, the portions of the first or second redistributions 112 that are tapered), and
a plurality of first redistribution insulating layers that surround the plurality of first redistribution patterns (FIGS. 1A-1N, first dielectric layer 111 formed as a plurality of layers surrounding the first and second redistributions 112, [0031]),
wherein the plurality of first redistribution patterns include a plurality of first bottom connection pads (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of first redistributions 112, [0031]) and a plurality of first top connection pads (FIGS. 1A-1N, depicting wherein the lower multilayer wiring structure includes a plurality of second redistributions 112, [0031]);
a second wiring structure (FIGS. 1A-1N, depicting an upper multilayer wiring structure, [0045]) that includes a plurality of second redistribution patterns (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of first and second redistributions 122, [0045]) that include a plurality of second redistribution line patterns (FIGS. 1A-1N, the portions of the first or second redistributions 122 that are flat) and a plurality of second redistribution via patterns (FIGS. 1A-1N, the portions of the first or second redistributions 122 that are tapered), and
a plurality of second redistribution insulating layers that surround the plurality of second redistribution patterns (FIGS. 1A-1N, second dielectric layer 121 formed as a plurality of layers surrounding the first lower and second upper redistributions 122),
wherein the plurality of second redistribution patterns include a plurality of second bottom connection pads (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of first redistributions 122, [0045]) and a plurality of second top connection pads (FIGS. 1A-1N, depicting wherein the upper multilayer wiring structure includes a plurality of second redistributions 122, [0045]);
a semiconductor chip (FIG. 1N, semiconductor die 130, [0034]) interposed between the first wiring structure and the second wiring structure (FIG. 1N, depicting wherein the semiconductor die 130 is interposed between the upper and lower multilayer wiring structures);
a plurality of connection structures (FIG. 1N, depicting a plurality of conductive pillars comprising a first conductive pillar 114, a second conductive pillar 124, and a solder cap 114a/124a, [0046], [0072]) that are spaced apart from the semiconductor chip in a horizontal direction and arranged around the semiconductor chip (FIG. 1N, depicting wherein the plurality of conductive pillars are spaced apart from the semiconductor die 130, and are arranged around the semiconductor die 130),
wherein the plurality of connection structures (FIG. 1N, depicting a plurality of conductive pillars comprising a first conductive pillar 114, a second conductive pillar 124, and a solder cap 114a/124a, [0046], [0072]) include a plurality of lower connection structures (FIGS. 1A-1N, first conductive pillars 114) attached to the plurality of first top connection pads (FIGS. 1A-1N, depicting wherein the bottom of the first conductive pillar 114 is attached to the top of the lower multilayer wiring structure, including the first or second redistributions 112),
a plurality of upper connection structures (FIGS. 1A-1N, second conductive pillars 124) attached to the plurality of second bottom connection pads (FIGS. 1A-1N, depicting wherein the top of the second conductive pillar 124 is attached to the bottom of the upper multilayer wiring structure including the first or second redistributions 122), and
a plurality of conductive connection layers (FIGS. 1A-1N, solder caps 114a/124a) interposed between the plurality of lower connection structures and the plurality of upper connection structures and that electrically connect the plurality of first redistribution patterns to the plurality of second redistribution patterns (FIGS. 1A-1N, depicting wherein the solder caps 114a/124a are interposed between the first and second conductive pillars 114 and 124, and connect the upper and lower multilayer wiring structures, including the first and second redistributions 112/122); and
an encapsulant (FIG. 1N, encapsulant 150, [0043]) that fills a space between the first wiring structure and the second wiring structure and surrounds the semiconductor chip and the plurality of connection structures (FIG. 1N, depicting wherein the encapsulant fills a space between the upper and lower multilayer wiring structures and surrounds the semiconductor die 130 and the plurality of conductive pillars comprising a first conductive pillar 114, a second conductive pillar 124, and a solder cap 114a/124a),
wherein the plurality of first redistribution via patterns and the plurality of second redistribution via patterns are tapered where horizontal widths thereof increase toward the semiconductor chip (FIGS. 1A-1N, depicting wherein the tapered portions of the first and second redistributions 112/122 are tapered, and wherein the horizontal widths thereof increase toward the semiconductor die 130), and
wherein the uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers and the lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers are in direct contact with the encapsulant (FIGS. 1A-1N, depicting wherein an uppermost dielectric layer 111 of the plurality of layers and a lowermost dielectric layer 121 of the plurality of layers are in direct contact with the encapsulant 150).
Kim does not specifically disclose wherein each of the plurality of first top connection pads protrudes from top surfaces of an uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers.
In the same field of endeavor, Na discloses a semiconductor package (FIG. 1A, depicting a circuit board, [0043]) including a connection pad (FIG. 1A, depicting bump 43, [0090]), wherein each of the plurality of connection pads protrudes from surfaces of a redistribution insulating layers (FIG. 1A, depicting wherein the bump 43 protrudes from a surface of a protective layer 30, [0091]). Regarding the bump 43, in [0090], Na states: “In addition, the width w5 of the second part 43-2 of the third bump 43 is greater than the width w3 of the third pad 23 and the width w4 of the first part 43-1. Accordingly, in the first comparative example, the bonding area with the solder is improved by using the second part 43-2 of the third bump 43.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Kim by adding the bumps 43 of Na to form top connection pads protruding from an uppermost surface of the dielectric layer 111 in order to improve the bonding area of the redistributions 112. See Na [0090].
Kim does not specifically disclose wherein each of the plurality of second bottom connection pads protrudes from bottom surfaces of a lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers.
In the same field of endeavor, Na discloses a semiconductor package (FIG. 1A, depicting a circuit board, [0043]) including a connection pad (FIG. 1A, depicting bump 43, [0090]), wherein each of the plurality of connection pads protrudes from surfaces of a redistribution insulating layers (FIG. 1A, depicting wherein the bump 43 protrudes from a surface of a protective layer 30, [0091]). Regarding the bump 43, in [0090], Na states: “In addition, the width w5 of the second part 43-2 of the third bump 43 is greater than the width w3 of the third pad 23 and the width w4 of the first part 43-1. Accordingly, in the first comparative example, the bonding area with the solder is improved by using the second part 43-2 of the third bump 43.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Kim by adding the bumps 43 of Na to form bottom connection pads protruding from a bottommost surface of the dielectric layer 121 in order to improve the bonding area of the redistributions 122. See Na [0090].
Regarding claim 20, Kim further discloses wherein the plurality of lower connection structures (FIGS. 1A-1N, first conductive pillars 114) and the plurality of upper connection structures (FIGS. 1A-1N, second conductive pillars 124) comprise copper (Cu) or a Cu alloy (FIG. 1A-1N, [0034]: “Here, the first conductive pad 113 and the first conductive pillar 114 may include, for example, copper, a copper alloy, aluminum, an aluminum alloy, iron, an iron alloy or equivalents thereof, but aspects of the present disclosure are not limited thereto.”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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