DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4 August 2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election of Species 1 in the reply filed on 27 October 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 8, 9, and 13-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 27 October 2025.
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-7, 10-12, and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2, 5-7 and 10-12 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Publication No. 2020/0105679 (published Apr. 2, 2020) (hereinafter “Bae”) in view of U.S. Patent Publication No. 2015/0221601 (filed Aug. 1, 2014) (hereinafter “Kim”).
Regarding independent claim 1, Bae discloses: A semiconductor package, comprising:
a first wiring structure that includes a plurality of first redistribution patterns that include a plurality of first bottom connection pads (FIG. 16, first redistribution layers 142, [0066]) and a plurality of first top connection pads (FIG. 16, wiring layers 112a, [0067]), and a plurality of first redistribution insulating layers that surround the plurality of first redistribution patterns (FIG. 16, insulating layers 141 surrounding the first redistribution layers 142 and the wiring layers 112a);
a second wiring structure that includes a plurality of second redistribution patterns that include a plurality of second bottom connection pads (FIG. 16, lower redistribution layer 152a, [0127]) and a plurality of second top connection pads (FIG. 16, upper redistribution layer 152b, [0127]), and a plurality of second redistribution insulating layers that surround the plurality of second redistribution patterns (FIG. 16, insulating layer 151 and passivation layer 190, [0127], [0070]);
a semiconductor chip interposed between the first wiring structure and the second wiring structure (FIG. 16, semiconductor chip 120, [0065]);
an encapsulant that fills a space between the first wiring structure and the second wiring structure and that surrounds the semiconductor chip (FIG. 16, depicting wherein a portion of the encapsulant layer including encapsulant 130 fills a space between the wiring structures and surrounds the semiconductor chip 120, [0065]); and
a plurality of connection structures that penetrate through the encapsulant and connect the plurality of first top connection pads to the plurality of second bottom connection pads and are arranged around the semiconductor chip (FIG. 16, depicting connection structures including wiring vias 113a and 113b that penetrate through the encapsulant layer including encapsulant 130, and connect the wiring layers 112a and the lower redistribution layer 152a, and are arranged around the semiconductor chip 120, [0067]),
wherein the plurality of connection structures include a plurality of lower connection structures of which bottom surfaces contact top surfaces of the plurality of first top connection pads (FIG. 16, wiring vias 113a of which bottom surfaces contact top surfaces of the wiring layers 112a),
a plurality of upper connection structures of which top surfaces contact bottom surfaces of the plurality of second bottom connection pads (FIG. 16, wiring vias 113b of which top surfaces contact bottom surfaces of the lower redistribution layers 152a), and
wherein each of the plurality of first top connection pads protrudes from top surfaces of an uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers (FIG. 16, depicting wherein the wiring layers 112a protrude from top surfaces of the uppermost of the insulating layers 141),
wherein each of the plurality of second bottom connection pads protrudes from bottom surfaces of a lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers (FIG. 16, depicting wherein the lower redistribution layers 152a protrude from bottom surfaces of the lowermost insulating layer 151),
wherein the uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers (FIG. 16, depicting wherein uppermost insulating layer 141 is in contact with the encapsulant layer, e.g., directly contacting the encapsulant 130) and the lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers are in direct contact with the encapsulant (FIG. 16, depicting wherein the lowermost insulating layer 151 is in contact with the encapsulant layer, e.g., directly contacting the insulating layer 132 which may be formed from the same material as the encapsulant 130, [0095]), and
wherein side surfaces and at least a part of a top surface of each of protruded portions of the plurality of first top connection pads (FIG. 16, depicting wherein side surfaces and at least a part of a top surface of the wiring vias 113a are in contact with the encapsulant layer including, e.g., insulating layer 111a, which may be formed from the same material as the encapsulant 130, [0088], [0095]) and side surfaces and at least a part of a bottom surface of each of protruded portions of the plurality of second bottom connection pads are in contact with the encapsulant (FIG. 16, depicting wherein side surfaces and at least a part of a bottom surface of the lower redistribution layers 152a are in contact with the encapsulant layer including, e.g., insulating layer 132 which may be formed from the same material as the encapsulant 130).
Bae does not specifically disclose wherein a plurality of conductive connection layers that contact top surfaces of the plurality of lower connection structures and bottom surfaces of the plurality of upper connection structures.
In the same field of endeavor, Kim discloses a semiconductor package (FIG. 1N, semiconductor device 100, [0062]) comprising a plurality of connection structures including a plurality of lower connection structures (FIGS. 1A-1N, first conductive pillars 114), a plurality of upper connection structures (FIGS. 1A-1N, second conductive pillars 124), and a plurality of conductive connection layers (FIGS. 1A-1N, solder caps 114a/124a) that contact top surfaces of the plurality of lower connection structures and bottom surfaces of the plurality of upper connection structures (FIGS. 1A-1N, depicting wherein the solder caps 114a/124a contact the top of the first conductive pillars 114 and the bottom of the second conductive pillars 124). Regarding the solder caps, in [0036], Kim states: “In addition, another solder cap 114 a may be additionally formed at a top end of the first conductive pillar 114 to allow the second redistribution layer 120 to be easily connected.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Bae by adding the solder cap 114 of Kim to facilitate easier connection between the wiring vias 113a/113b. See Kim [0036].
Regarding claim 2, Bae in view of Kim further discloses wherein the plurality of first redistribution patterns include a plurality of first redistribution line patterns (FIG. 16, depicting wherein the first redistribution layers 142 and the wiring layers 112a include line patterns) and a plurality of first redistribution via patterns (FIG. 16, depicting wherein the first redistribution layers 142 and the wiring layers 112a include via patterns), wherein the plurality of second redistribution patterns include a plurality of second redistribution line patterns (FIG. 16, depicting wherein the lower redistribution layers 152a and the upper redistribution layers 152b include line patterns) and a plurality of second redistribution via patterns (FIG. 16, depicting wherein the lower redistribution layers 152a and the upper redistribution layers 152b include via patterns), and wherein the plurality of first redistribution via patterns and the plurality of second redistribution via patterns are tapered wherein horizontal widths thereof decrease in directions opposite to each other in a vertical direction (FIG. 16, depicting wherein the via patterns of the first redistribution layers 142 and the wiring layers 112a and via patterns of the lower redistribution layers 152a and the upper redistribution layers 152b are tapered such that horizontal widths thereof decrease in direction opposite to each other in a vertical direction, one in an upward direction, and one in a downward direction).
Regarding claim 5, Bae in view of Kim further discloses wherein the encapsulant covers side surfaces and at least a part of a top surface of each of the plurality of first top connection pads (FIG. 16, depicting wherein side surfaces and at least a part of a top surface of the wiring vias 113a are covered by the encapsulant layer including, e.g., insulating layer 111a, which may be formed from the same material as the encapsulant 130, [0088], [0095]) and side surfaces and at least a part of a bottom surface of each of the plurality of second bottom connection pads (FIG. 16, depicting wherein side surfaces and at least a part of a bottom surface of the lower redistribution layers 152a are covered by the encapsulant layer including, e.g., insulating layer 132 which may be formed from the same material as the encapsulant 130).
Regarding claim 6, Bae does not specifically disclose wherein bottom surfaces of the plurality of first bottom connection pads and a bottom surface of a lowermost first redistribution insulating layer of the first redistribution insulating layers are coplanar.
In the same field of endeavor, Kim discloses wherein bottom surfaces of the plurality of first bottom connection pads and a bottom surface of a lowermost first redistribution insulating layer of the first redistribution insulating layers are coplanar (FIGS. 1C-1D, depicting wherein first redistributions 112 are formed such that the bottom surfaces of the first redistributions are coplanar with the bottom surface of the lowermost dielectric layer 111, [0031]). Regarding the configuration of the first redistributions 112, in [0029], Kim states: “As illustrated in FIG. 1C, first redistributions 112 may be formed in the first openings 111 a and the first dielectric layer 111. Accordingly, the first redistributions 112 may make direct contact with the first dummy substrate 110A through the first openings 111 a.” Kim further states in [0004]-[0006]: “However, in the conventional POP, since a relatively thick printed circuit board (PCB) is typically used as a substrate and a solder ball having a relatively large diameter is used as an internal conductor, the overall thickness of the POP is approximately 1 mm or greater. . . . The PCB includes a variety of organic materials, and the coefficient of the thermal expansion of the organic material may be significantly different from that of an inorganic material, such as the semiconductor die or an encapsulant, and as such a considerably severe warping phenomenon may occur to the completed POP. Additionally, in order to fabricate a POP, the costly PCB must be purchased, increasing the manufacturing cost of the POP.” Kim further states in [0031]: “As illustrated in FIG. 1D, the process of forming the first dielectric layer 111 and the process of forming the first redistributions 112 may be repeated multiple times, thereby completing the first redistribution layer 110 having a multi-layered structure. For example, the first redistribution layer 110 includes a dielectric layer and redistributions. However, unlike in a conventional printed circuit board (PCB) (e.g., a rigid PCB or a flexible PCB), an organic core layer or an organic build-up layer might not be utilized in the first redistribution layer 110. Therefore, the first redistribution layer 110 may be relatively thin. For example, the first redistribution layer 110 may be formed to a thickness of 10 μm or less. By contrast, a conventional PCB may generally be formed to a thickness in the range of 200 μm to 300 μm.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Bae by adding the solder cap 114 of Kim to facilitate easier connection between the wiring vias 113a/113b. See Kim [0036].
Regarding claim 7, Bae in view of Kim further discloses a plurality of conductive protective layers that cover the plurality of second top connection pads (FIG. 16, surface treatment layer 152P covering the upper redistribution layer 152b, [0070]), wherein a top surface of each of the plurality of conductive protective layers is coplanar with or lower than that of a top surface of an uppermost second redistribution insulating layer (FIG. 16, depicting wherein a top surface of the surface treatment layer 152P is lower than a top surface of the passivation layer 190).
Regarding claim 10, Bae in view of Kim further discloses wherein at least a part of the plurality of conductive connection layers is at a same vertical level as the semiconductor chip (Bae FIG. 16; Kim FIG. 1N; depicting wherein the solder caps 114a/124a are at a same vertical level as the semiconductor die 130, such that the solder caps 114a/124a would be at a same vertical level as the semiconductor chip 120).
Regarding independent claim 11, Bae discloses: A semiconductor package, comprising:
a first wiring structure that includes a plurality of first redistribution patterns that include a plurality of first bottom connection pads (FIG. 16, first redistribution layers 142, [0066]) and a plurality of first top connection pads (FIG. 16, wiring layers 112a, [0067]), and a plurality of first redistribution insulating layers that surround the plurality of first redistribution patterns (FIG. 16, insulating layers 141 surrounding the first redistribution layers 142 and the wiring layers 112a);
a semiconductor chip attached onto the first wiring structure (FIG. 16, semiconductor chip 120 attached to the wiring structure including first redistribution layers 142 and wiring layers 112a, [0065]);
a second wiring structure disposed on the first wiring structure and the semiconductor chip (FIG. 16, depicting wherein the lower redistribution layer 152a, upper redistribution layer 152b, and insulating layer 151 and passivation layer 190 are disposed on the wiring structure including first redistribution layers 142 and wiring layers 112a and the semiconductor chip 120), wherein the second wiring structure includes a plurality of second redistribution patterns that include a plurality of second bottom connection pads (FIG. 16, lower redistribution layer 152a, [0127]) and a plurality of second top connection pads (FIG. 16, upper redistribution layer 152b, [0127]), and a plurality of second redistribution insulating layers that surround the plurality of second redistribution patterns (FIG. 16, insulating layer 151 and passivation layer 190, [0127], [0070]);
a plurality of connection structures that include a plurality of lower connection structures attached to the plurality of first top connection pads (FIG. 16, wiring vias 113a attached to the wiring layers 112a, [0067]),
a plurality of upper connection structures attached to the plurality of second bottom connection pads (FIG. 16, wiring vias 113b attached to the lower redistribution layers 152a, [0067]), and
an encapsulant that fills a space between the first wiring structure and the second wiring structure and surrounds the semiconductor chip and the plurality of connection structures (FIG. 16, depicting wherein a portion of the encapsulant layer including encapsulant 130 fills a space between the wiring structures and surrounds the semiconductor chip 120 and the wiring vias 113a and the wiring vias 113b, [0065]),
wherein each of the plurality of first top connection pads protrudes from top surfaces of an uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers (FIG. 16, depicting wherein the wiring layers 112a protrude from top surfaces of the uppermost of the insulating layers 141) and each of the plurality of second bottom connection pads protrudes from bottom surfaces of a lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers (FIG. 16, depicting wherein the lower redistribution layers 152a protrude from bottom surfaces of the lowermost insulating layer 151),
wherein the uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers (FIG. 16, depicting wherein uppermost insulating layer 141 is in contact with the encapsulant layer, e.g., directly contacting the encapsulant 130) and the lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers are in direct contact with the encapsulant (FIG. 16, depicting wherein the lowermost insulating layer 151 is in contact with the encapsulant layer, e.g., directly contacting the insulating layer 132 which may be formed from the same material as the encapsulant 130, [0095]), and
wherein the encapsulant covers side surfaces and at least a part of a top surface of each of protruded portions of the plurality of first top connection pads (FIG. 16, depicting wherein side surfaces and at least a part of a top surface of the wiring vias 113a are covered by the encapsulant layer including, e.g., insulating layer 111a, which may be formed from the same material as the encapsulant 130, [0088], [0095]) and side surfaces and at least a part of a bottom surface of each of protruded portions of the plurality of second bottom connection pads (FIG. 16, depicting wherein side surfaces and at least a part of a bottom surface of the lower redistribution layers 152a are covered by the encapsulant layer including, e.g., insulating layer 132 which may be formed from the same material as the encapsulant 130).
Bae does not specifically disclose wherein a plurality of conductive connection layers interposed between the plurality of lower connection structures and the plurality of upper connection structures and that connect the first wiring structure to the second wiring structure.
In the same field of endeavor, Kim discloses a semiconductor package (FIG. 1N, semiconductor device 100, [0062]) comprising a plurality of conductive connection layers (FIGS. 1A-1N, solder caps 114a/124a) interposed between a plurality of lower connection structures and a plurality of upper connection structures and that connect the first wiring structure to the second wiring structure (FIGS. 1A-1N, depicting wherein the solder caps 114a/124a are interposed between the first and second conductive pillars 114 and 124, and connect the upper and lower multilayer wiring structures). Regarding the solder caps, in [0036], Kim states: “In addition, another solder cap 114 a may be additionally formed at a top end of the first conductive pillar 114 to allow the second redistribution layer 120 to be easily connected.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Bae by adding the solder cap 114 of Kim to facilitate easier connection between the wiring vias 113a/113b. See Kim [0036].
Regarding claim 12, Bae in view of Kim further discloses wherein a height of each of the plurality of lower connection structures is equal to that of each of the plurality of upper connection structures (FIG. 16, depicting wherein the wiring vias 113a/113b are equal in height).
Claims 3 and 18-20 are rejected under 35 U.S.C. § 103 as being unpatentable over Bae in view of Kim, and further in view of U.S. Patent Publication No. 2023/0361014 (filed May 6, 2022) (hereinafter “Ho”).
Regarding claim 3, Bae in view of Kim does not specifically disclose wherein horizontal widths of the plurality of first redistribution via patterns and the plurality of second redistribution via patterns increase toward the semiconductor chip.
In the same field of endeavor, Ho discloses a semiconductor package (FIGS. 5B/6, electronic package 3d’/3e, [0075]-[0076]) including a plurality of first redistribution via patterns (FIGS. 5B/6, depicting circuit layers 151/152, [0045]), a plurality of second redistribution via patterns (FIGS. 5B/6, depicting circuit layers 24/25, [0052]), and a semiconductor chip (FIGS. 5B/6, electronic device 34, [0045]), wherein horizontal widths of the plurality of first redistribution via patterns and the plurality of second redistribution via patterns increase toward the semiconductor chip (FIG. 6, depicting wherein the circuit layers 24/25/151/152 each increase in width toward the semiconductor chip). In [0076], Ho states: “The electronic package 3e of FIG. 6 is similar to the electronic package 3 d of FIG. 5 , except that the first circuit pattern structure 1 is upside down to become the first circuit pattern structure 1 b of FIG. 6 .”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor of Bae by substituting the redistribution via pattern configuration of Ho, such that the horizontal widths of the first redistribution layers 142 and wiring layers 112a and lower redistribution layer 152a and upper redistribution layer 152b increase toward the semiconductor chip 120, as such simple substitution of one known configuration for the other could have been accomplished by one of ordinary skill in the art, and the results of such substitution would have been predictable, providing the semiconductor package of Bae with an alternate redistribution via pattern configuration. See Ho [0076].
Regarding claim 18, Bae in view of Kim further discloses wherein the plurality of first redistribution patterns include a plurality of first redistribution line patterns (FIG. 16, depicting wherein the first redistribution layers 142 and the wiring layers 112a include line patterns) and a plurality of first redistribution via patterns (FIG. 16, depicting wherein the first redistribution layers 142 and the wiring layers 112a include via patterns), wherein the plurality of second redistribution patterns include a plurality of second redistribution line patterns (FIG. 16, depicting wherein the lower redistribution layers 152a and the upper redistribution layers 152b include line patterns) and a plurality of second redistribution via patterns (FIG. 16, depicting wherein the lower redistribution layers 152a and the upper redistribution layers 152b include via patterns).
Bae in view of Kim does not specifically disclose wherein the plurality of first redistribution via patterns and the plurality of second redistribution via patterns are tapered such that horizontal widths thereof increase toward the semiconductor chip.
In the same field of endeavor, Ho discloses a semiconductor package (FIGS. 5B/6, electronic package 3d’/3e, [0075]-[0076]) including a plurality of first redistribution via patterns (FIGS. 5B/6, depicting circuit layers 151/152, [0045]), a plurality of second redistribution via patterns (FIGS. 5B/6, depicting circuit layers 24/25, [0052]), and a semiconductor chip (FIGS. 5B/6, electronic device 34, [0045]), wherein horizontal widths of the plurality of first redistribution via patterns and the plurality of second redistribution via patterns increase toward the semiconductor chip (FIG. 6, depicting wherein the circuit layers 24/25/151/152 each increase in width toward the semiconductor chip). In [0076], Ho states: “The electronic package 3e of FIG. 6 is similar to the electronic package 3 d of FIG. 5 , except that the first circuit pattern structure 1 is upside down to become the first circuit pattern structure 1 b of FIG. 6 .”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor of Bae by substituting the redistribution via pattern configuration of Ho, such that the horizontal widths of the first redistribution layers 142 and wiring layers 112a and lower redistribution layer 152a and upper redistribution layer 152b increase toward the semiconductor chip 120, as such simple substitution of one known configuration for the other could have been accomplished by one of ordinary skill in the art, and the results of such substitution would have been predictable, providing the semiconductor package of Bae with an alternate redistribution via pattern configuration. See Ho [0076].
Regarding independent claim 19, Bae discloses: A semiconductor package, comprising:
a first wiring structure that includes a plurality of first redistribution line patterns (FIG. 16, depicting wherein the first redistribution layers 142 and the wiring layers 112a include line patterns) and a plurality of first redistribution via patterns (FIG. 16, depicting wherein the first redistribution layers 142 and the wiring layers 112a include via patterns), and a plurality of first redistribution insulating layers that surround the plurality of first redistribution patterns (FIG. 16, insulating layers 141 surrounding the first redistribution layers 142 and the wiring layers 112a), wherein the plurality of first redistribution patterns include a plurality of first bottom connection pads (FIG. 16, first redistribution layers 142, [0066]) and a plurality of first top connection pads (FIG. 16, wiring layers 112a, [0067]);
a second wiring structure that includes a plurality of second redistribution line patterns (FIG. 16, depicting wherein the lower redistribution layers 152a and the upper redistribution layers 152b include line patterns) and a plurality of second redistribution via patterns (FIG. 16, depicting wherein the lower redistribution layers 152a and the upper redistribution layers 152b include via patterns), and a plurality of second redistribution insulating layers that surround the plurality of second redistribution patterns (FIG. 16, insulating layer 151 and passivation layer 190, [0127], [0070]), wherein the plurality of second redistribution patterns include a plurality of second bottom connection pads (FIG. 16, lower redistribution layer 152a, [0127]) and a plurality of second top connection pads (FIG. 16, upper redistribution layer 152b, [0127]);
a semiconductor chip interposed between the first wiring structure and the second wiring structure (FIG. 16, semiconductor chip 120, [0065]);
a plurality of connection structures that are spaced apart from the semiconductor chip in a horizontal direction and arranged around the semiconductor chip (FIG. 16, depicting connection structures including wiring vias 113a and 113b that are spaced apart from the semiconductor chip 120 in a horizontal direction and are arranged around the semiconductor chip 120), wherein the plurality of connection structures include
a plurality of lower connection structures attached to the plurality of first top connection pads (FIG. 16, wiring vias 113a attached to the wiring layers 112a, [0067]),
a plurality of upper connection structures attached to the plurality of second bottom connection pads (FIG. 16, wiring vias 113b attached to the lower redistribution layers 152a, [0067]); and
an encapsulant that fills a space between the first wiring structure and the second wiring structure and surrounds the semiconductor chip and the plurality of connection structures (FIG. 16, depicting wherein a portion of the encapsulant layer including encapsulant 130 fills a space between the wiring structures and surrounds the semiconductor chip 120 and the wiring vias 113a and the wiring vias 113b, [0065]),
wherein each of the plurality of first top connection pads protrudes from top surfaces of an uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers (FIG. 16, depicting wherein the wiring layers 112a protrude from top surfaces of the uppermost of the insulating layers 141),
wherein each of the plurality of second bottom connection pads protrudes from bottom surfaces of a lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers (FIG. 16, depicting wherein the lower redistribution layers 152a protrude from bottom surfaces of the lowermost insulating layer 151),
wherein the uppermost first redistribution insulating layer of the plurality of first redistribution insulating layers (FIG. 16, depicting wherein uppermost insulating layer 141 is in contact with the encapsulant layer, e.g., directly contacting the encapsulant 130) and the lowermost second redistribution insulating layer of the plurality of second redistribution insulating layers are in direct contact with the encapsulant (FIG. 16, depicting wherein the lowermost insulating layer 151 is in contact with the encapsulant layer, e.g., directly contacting the insulating layer 132 which may be formed from the same material as the encapsulant 130, [0095]) and
wherein side surfaces and at least a part of a top surface of each of protruded portions of the plurality of first top connection pads (FIG. 16, depicting wherein side surfaces and at least a part of a top surface of the wiring vias 113a are in contact with the encapsulant layer including, e.g., insulating layer 111a, which may be formed from the same material as the encapsulant 130, [0088], [0095]) and side surfaces and at least a part of a bottom surface of each of protruded portions of the plurality of second bottom connection pads are in contact with the encapsulant (FIG. 16, depicting wherein side surfaces and at least a part of a bottom surface of the lower redistribution layers 152a are in contact with the encapsulant layer including, e.g., insulating layer 132 which may be formed from the same material as the encapsulant 130).
Bae does not specifically disclose a plurality of conductive connection layers interposed between the plurality of lower connection structures and the plurality of upper connection structures, and that electrically connect the plurality of first redistribution patterns to the plurality of second redistribution patterns.
In the same field of endeavor, Kim discloses a semiconductor package (FIG. 1N, semiconductor device 100, [0062]) comprising a plurality of conductive connection layers (FIGS. 1A-1N, solder caps 114a/124a) interposed between a plurality of lower connection structures and a plurality of upper connection structures and that electrically connect the first redistribution patterns to the second redistribution patterns (FIGS. 1A-1N, depicting wherein the solder caps 114a/124a are interposed between the first and second conductive pillars 114 and 124, and electrically connect the upper and lower multilayer wiring structures). Regarding the solder caps, in [0036], Kim states: “In addition, another solder cap 114 a may be additionally formed at a top end of the first conductive pillar 114 to allow the second redistribution layer 120 to be easily connected.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed device of Bae by adding the solder cap 114 of Kim to facilitate easier connection between the wiring vias 113a/113b. See Kim [0036].
Bae in view of Kim does not specifically disclose wherein the plurality of first redistribution via patterns and the plurality of second redistribution via patterns are tapered where horizontal widths thereof increase toward the semiconductor chip.
In the same field of endeavor, Ho discloses a semiconductor package (FIGS. 5B/6, electronic package 3d’/3e, [0075]-[0076]) including a plurality of first redistribution via patterns (FIGS. 5B/6, depicting circuit layers 151/152, [0045]), a plurality of second redistribution via patterns (FIGS. 5B/6, depicting circuit layers 24/25, [0052]), and a semiconductor chip (FIGS. 5B/6, electronic device 34, [0045]), wherein horizontal widths of the plurality of first redistribution via patterns and the plurality of second redistribution via patterns increase toward the semiconductor chip (FIG. 6, depicting wherein the circuit layers 24/25/151/152 each increase in width toward the semiconductor chip). In [0076], Ho states: “The electronic package 3e of FIG. 6 is similar to the electronic package 3 d of FIG. 5 , except that the first circuit pattern structure 1 is upside down to become the first circuit pattern structure 1 b of FIG. 6 .”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor of Bae by substituting the redistribution via pattern configuration of Ho, such that the horizontal widths of the first redistribution layers 142 and wiring layers 112a and lower redistribution layer 152a and upper redistribution layer 152b increase toward the semiconductor chip 120, as such simple substitution of one known configuration for the other could have been accomplished by one of ordinary skill in the art, and the results of such substitution would have been predictable, providing the semiconductor package of Bae with an alternate redistribution via pattern configuration. See Ho [0076].
Regarding claim 20, Bae in view of Kim and Ho further discloses wherein the plurality of lower connection structures and the plurality of upper connection structures comprise copper (Cu) or a Cu alloy (FIG. 16, [0089]: “A material of each of the wiring layers 112 a, 112 b, and 112 c may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.”).
Conclusion
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/ADAM D WEILAND/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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