DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment filed on 06/24/2026. The applicant elects the Species 1: Figure 3 (without traverse).
Claim Objections
Claims 22, 24 and 26 are objected to because of the following informalities: Claims 22, 24 and 26, line 5 recites “Vlamp1”, which appears a typographical error of -- Vclamp1--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 17-21, 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0092623), hereinafter Huang, in view of Lai et al. (US 2023/0015792), hereinafter Lai.
Regarding claim 1, Huang discloses (see figures 1-13) a voltage conversion circuit (figure 11, part 300), comprising: an input switch (figure 11, part Q1H), a switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H), a first clamp circuit (figure 11, part first clamp circuit generated by 260 and current source Is), a first capacitor (figure 11, part CFLY) and a second element (figure 11, part BAT); wherein a first terminal of the input switch (figure 11, part Q1H; upper terminal) is electrically connected to a voltage input terminal (figure 11, part VMID terminal), a second terminal of the input switch (figure 11, part Q1H; lower terminal) is electrically connected to a first plate of the first capacitor (figure 11, part CFLY; upper plate CP), the first plate and a second plate of the first capacitor (figure 11, part CFLY; upper/lower plates CP/CN) are electrically connected to a voltage output terminal of the voltage conversion circuit (figure 11, part VBAT terminal) via the switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H), the first plate and the second plate of the first capacitor (figure 11, part CFLY; upper/lower plates CP/CN) are further grounded (figure 11, part grounded) via the switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H), the voltage output terminal (figure 11, part VBAT terminal) is grounded via the second element (figure 11, part BAT), and the first clamp circuit (figure 11, part first clamp circuit generated by 260 and current source Is) is electrically connected across the first terminal and the second terminal of the input switch (figure 11, part Q1H; upper and lower terminals); the input switch (figure 11, part Q1H) is configured to, in cooperation with the switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H), control an electrical connection between the first capacitor (figure 11, part CFLY) and the second element (figure 11, part BAT), such that an output voltage of the voltage conversion circuit (figure 11, part VBAT) is less than an input voltage of the voltage conversion circuit (figure 11, part VMID) (paragraph [0069]; the voltage of the first power VMID is greater than the voltage of the second power VBAT); and the first clamp circuit (figure 11, part first clamp circuit generated by 260 and current source Is) is configured to, in response to the input voltage being (figure 11, part VMID) greater than a first clamp voltage of the first clamp circuit (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is), limit a voltage across the first terminal and the second terminal of the input switch (figure 11, part Q1H; upper and lower terminals) to the first clamp voltage (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is) (paragraphs [0095]-[0096]; the clamper 260 is configured to clamp a voltage difference between the first inverting output end of the first switch Q1H and the first control end of the first switch Q1H in the first switch unit 310 to be below a clamping limit, so that a voltage difference between the first inverting output end of the first switch Q1H and the first non-inverting output end of the first switch Q1H does not exceed an absolute maximum rating of the first switch Q1H, and the clamping limit is less than the absolute maximum rating of the first switch Q1H. In other words, since the clamper 260 limits the voltage of the first switch Q1H during operation, the size of the first switch Q1H in the first switch unit 310 can be reduced, thereby reducing the conduction resistance of the first switch Q1H. Therefore, the clamping circuit technology can effectively reduce the overall loss of the switched capacitor converter 300); wherein the switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H) comprises: a ninth switch (figure 11, part Q2H), a tenth switch (figure 11, part Q3H), and an eleventh switch (figure 11, part Q4H), wherein, a first terminal of the ninth switch (figure 11, part Q2H; upper terminal) is electrically connected to the second terminal of the input switch (figure 11, part Q1H; lower terminal) and the first plate of the first capacitor (figure 11, part CFLY; upper plate CP), a second terminal of the ninth switch (figure 11, part Q2H; lower terminal) is electrically connected to the voltage output terminal (figure 11, part VBAT terminal) and a first terminal of the tenth switch (figure 11, part Q3H; upper terminal), a second terminal of the tenth switch (figure 11, part Q3H; lower terminal) is electrically connected to a first terminal of the eleventh switch (figure 11, part Q4H; upper terminal)and the second plate of the first capacitor (figure 11, part CFLY; lower plate CN), and a second terminal of the eleventh switch is grounded (figure 11, part Q4H; lower terminal is grounded); when the voltage conversion circuit (figure 11, part 300) normally operates (figure 7), the input switch (figures 7 and 11, part Q1H; turned on between t1-t4) and the tenth switch are both turned on (figures 7 and 11, part Q3H; turned on between t1-t4), and the ninth switch (figures 7 and 11, part Q2H; turned off between t1-t4) and the eleventh switch are both turned off (figures 7 and 11, part Q4H; turned off between t1-t4), so that the first capacitor (figures 7 and 11, part CFLY; between t1-t4) and the second element are connected in series (figures 7 and 11, part BAT; between t1-t4), the first capacitor (figures 7 and 11, part CFLY; between t1-t4) and the second element are in a charging state (figures 7 and 11, part BAT; between t1-t4), and energy provided by the input voltage (figure 11, part VMID) is stored in the first capacitor (figures 7 and 11, part CFLY; between t1-t4) and the second element (figures 7 and 11, part BAT; between t1-t4) (paragraph [0074]; When the first switch unit 310 and the third switch unit 330 are turned on, and the second switch unit 320 and the fourth switch unit 340 are turned off (as shown from time point t1 to time point t4) , the capacitor CFLY forms a series circuit with the battery BAT, wherein the capacitor CFLY and the battery BAT are connected in series between the first power VMID and the ground potential. At this state, the first power VMID charges both the capacitor CFLY and the battery BAT (step S40, hereinafter referred to as the first state)); and upon completion of charging (figures 7 and 11, part upon completion of charging between t1-t4), a voltage across the first plate and the second plate of the first capacitor (figure 11, part CFLY; voltage across the upper and lower plate CP/CN) and a voltage across two plates of the second element (figures 7 and 11, part BAT; voltage across the upper and lower terminal of BAT) are both half of the input voltage (figure 11, part half of VMID; based on previous series charging process), afterwards, the ninth switch (figures 7 and 11, part Q2H; turned on between t4-t5) and the eleventh switch are both turned on (figures 7 and 11, part Q4H; turned on between t4-t5), and the input switch (figures 7 and 11, part Q1H; turned off between t4-t5) and the tenth switch are both turned off (figures 7 and 11, part Q3H; turned off between t4-t5), so that the first capacitor (figures 7 and 11, part CFLY; between t4-t5) and the second element are connected in parallel (figures 7 and 11, part BAT; between t4-t5), the first capacitor (figures 7 and 11, part CFLY; between t4-t5) and the second element are in a discharging state parallel (figures 7 and 11, part BAT; between t4-t5), the energy stored in the first capacitor (figures 7 and 11, part CFLY; between t4-t5) and the second element is released (figures 7 and 11, part BAT; between t4-t5), and the output voltage (figure 11, part VBAT) is the voltage across the two plates of the second element (figures 7 and 11, part BAT; between t4-t5) and is equal to half of the input voltage (figure 11, part half of VMID; based on previous series charging process) (paragraph [0075]; Following step S40… the switch driving circuit 350 controls the first switch Q2H of the second switch unit 320 and the first switch Q4H of the fourth switch unit 340 to be turned on through control signals G2H and G4H, respectively, and controls the first switch Q1H of the first switch unit 310 and the first switch Q3H of the third switch unit 330 to be turned off through the control signals G1H and G3H, respectively (step S60, time point t4). When the second switch unit 320 and the fourth switch unit 340 are turned on, and the first switch unit 310 and the third switch unit 330 are turned off (as shown from time point t5 to time point t8) , the capacitor CFLY forms a parallel circuit with the battery BAT, and at this state, the capacitor CFLY discharges to charge the battery BAT (step S70, hereinafter referred to as the second state)).
Huang does not expressly disclose a second capacitor.
Lai teaches (see figures 1-7) a voltage conversion circuit (figure 1), comprising: an input switch (figure 1, part SW4), a switch assembly (figure 1, part switch assembly generated by SW1-SW3), a first capacitor (figure 1, part Cfly), and a second capacitor (figure 1, part Cout); wherein a first terminal of the input switch (figure 1, part SW4; upper terminal) is electrically connected to a voltage input terminal (figure 1, part VIN terminal), a second terminal of the input switch (figure 1, part SW4; lower terminal) is electrically connected to a first plate of the first capacitor (figure 1, part Cfly; upper first plate), the first plate and the second plate of the first capacitor (figure 1, part Cfly; upper/lower plates) are electrically connected to a voltage output terminal of the voltage conversion circuit (figure 1, part VOUT terminal) via the switch assembly (figure 1, part switch assembly generated by SW1-SW3), the first plate and the second plate of the first capacitor (figure 1, part Cfly; upper/lower plates) are further grounded (figure 1, part GND) via the switch assembly (figure 1, part switch assembly generated by SW1-SW3), the voltage output terminal (figure 1, part VOUT terminal) is grounded (figure 1, part grounded) via the second capacitor (figure 1, part Cout), and the input switch (figure 1, part SW4) is configured to, in cooperation with the switch assembly (figure 1, part switch assembly generated by SW1-SW3), control an electrical connection between the first capacitor (figure 1, part Cfly) and the second capacitor (figure 1, part Cout).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the voltage conversion circuit (more specific the second element) of Huang with the second capacitor features as taught by Lai and obtain a voltage conversion circuit, comprising: an input switch, a switch assembly, a first clamp circuit, a first capacitor, and a second capacitor; wherein a first terminal of the input switch is electrically connected to a voltage input terminal, a second terminal of the input switch is electrically connected to a first plate of the first capacitor, the first plate and a second plate of the first capacitor are electrically connected to a voltage output terminal of the voltage conversion circuit via the switch assembly, the first plate and the second plate of the first capacitor are further grounded via the switch assembly, the voltage output terminal is grounded via the second capacitor, and the first clamp circuit is electrically connected across the first terminal and the second terminal of the input switch; the input switch is configured to, in cooperation with the switch assembly, control an electrical connection between the first capacitor and the second capacitor, such that an output voltage of the voltage conversion circuit is less than an input voltage of the voltage conversion circuit; and the first clamp circuit is configured to, in response to the input voltage being greater than a first clamp voltage of the first clamp circuit, limit a voltage across the first terminal and the second terminal of the input switch to the first clamp voltage; wherein the switch assembly comprises: a ninth switch, a tenth switch, and an eleventh switch, wherein, a first terminal of the ninth switch is electrically connected to the second terminal of the input switch and the first plate of the first capacitor, a second terminal of the ninth switch is electrically connected to the voltage output terminal and a first terminal of the tenth switch, a second terminal of the tenth switch is electrically connected to a first terminal of the eleventh switch and the second plate of the first capacitor, and a second terminal of the eleventh switch is grounded; when the voltage conversion circuit normally operates, the input switch and the tenth switch are both turned on, and the ninth switch and the eleventh switch are both turned off, so that the first capacitor and the second capacitor are connected in series, the first capacitor and the second capacitor are in a charging state, and energy provided by the input voltage is stored in the first capacitor and the second capacitor; and upon completion of charging, a voltage across the first plate and the second plate of the first capacitor and a voltage across two plates of the second capacitor are both half of the input voltage, afterwards, the ninth switch and the eleventh switch are both turned on, and the input switch and the tenth switch are both turned off, so that the first capacitor and the second capacitor are connected in parallel, the first capacitor and the second capacitor are in a discharging state, the energy stored in the first capacitor and the second capacitor is released, and the output voltage is the voltage across the two plates of the second capacitor and is equal to half of the input voltage, because it provides more stable and efficient output voltage with a switched capacitor converter capable of achieving a safe and quick charging of large-capacity batteries (paragraph [0004]).
Regarding claim 2, Huang and Lai teach everything claimed as applied above (see claim 1). Further, Huang discloses (see figures 1-13) an output terminal of the first clamp circuit (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is; output to GIH) is electrically connected to a control terminal of the input switch (figure 11, part control terminal G1H of Q1H); and the first clamp circuit (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is) is configured to, in response to the input voltage (figure 11, part VMID) being greater than the first clamp voltage (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is), raise a control voltage of the input switch (figure 11, part Q1H) (paragraphs [0095]-[0096]; the clamper 260 is configured to clamp a voltage difference between the first inverting output end of the first switch Q1H and the first control end of the first switch Q1H in the first switch unit 310 to be below a clamping limit, so that a voltage difference between the first inverting output end of the first switch Q1H and the first non-inverting output end of the first switch Q1H does not exceed an absolute maximum rating of the first switch Q1H, and the clamping limit is less than the absolute maximum rating of the first switch Q1H. In other words, since the clamper 260 limits the voltage of the first switch Q1H during operation, the size of the first switch Q1H in the first switch unit 310 can be reduced, thereby reducing the conduction resistance of the first switch Q1H. Therefore, the clamping circuit technology can effectively reduce the overall loss of the switched capacitor converter 300).
Regarding claim 3, Huang and Lai teach everything claimed as applied above (see claim 1). Further, Huang discloses (see figures 1-13) the first clamp circuit (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is) is further configured to, in response to the input voltage (figure 11, part VMID) being greater than the first clamp voltage (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is), raise a voltage at the second terminal of the input switch (figure 11, part Q1H; lower terminal) (paragraphs [0095]-[0096]; the clamper 260 is configured to clamp a voltage difference between the first inverting output end of the first switch Q1H and the first control end of the first switch Q1H in the first switch unit 310 to be below a clamping limit, so that a voltage difference between the first inverting output end of the first switch Q1H and the first non-inverting output end of the first switch Q1H does not exceed an absolute maximum rating of the first switch Q1H, and the clamping limit is less than the absolute maximum rating of the first switch Q1H. In other words, since the clamper 260 limits the voltage of the first switch Q1H during operation, the size of the first switch Q1H in the first switch unit 310 can be reduced, thereby reducing the conduction resistance of the first switch Q1H. Therefore, the clamping circuit technology can effectively reduce the overall loss of the switched capacitor converter 300).
Regarding claim 17, claim 1 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 18, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 19, claim 1 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 20, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 21, Huang and Lai teach everything claimed as applied above (see claim 1). Further, Huang discloses (see figures 1-13) when the voltage conversion circuit (figure 11, part 300) starts or stops operating (figure 11, part 300) (paragraph [0076]; the switch driving circuit 350 generates a control signal G0 to control the path switch Q0 to be turned off, and the switch driving circuit 350 stops operating (step S80)), the ninth switch (figure 11, part Q2H; turn-off at stop operation), the tenth switch (figure 11, part Q3H; turn-off at stop operation), and the eleventh switch are all turned off (figure 11, part Q4H; turn-off at stop operation), the output voltage is 0 (figure 11, part VBAT; 0V), a voltage on the first plate of the first capacitor is 0 V (figure 11, part CFLY; upper plate CP; 0V), and thus the voltage across the first terminal and the second terminal of the input switch (figure 11, part Q1H; voltage at upper and lower terminals) is the input voltage (figure 11, part VMID); when the input voltage (figure 11, part VMID) is less than the first clamp voltage of the first clamp circuit (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is), wherein the first clamp voltage (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is) is less than a maximum withstand voltage of the input switch (figure 11, part maximum withstand voltage of Q1H), the input switch is maintained in an off state (figure 11, part Q1H; off state), and the first clamp circuit is in a non-operating state (figure 11, part first clamp circuit generated by 260 and current source Is; non-operating state because the voltage is less than the first clamp voltage); the voltage on the first plate of the first capacitor (figure 11, part CFLY; upper plate CP; 0V) and a voltage on the second plate of the first capacitor are both 0 (figure 11, part CFLY; lower plate CN; 0V), a voltage across the first terminal and the second terminal of the ninth switch (figure 11, part Q2H; voltage at upper and lower terminals is 0V), a voltage across the first terminal and the second terminal of the tenth switch (figure 11, part Q3H; voltage at upper and lower terminals is 0V), and a voltage across the first terminal and the second terminal of the eleventh switch are all 0 (figure 11, part Q4H; voltage at upper and lower terminals is 0V), and the voltage across the first terminal and the second terminal of the input switch (figure 11, part Q1H; voltage at upper and lower terminals) is less than the maximum withstand voltage of the input switch (figure 11, part maximum withstand voltage of Q1H) (paragraphs [0095]-[0096]; the clamper 260 is configured to clamp a voltage difference between the first inverting output end of the first switch Q1H and the first control end of the first switch Q1H in the first switch unit 310 to be below a clamping limit, so that a voltage difference between the first inverting output end of the first switch Q1H and the first non-inverting output end of the first switch Q1H does not exceed an absolute maximum rating of the first switch Q1H, and the clamping limit is less than the absolute maximum rating of the first switch Q1H. In other words, since the clamper 260 limits the voltage of the first switch Q1H during operation, the size of the first switch Q1H in the first switch unit 310 can be reduced, thereby reducing the conduction resistance of the first switch Q1H. Therefore, the clamping circuit technology can effectively reduce the overall loss of the switched capacitor converter 300).
Regarding claim 23, claim 21 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 25, claim 21 has the same limitations, based on this is rejected for the same reasons.
Response to Arguments
Applicant's arguments filed 06/24/2026 have been fully considered but they are not persuasive.
Applicant’s argues on pages 11-15 of the Applicant's Response (“In contrast, claim 1 limits that the first clamp circuit is electrically connected across the first terminal and the second terminal of the input switch (distinguishing feature 1), but the first clamp circuit is not electrically connected a control terminal of the input switch, which is different from that "the damper 260 is coupled between the first inverting output end of the first switch Q1L and the first control end of the first switch of Q1L" of Huan. Furthermore, Huang does not disclose the limitations of "when the voltage conversion circuit normally operates, the input switch and the tenth switch are both turned on, and the ninth switch and the eleventh switch are both turned off, so that the first capacitor and the second capacitor are connected in series, the first capacitor and the second capacitor are in a charging state, and energy provided by the input voltage is stored in the first capacitor and the second capacitor" (distinguishing feature 2) and "upon completion of charging, a voltage across the first plate and the second plate of the first capacitor and a voltage across two plates of the second capacitor are both half of the input voltage, afterwards, the ninth switch and the eleventh switch are both turned on, and the input switch and the tenth switch are both turned off, so that the first capacitor and the second capacitor are connected in parallel, the first capacitor and the second capacitor are in a discharging state, the energy stored in the first capacitor and the second capacitor is released, and the output voltage is the voltage across the two plates of the second capacitor and is equal to half of the input voltage" (distinguishing feature 3) as claimed in claim 1 of the present application”).
The Examiner respectfully disagrees with Applicant’s arguments, because Huang discloses the first clamp circuit (figure 11, part first clamp circuit generated by 260 and current source Is) is electrically connected across the first terminal and the second terminal of the input switch (figure 11, part Q1H; upper and lower terminals). As disclosed above, the first clamp circuit, in Huang’s reference, is generated by 260 and current source Is (figure 11, part first clamp circuit generated by 260 and current source Is) (paragraphs [0095]-[0096]; a voltage difference between the first inverting output end of the first switch Q1H and the first non-inverting output end of the first switch Q1H does not exceed an absolute maximum rating of the first switch Q1H, and the clamping limit is less than the absolute maximum rating of the first switch Q1H. In other words, since the clamper 260 limits the voltage of the first switch Q1H during operation, the size of the first switch Q1H in the first switch unit 310 can be reduced, thereby reducing the conduction resistance of the first switch Q1H. Therefore, the clamping circuit technology can effectively reduce the overall loss of the switched capacitor converter 300). Therefore, Huang meets with the claimed limitation. Additional, Huang discloses (regarding the operation) when the voltage conversion circuit (figure 11, part 300) normally operates (figure 7), the input switch (figures 7 and 11, part Q1H; turned on between t1-t4) and the tenth switch are both turned on (figures 7 and 11, part Q3H; turned on between t1-t4), and the ninth switch (figures 7 and 11, part Q2H; turned off between t1-t4) and the eleventh switch are both turned off (figures 7 and 11, part Q4H; turned off between t1-t4), so that the first capacitor (figures 7 and 11, part CFLY; between t1-t4) and the second element are connected in series (figures 7 and 11, part BAT; between t1-t4), the first capacitor (figures 7 and 11, part CFLY; between t1-t4) and the second element are in a charging state (figures 7 and 11, part BAT; between t1-t4), and energy provided by the input voltage (figure 11, part VMID) is stored in the first capacitor (figures 7 and 11, part CFLY; between t1-t4) and the second element (figures 7 and 11, part BAT; between t1-t4) (paragraph [0074]; When the first switch unit 310 and the third switch unit 330 are turned on, and the second switch unit 320 and the fourth switch unit 340 are turned off (as shown from time point t1 to time point t4) , the capacitor CFLY forms a series circuit with the battery BAT, wherein the capacitor CFLY and the battery BAT are connected in series between the first power VMID and the ground potential. At this state, the first power VMID charges both the capacitor CFLY and the battery BAT (step S40, hereinafter referred to as the first state)); and upon completion of charging (figures 7 and 11, part upon completion of charging between t1-t4), a voltage across the first plate and the second plate of the first capacitor (figure 11, part CFLY; voltage across the upper and lower plate CP/CN) and a voltage across two plates of the second element (figures 7 and 11, part BAT; voltage across the upper and lower terminal of BAT) are both half of the input voltage (figure 11, part half of VMID; based on previous series charging process), afterwards, the ninth switch (figures 7 and 11, part Q2H; turned on between t4-t5) and the eleventh switch are both turned on (figures 7 and 11, part Q4H; turned on between t4-t5), and the input switch (figures 7 and 11, part Q1H; turned off between t4-t5) and the tenth switch are both turned off (figures 7 and 11, part Q3H; turned off between t4-t5), so that the first capacitor (figures 7 and 11, part CFLY; between t4-t5) and the second element are connected in parallel (figures 7 and 11, part BAT; between t4-t5), the first capacitor (figures 7 and 11, part CFLY; between t4-t5) and the second element are in a discharging state parallel (figures 7 and 11, part BAT; between t4-t5), the energy stored in the first capacitor (figures 7 and 11, part CFLY; between t4-t5) and the second element is released (figures 7 and 11, part BAT; between t4-t5), and the output voltage (figure 11, part VBAT) is the voltage across the two plates of the second element (figures 7 and 11, part BAT; between t4-t5) and is equal to half of the input voltage (figure 11, part half of VMID; based on previous series charging process) (paragraph [0075]; Following step S40… the switch driving circuit 350 controls the first switch Q2H of the second switch unit 320 and the first switch Q4H of the fourth switch unit 340 to be turned on through control signals G2H and G4H, respectively, and controls the first switch Q1H of the first switch unit 310 and the first switch Q3H of the third switch unit 330 to be turned off through the control signals G1H and G3H, respectively (step S60, time point t4). When the second switch unit 320 and the fourth switch unit 340 are turned on, and the first switch unit 310 and the third switch unit 330 are turned off (as shown from time point t5 to time point t8) , the capacitor CFLY forms a parallel circuit with the battery BAT, and at this state, the capacitor CFLY discharges to charge the battery BAT (step S70, hereinafter referred to as the second state)). Lai teaches a second capacitor (figure 1, part Cout). It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the voltage conversion circuit (more specific the second element) of Huang with the second capacitor features as taught by Lai and obtain a voltage conversion circuit, comprising: an input switch, a switch assembly, a first clamp circuit, a first capacitor, and a second capacitor; wherein a first terminal of the input switch is electrically connected to a voltage input terminal, a second terminal of the input switch is electrically connected to a first plate of the first capacitor, the first plate and a second plate of the first capacitor are electrically connected to a voltage output terminal of the voltage conversion circuit via the switch assembly, the first plate and the second plate of the first capacitor are further grounded via the switch assembly, the voltage output terminal is grounded via the second capacitor, and the first clamp circuit is electrically connected across the first terminal and the second terminal of the input switch; the input switch is configured to, in cooperation with the switch assembly, control an electrical connection between the first capacitor and the second capacitor, such that an output voltage of the voltage conversion circuit is less than an input voltage of the voltage conversion circuit; and the first clamp circuit is configured to, in response to the input voltage being greater than a first clamp voltage of the first clamp circuit, limit a voltage across the first terminal and the second terminal of the input switch to the first clamp voltage; wherein the switch assembly comprises: a ninth switch, a tenth switch, and an eleventh switch, wherein, a first terminal of the ninth switch is electrically connected to the second terminal of the input switch and the first plate of the first capacitor, a second terminal of the ninth switch is electrically connected to the voltage output terminal and a first terminal of the tenth switch, a second terminal of the tenth switch is electrically connected to a first terminal of the eleventh switch and the second plate of the first capacitor, and a second terminal of the eleventh switch is grounded; when the voltage conversion circuit normally operates, the input switch and the tenth switch are both turned on, and the ninth switch and the eleventh switch are both turned off, so that the first capacitor and the second capacitor are connected in series, the first capacitor and the second capacitor are in a charging state, and energy provided by the input voltage is stored in the first capacitor and the second capacitor; and upon completion of charging, a voltage across the first plate and the second plate of the first capacitor and a voltage across two plates of the second capacitor are both half of the input voltage, afterwards, the ninth switch and the eleventh switch are both turned on, and the input switch and the tenth switch are both turned off, so that the first capacitor and the second capacitor are connected in parallel, the first capacitor and the second capacitor are in a discharging state, the energy stored in the first capacitor and the second capacitor is released, and the output voltage is the voltage across the two plates of the second capacitor and is equal to half of the input voltage, because it provides more stable and efficient output voltage with a switched capacitor converter capable of achieving a safe and quick charging of large-capacity batteries (paragraph [0004]). Therefore, the combination between Huang and Lai meet with the claimed limitation.
Allowable Subject Matter
Claims 22, 24 and 26 are objected, but would be allowable upon overcoming the objections set forth in this action and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination) when the input voltage is greater than the first clamp voltage of the first clamp circuit, the first clamp circuit is in an operating state, the voltage on the second plate of the first capacitor is 0, and the first clamp circuit is configured to raise the voltage on the first plate of the first capacitor from 0 V to a voltage difference of Vin-Vclamp 1 [based on objection presented above], wherein the Vin represents the input voltage, and the Vclamp 1 [based on objection presented above] represents the first clamp voltage of the first clamp circuit; the voltage across the first terminal and the second terminal of the tenth switch and the voltage across the first terminal and the second terminal of the eleventh switch are both 0, the voltage across the first terminal and the second terminal of the input switch is the first clamp voltage of the first clamp circuit, the voltage across the first terminal and the second terminal of the ninth switch is the voltage difference of Vin-Vclamp 1, and the voltage difference of Vin-Vclamp 1 is less than a maximum withstand voltage of the ninth switch, in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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