DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Response to Restriction filed on 02/09/2026. The applicant elects the Species 1: Figure 3 (without traverse).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because the abstract in last sentence recites “such that a switch with a low withstand voltage is selected and hence a conversion efficiency is improved” that is considered legal phraseology. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities: the Specification should be revised carefully because it contains some typographical errors (Example: page 16; paragraph [0072]; last sentence recites “the input switch C’”, which should be “the input switch Q’” because in way is supported in the Figures).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 13 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0092623), hereinafter Huang, in view of Lai et al. (US 2023/0015792), hereinafter Lai.
Regarding claim 1, Huang discloses (see figures 1-13) a voltage conversion circuit (figure 11, part 300), comprising: an input switch (figure 11, part Q1H), a switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H), a first clamp circuit (figure 11, part first clamp circuit generated by 260 and current source Is), a first capacitor (figure 11, part CFLY) and a second element (figure 11, part BAT); wherein a first terminal of the input switch (figure 11, part Q1H; upper terminal) is electrically connected to a voltage input terminal (figure 11, part VMID terminal), a second terminal of the input switch (figure 11, part Q1H; lower terminal) is electrically connected to a first plate of the first capacitor (figure 11, part CFLY; upper plate CP), two plates of the first capacitor (figure 11, part CFLY; upper/lower plates CP/CN) are electrically connected to a voltage output terminal (figure 11, part VBAT terminal) via the switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H), the two plates of the first capacitor (figure 11, part CFLY; upper/lower plates CP/CN) are further grounded (figure 11, part grounded) via the switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H), the voltage output terminal (figure 11, part VBAT terminal) is grounded via the second element (figure 11, part BAT), and the first clamp circuit (figure 11, part first clamp circuit generated by 260 and current source Is) is electrically connected across two terminals of the input switch (figure 11, part Q1H); the input switch (figure 11, part Q1H) is configured to, in cooperation with the switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H), control an electrical connection between the first capacitor (figure 11, part CFLY) and the second element (figure 11, part BAT), such that an output voltage (figure 11, part VBAT) is less than an input voltage (figure 11, part VMID) (paragraph [0069]; the voltage of the first power VMID is greater than the voltage of the second power VBAT); and the first clamp circuit (figure 11, part first clamp circuit generated by 260 and current source Is) is configured to, in response to the input voltage being (figure 11, part VMID) greater than a first clamp voltage (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is), limit a voltage across the two terminals of the input switch (figure 11, part Q1H) to the first clamp voltage (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is) (paragraphs [0095]-[0096]; the clamper 260 is configured to clamp a voltage difference between the first inverting output end of the first switch Q1H and the first control end of the first switch Q1H in the first switch unit 310 to be below a clamping limit, so that a voltage difference between the first inverting output end of the first switch Q1H and the first non-inverting output end of the first switch Q1H does not exceed an absolute maximum rating of the first switch Q1H, and the clamping limit is less than the absolute maximum rating of the first switch Q1H. In other words, since the clamper 260 limits the voltage of the first switch Q1H during operation, the size of the first switch Q1H in the first switch unit 310 can be reduced, thereby reducing the conduction resistance of the first switch Q1H. Therefore, the clamping circuit technology can effectively reduce the overall loss of the switched capacitor converter 300).
Huang does not expressly disclose a second capacitor.
Lai teaches (see figures 1-7) a voltage conversion circuit (figure 1), comprising: an input switch (figure 1, part SW4), a switch assembly (figure 1, part switch assembly generated by SW1-SW3), a first capacitor (figure 1, part Cfly), and a second capacitor (figure 1, part Cout); wherein a first terminal of the input switch (figure 1, part SW4; upper terminal) is electrically connected to a voltage input terminal (figure 1, part VIN terminal), a second terminal of the input switch (figure 1, part SW4; lower terminal) is electrically connected to a first plate of the first capacitor (figure 1, part Cfly; upper first plate), two plates of the first capacitor (figure 1, part Cfly; upper/lower plates) are electrically connected to a voltage output terminal (figure 1, part VOUT terminal) via the switch assembly (figure 1, part switch assembly generated by SW1-SW3), the two plates of the first capacitor (figure 1, part Cfly; upper/lower plates) are further grounded (figure 1, part GND) via the switch assembly (figure 1, part switch assembly generated by SW1-SW3), the voltage output terminal (figure 1, part VOUT terminal) is grounded (figure 1, part grounded) via the second capacitor (figure 1, part Cout), and the input switch (figure 1, part SW4) is configured to, in cooperation with the switch assembly (figure 1, part switch assembly generated by SW1-SW3), control an electrical connection between the first capacitor (figure 1, part Cfly) and the second capacitor (figure 1, part Cout).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the voltage conversion circuit of Huang with the second capacitor features as taught by Lai and obtain a voltage conversion circuit, comprising: an input switch, a switch assembly, a first clamp circuit, a first capacitor, and a second capacitor; wherein a first terminal of the input switch is electrically connected to a voltage input terminal, a second terminal of the input switch is electrically connected to a first plate of the first capacitor, two plates of the first capacitor are electrically connected to a voltage output terminal via the switch assembly, the two plates of the first capacitor are further grounded via the switch assembly, the voltage output terminal is grounded via the second capacitor, and the first clamp circuit is electrically connected across two terminals of the input switch; the input switch is configured to, in cooperation with the switch assembly, control an electrical connection between the first capacitor and the second capacitor, such that an output voltage is less than an input voltage; and the first clamp circuit is configured to, in response to the input voltage being greater than a first clamp voltage, limit a voltage across the two terminals of the input switch to the first clamp voltage, because it provides more stable and efficient output voltage with a switched capacitor converter capable of achieving a safe and quick charging of large-capacity batteries (paragraph [0004]).
Regarding claim 2, Huang and Lai teach everything claimed as applied above (see claim 1). Further, Huang discloses (see figures 1-13) an output terminal of the first clamp circuit (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is; output to GIH) is electrically connected to a control terminal of the input switch (figure 11, part control terminal G1H of Q1H); and the first clamp circuit (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is) is configured to, in response to the input voltage (figure 11, part VMID) being greater than the first clamp voltage (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is), raise a control voltage of the input switch (figure 11, part Q1H) (paragraphs [0095]-[0096]; the clamper 260 is configured to clamp a voltage difference between the first inverting output end of the first switch Q1H and the first control end of the first switch Q1H in the first switch unit 310 to be below a clamping limit, so that a voltage difference between the first inverting output end of the first switch Q1H and the first non-inverting output end of the first switch Q1H does not exceed an absolute maximum rating of the first switch Q1H, and the clamping limit is less than the absolute maximum rating of the first switch Q1H. In other words, since the clamper 260 limits the voltage of the first switch Q1H during operation, the size of the first switch Q1H in the first switch unit 310 can be reduced, thereby reducing the conduction resistance of the first switch Q1H. Therefore, the clamping circuit technology can effectively reduce the overall loss of the switched capacitor converter 300).
Regarding claim 3, Huang and Lai teach everything claimed as applied above (see claim 1). Further, Huang discloses (see figures 1-13) the first clamp circuit (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is) is further configured to, in response to the input voltage (figure 11, part VMID) being greater than the first clamp voltage (figure 11, part first clamp voltage at first clamp circuit generated by 260 and current source Is), raise a voltage at the second terminal of the input switch (figure 11, part Q1H; lower terminal) (paragraphs [0095]-[0096]; the clamper 260 is configured to clamp a voltage difference between the first inverting output end of the first switch Q1H and the first control end of the first switch Q1H in the first switch unit 310 to be below a clamping limit, so that a voltage difference between the first inverting output end of the first switch Q1H and the first non-inverting output end of the first switch Q1H does not exceed an absolute maximum rating of the first switch Q1H, and the clamping limit is less than the absolute maximum rating of the first switch Q1H. In other words, since the clamper 260 limits the voltage of the first switch Q1H during operation, the size of the first switch Q1H in the first switch unit 310 can be reduced, thereby reducing the conduction resistance of the first switch Q1H. Therefore, the clamping circuit technology can effectively reduce the overall loss of the switched capacitor converter 300).
Regarding claim 13, Huang and Lai teach everything claimed as applied above (see claim 1). Further, Huang discloses (see figures 1-13) the switch assembly (figure 11, part switch assembly generated by Q2H, Q3H and Q4H) comprises: a ninth switch (figure 11, part Q2H), a tenth switch (figure 11, part Q3H), and an eleventh switch (figure 11, part Q4H); wherein a first terminal of the ninth switch (figure 11, part Q2H; upper terminal) is electrically connected to the first plate of the first capacitor (figure 11, part CFLY; upper plate CP), a second terminal of the ninth switch (figure 11, part Q2H; lower terminal) is electrically connected to the voltage output terminal (figure 11, part VBAT terminal) and a first terminal of the tenth switch (figure 11, part Q3H; upper terminal), a second terminal of the tenth switch (figure 11, part Q3H; lower terminal) is electrically connected to a first terminal of the eleventh switch (figure 11, part Q4H; upper terminal) and a second plate of the first capacitor (figure 11, part CFLY; lower plate CN), and a second terminal of the eleventh switch is grounded (figure 11, part Q4H; lower terminal grounded).
Regarding claim 17, claim 1 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 18, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 19, claim 1 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 20, claim 2 has the same limitations, based on this is rejected for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838