Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5, 8, 11-12, 15 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goel et al., US Patent 11,816,103, in view of Gschwind, US PGPub 2018/0024930, further in view of Sorenson, III, US Patent 10,210,167, further in view of Jain et al., US PGPub 2022/0292061.
With respect to claim 1, Goel teaches a system comprising:
a processor (col. 13, lines 39-41, processor 3010A); and
a memory comprising computer program code (col. 13, lines 39-41, system memory 3020 configure to store program instructions), the memory and the computer program code configured to cause the processor to perform operations comprising:
adding, by a virtual storage area network (vSAN) component executing on a compute node in a vSAN, prefetch requests to a prefetch request queue (col. 8, lines 23-26, the prefetch requests in the prefetch request buffer 300. Col. 14, lines 4-16 discloses that the network interface supports a communication network such as a Fibre Channel SAN, which is an example of a virtual SAN.);
obtaining, by a first prefetch thread, a first prefetch request of the prefetch requests in the prefetch request queue (col. 7, lines 35-47, a first thread of threads 201A-201Z performs a prefetch. Col. 8, lines 23-35 describe that prefetches are performed by selecting prefetch requests from the prefetch request buffer 300);
obtaining, by a second prefetch thread, a second prefetch request of the prefetch requests in the prefetch request queue (col. 7, lines 35-47, a second one of threads 201A-201Z performs a prefetch in parallel. Col. 8, lines 23-35 describe that prefetches are performed by selecting prefetch requests from the prefetch request buffer 300);
Goel fails to teach updating a memory cache with first and second metadata associated with LBAs.
Gschwind teaches:
updating a memory cache with first metadata associated with a first logical block address (LBA) of the first prefetch request from a first data store by the first prefetch thread (pars. 49-50, the list/queue 152 corresponds to the memory cache, and the prefetch request or pointer to the block of data corresponds to the first metadata. Par. 31 discloses that a prefetch request contains a logical address, which is the LBA of the claim);
updating the memory cache with second metadata associated with a second LBA of the second prefetch request from the first data store by the second prefetch thread, wherein updating the memory cache with the first metadata and updating the memory cache with the second metadata are performed in parallel (pars. 49-50, the list/queue 152 corresponds to the memory cache, and the prefetch request or pointer to the block of data corresponds to the first metadata. Par. 49 discloses that multiple prefetch processes occur in a non-contiguous manner, i.e. in parallel. Par. 31 discloses that a prefetch request contains a logical address, which is the LBA of the claim);
Goel and Gschwind fail to teach data bank flushing as required by the claim.
Sorenson teaches:
determining a data bank associated with the memory cache has reached a flush threshold (col. 29, lines 43-59, the free space available in the RAM is below a threshold. The RAM of Sorenson corresponds to the data bank associated with the memory cache);
writing data in the data bank associated with the first prefetch request and the second prefetch request to a second data store (col. 29, lines 43-59, flushing the RAM, with the SSD being the second data store. Col. 27, line 52 through col. 28, line 28 describe the flushing from RAM to SSD process. The RAM contains data from multiple prefetch requests, as described in col. 31, line 66, through col. 321, line 29, so therefore the data is associated with first and second prefetch requests. The SSD is the second data store); and
updating a metadata structure of the first data store using the first metadata and second metadata in the updated memory cache, wherein the updated metadata structure of the first data store indicates data locations in the second data store to which the data associated with the first prefetch request and the second prefetch request is written (col. 27, line 52 through col. 28, line 28, after flushing, data storage information is updated to indicate the SSD data pages that are overwritten in the SSD and are dirty in the SSD. The data storage information corresponds to a metadata structure of the first data store of the claim).
Goel, Gschwind, and Sorenson fail to teach the vSAN is a component of a virtualization platform, wherein the virtualization platform includes hypervisor functionality, the compute node hosts one or more virtual machines managed by the virtualization platform, and the vSAN component is configured to virtualize physical storage components of one or more storage nodes separate from the compute node to provide a distributed shared data store.
Jain teaches:
a virtual storage area network (vSAN) component of a virtualization platform, wherein the virtualization platform includes hypervisor functionality, the compute node hosts one or more virtual machines managed by the virtualization platform, and the vSAN component is configured to virtualize physical storage components of one or more storage nodes separate from the compute node to provide a distributed shared data store (pars. 24-27).
It would have been obvious to one of ordinary skill in the art, having the teachings of Goel and Gschwind before him before the earliest effective filing date, to modify the memory system of Goel with the memory stem of Gschwind, in order to improve system performance by prefetching data in the ideal order, as taught by Gschwind in pars. 46-47. Further, it would have been obvious, also having the teachings of Sorenson before him before the earliest effective filing date, to modify the memory system of Goel and Gschwind with the memory system of Sorenson, in order to flush data to non-volatile SSD memory, as it allows data pages cached in the SSD to persist across system crashes or restarts, as taught by Sorenson in col. 24, lines 12-19. Finally, it would have been obvious, also having the teachings of Jain before him before the earliest effective filing date, to modify the memory system of Goel, Gschwind and Sorenson with the memory system of Jain, as the use of the virtual SAN component saves processing power for storage nodes and allows compute nodes to operate with a wide range of storage options, as taught by Jain in par. 26.
With respect to claim 4, Goel, Gschwind, Sorenson and Jain teach the limitation of the parent claim. Gschwind further teaches the system of claim 1, wherein updating the metadata structure of the first data store includes:
updating a metadata address map with the first metadata and the second metadata after writing the data in the data bank to the second data store, wherein the metadata address map includes mappings of LBAs of data blocks to physical block addresses (PBAs) of data blocks within the second data store (pars. 63-65, storing the translation mapping in a structure associated with address translation, such as a translation look-aside buffer. Par. 41 teaches that the TLB is formed for data that is prefetched (after writing the data in the data bank of the second store)).
With respect to claim 5, Goel, Gschwind, Sorenson and Jain teach the limitation of the parent claim. Gschwind further teaches the system of claim 1, the operations further comprising:
clearing the prefetch request queue of prefetch requests associated with data written to the second data store after writing the data in the data bank to the second data store (par. 54, step 310, processing the block of data); and
clearing the memory cache of metadata associated with data that has been written to the second data store after writing the data in the data bank to the second data store (par. 54, step 312, removing the indication of the block of data from the queue).
Claims 8 and 11-12 are a computerized method that corresponds to claims 1 and 4-5 and are rejected using similar logic.
Claims 15 and 18-19 are a computer storage media that corresponds to claims 1 and 4-5 and are rejected using similar logic.
Claim(s) 2-3, 7, 9-10, 14, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goel, Gschwind, Sorenson and Jain as applied to claims 1, 8, and 15 above, and further in view of Meier et al., US PGPub 2021/0303471.
With respect to claim 2, Goel, Gschwind, Sorenson and Jain teach the limitations of the parent claim, but fail to teach identifying a missing LBA. Meier teaches the system of claim 1, the operations further comprising:
identifying, by the first prefetch thread, that the first metadata associated with the first LBA is missing in the memory cache, wherein updating the memory cache with the first metadata is based on identifying that the first metadata is missing in the memory cache (par. 83, determining if the demand access is a hit or miss, and allocating an access map entry in response to a miss); and
identifying, by the second prefetch thread, that the second metadata associated with the second LBA is missing in the memory cache, wherein updating the memory cache with the second metadata is based on identifying that the second metadata is missing in the memory cache (pars. 83-84, determining if the demand access is a hit or miss, and allocating an access map entry in response to a miss. As disclosed in par. 48, the primary prefetch circuit supports a number of concurrent operations, Q, so the second prefetch thread corresponds to a second of the Q concurrent operations performing the process described in par. 83 and shown in fig. 6).
It would have been obvious, having the teachings of Goel, Gschwind, Sorenson, Jain and Meier before him before the earliest effective filing date, to modify the memory system of Goel, Gschwind, Sorenson and Jain with the memory system of Meier, in order to accurately generate a significant number of prefetches, as taught by Meier in par. 85.
With respect to claim 3, Goel, Gschwind, Sorenson, Jain and Meier teach the limitations of the parent claims. Meier further teaches the system of claim 2, the operations further comprising:
removing, by the first prefetch thread, the first LBA from the first prefetch request to form a modified prefetch request; adding, by the first prefetch thread, the modified prefetch request to the prefetch request queue prior to updating the memory cache of the data bank with the first metadata (par. 86, when there is a hit to an existing stream being prefetched, instead of allocating a new entry, the hitting stream memory location is updated, this updated entry being used for future prefetches);
Goel teaches:
wherein obtaining the second prefetch request, including the one or more remaining LBAs, by the second prefetch thread includes obtaining the modified prefetch request added to the prefetch request queue by the first prefetch thread (col. 7, lines 35-47, a second one of threads 201A-201Z performs a prefetch in parallel. Col. 8, lines 23-35 describe that prefetches are performed by selecting prefetch requests from the prefetch request buffer 300);
With respect to claim 7, Goel, Gschwind, Sorenson and Jain teach the limitations of the parent claim, but fail to teach wherein the second data store is a log-structured data store and writing data in the data bank to the second data store includes performing a full stripe write to the second data store. Meier further teaches the system of claim 1, the operations further comprising: avoiding reads from the first data store by waiting until the first and second prefetch threads have completed updating the memory cache before writing the data from the data bank to the second data store (par. 45, demand accesses are avoided until the prefetch requests are complete).
It would have been obvious, having the teachings of Goel, Gschwind, Sorenson, Jain and Meier before him before the earliest effective filing date, to modify the memory system of Goel, Gschwind, Jain and Sorenson with the memory system of Meier, in order to accurately generate a significant number of prefetches, as taught by Meier in par. 85.
Claims 9-10 and 14 are a computerized method that corresponds to claims 2-3 and 7 and are rejected using similar logic.
Claims 16-17 are a computer storage media that corresponds to claims 2-3 and is rejected using similar logic.
Claim(s) 6, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goel, Gschwind, Sorenson and Jain as applied to claims 1, 8, and 15 above, and further in view of Kalamatianos el., US PG Pub 2024/0111676.
With respect to claim 6, Goel, Gschwind, Sorenson and Jain teach all limitations of the parent claim, but fail to teach a trained machine learning model. Kalamatianos further teaches the system of claim 1, the operations further comprising:
activating a third prefetch thread based on analysis of a current state of the first data store and a current quantity of active prefetch threads using a trained machine learning model (par. 56-58, training is implemented on three different threads simultaneously, meaning that if there are only two threads, a third thread is activated, the training also based on whether there are irregular memory accesses (current state of the first data store)).
It would have been obvious, having the teachings of Goel, Gschwind, Sorenson, Jain and Kalamatianos before him before the earliest effective filing date, to modify the memory system of Goel, Gschwind, Sorenson and Jain with the memory system of Kalamatianos, in order to improve a prefetchers' ability to predict which data to fetch and/or obtain from main memory, as taught by Kalamatianos in par. 2.
Claim 13 is a computerized method that corresponds to claim 6 and is rejected using similar logic.
Claim 20 is a computer storage media that corresponds to claim 6 and is rejected using similar logic.
Response to Arguments
Applicant's arguments filed 03/19/2026 have been fully considered but they are not persuasive. Firstly, the objections to the claims and the rejections under 35 USC 112(b) are withdrawn, due to the claim amendments. Applicant’s arguments on pages 14-17 are directed towards the cited references failing to teach that the vSAN is a component of a virtualization platform, wherein the virtualization platform includes hypervisor functionality, the compute node hosts one or more virtual machines managed by the virtualization platform, and the vSAN component is configured to virtualize physical storage components of one or more storage nodes separate from the compute node to provide a distributed shared data store. These arguments are moot, as the new Jain reference has been supplied to teach these features.
Conclusion
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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