DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The Examiner recognizes Applicant’s cooperation in amending the claims with commensurate scope so as to comply with the previously made enablement and written description rejections. The Examiner recognizes Applicant’s cooperation in amending claims 3-4 and 15 for compliance with the indefiniteness rejections previously made however it would seem there is still some confusion regarding the claimed arrangement.
Applicant's arguments filed 12/05/2025 directed towards the amended claims have been fully considered but they are not fully persuasive.
On Page 3 of the Arguments / Remarks, Applicant states Sakaida teaches 121 and 122 are ‘patch antennas’ and that 141A3 is a feed line such that there is no disclosure that 141A3 is a patch antenna. However it is noted that "[t]he use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). E.g.., see MPEP § 2123. Sakaida’s ‘feed lines’ are flat conductive elements that conduct current similar to Applicant’s ‘patch antenna’; a person of ordinary skill in the art would look upon flat conductive elements conducting current including the antenna feed signal to be considered ‘patch antennas’. The Specification further suggests that such elements can be considered the staircase antenna and thus portions of the antenna; e.g., Paragraph 67 suggests that signal feeds are included in ‘staircase antennas’. There is no distinguishing feature of the claimed patch antenna which distinguish them from Sakaida’s feed lines beyond their structural arrangement which is taught by Sakaida as presented in the current Office Action and the previously. Applicant may present features which distinguish patch antenna such as a certain wavelength size suggesting they radiate the signal. Accordingly Applicant’s argument that Sakaida’s feed lines are not ‘patch antennas’ is not convincing.
With regard to generic arguments directed towards the newly amended limitations, i.e., laterally offset, see the rejection herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4 is directed towards the embodiments of FIGS. 10A-10B. Thus the arrangement of the second staircase antenna coincides with the arrangement of elements of a side in a direction of the staircase antenna, for example 101b, 108b, 301b, 302, 109b, and 103b. Accordingly the terms “coupling” and “directly connected” are appropriate for a fourth via, e.g., 108b and 301b, coupling the fourth patch antenna, e.g., 101b, to the second patch antenna, e.g., 302, and a fifth via, e.g., 109b, directly connecting the second patch antenna, e.g., 302, to the fifth patch antenna, e.g., 103b, for the FIG. 10 embodiment. However the claimed arrangement calls into question the limitations and relationship of the claim 1 antenna regarding “a second via connecting the first patch antenna to the second patch antenna”. It is unclear if claim 4 is claiming a different arrangement from the antenna of claim 1 with regard to one side of the FIG. 10 embodiment because of the terms “connecting” used for the relationship between the first patch and the second patch in claim 1 and the term “coupling” used for the relationship between the fifth and second patch in claim 4. The Examiner believes the root of this issue is that FIG. 10 is a mutually exclusive embodiment from the FIGS 3-5 embodiment, where FIG. 10 has a capacitive coupling of the first and fourth patch antennas to the second patch antenna and FIGS. 3-5 has a directly connected relationship of the first patch antenna to the second patch antenna. However if the subject matter of claim 4 is incorporated into claim 1 and the claim 1 language for the relationship of the first patch and the second patch is amended to reflect the ‘coupled’ and ‘directly connected’ language, the Examiner anticipate the claim to be allowable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7-10, 13, 15, 18, 20, and 22-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WO2021166443 A1 (US20220384945A1 being a PCT CON thereof and utilized for an English translation and referred to hereinafter as “Sakaida”)
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Claim 1, 13, and 20: Sakaida teaches a circuit board (e.g., see 130 in FIG. 2-3) and method of antenna formation comprising: a plurality of conductive layers (e.g., of the 121, 122, 146, GND) separated by dielectric (e.g., see Para. 41) in the circuit board; a first staircase antenna including a first patch antenna, a second patch antenna, and a third patch antenna as steps of the first staircase antenna, wherein the first patch antenna (e.g., see 1st patch in annotated FIG. 14 above showing electrode 146 of feed line 141A or 141B) is formed on a first conductive layer of the plurality of conductive layers of the circuit board (e.g., see Para. 50); wherein the second patch antenna (e.g., see 2nd patch in annotated FIG. 14 above or 121) is formed on a second conductive layer of the plurality of conductive layers of the circuit board and is laterally offset from the first patch antenna in a first direction (e.g., the annotated 2nd patch is laterally offset from the 1st patch as shown and does not overlap the 1st patch), and wherein the third patch antenna (e.g., 3rd patch in annotated FIG. 14 above) is formed on a third conductive layer of the plurality of conductive layers and is laterally offset from the second patch antenna in the first direction (e.g., wherein the 3rd patch is laterally offset from the 2nd patch as shown and does not overlap the 2nd patch); a first via (e.g., see 1st via in annotated FIG. 14 above, see Para. 50) in the circuit board connected to the first patch antenna and configured to carry a radio frequency (RF) signal (e.g., see Para. 47); and a second via (e.g., see 2nd via in annotated FIG. 14 above) in the circuit board connecting the first patch antenna to the second patch antenna (e.g., as shown) and laterally offset from the first via in the first direction (wherein the 2nd via is laterally offset from the 1st via as shown above and does not overlap the 1st via); and a third via (e.g., see 3rd via in annotated FIG. 14 above) connecting the second patch antenna to the third patch antenna and laterally offset from the second via in the first direction (as shown).
Alternatively, under a different interpretation of Sakaida, the labeled 3rd patch antenna in the annotated Figure is the 2nd patch antenna, the 2nd patch antenna is the 3rd patch antenna and all the remaining parts are the same as labeled.
Claim 3: Sakaida teaches the circuit board of Claim 1, further comprising a second staircase antenna including a fourth patch antenna (e.g., see 4th patch of feed line 141A or 141B different from feed line of 1st patch, i.e., two feed lines as shown in FIG. 2 perspective) formed on the first conductive layer (e.g., feed lines 141A and 141B being designed the same), the second patch antenna formed on the second conductive layer (Id.), a fifth patch antenna (e.g., see 5th patch of feed line 141A or 141B different from feed line of 3rd patch) formed on the third conductive layer, wherein the second patch antenna is laterally offset from the fourth patch antenna in a second direction substantially perpendicular to the first direction, and the fifth patch is laterally offset from the second patch antenna in the second direction (e.g., as shown, Id.).
Claim 7, 18, and 22: Sakaida teaches the circuit board of Claim 1, the method of Claim 13, or the staircase antenna structure of Claim 20, respectively, further comprising a ground plane (e.g., see GND) on a fourth conductive layer of the plurality of conductive layers, and an RF signal route (e.g., see RFIC 110 on 132 in FIG. 3) on a fifth conductive layer of the plurality of conductive layers.
Claim 8 and 23: Sakaida teaches the circuit board of Claim 7 and the staircase antenna of Claim 22, respectively, wherein the first patch antenna is over the RF signal route, the second patch antenna is over the first patch antenna, and the third patch antenna is over the second patch antenna (e.g., wherein for this claim, the different alternative interpretation of Sakaida is used where the 3rd patch antenna in the annotated Figure of Sakaida above is the 2nd patch and the 2nd patch is the 3rd patch while still meeting the claim 7 and 1 limitations).
Claim 9 and 24: Sakaida teaches the circuit board of Claim 7 and the staircase antenna of Claim 22, respectively, wherein the third patch antenna is over the RF signal route, the second patch antenna is over the third patch antenna, and the first patch antenna is over the second patch antenna (wherein for this claim, the 1st patch antenna in the annotated Figure of Sakaida above is redefined as 3rd patch antenna and the 3rd patch antenna is redefined as the 2nd patch, and the 2nd patch is redefined as the 1st patch, while still meeting the claim 7 and 1 limitations).
Claim 10 and 25: Sakaida teaches the circuit board of Claim 7 and the staircase antenna of Claim 22, respectively, wherein the first via passes through an opening in the ground plane to connect the RF signal route to the first patch antenna (e.g., see opening for 141A-B in GND).
Claim 15: Sakaida teaches the method of Claim 13, further comprising forming a second staircase antenna in the circuit board, the second staircase antenna including a fourth patch antenna (e.g., see 4th patch of feed line 141A or 141B different from feed line of 1st patch, i.e., two feed lines as shown in FIG. 2 perspective) formed on the first conductive layer (e.g., feed lines 141A and 141B being designed the same), a fifth patch antenna (e.g., see 5th patch of feed line 141A or 141B different from feed line of 3rd patch) formed on the third conductive layer, wherein the first staircase antenna radiates with a first antenna polarization, and the second staircase antenna radiates with a second antenna polarization (e.g., wherein each of 141A and 141B feed two different polarizations allowing second patch to radiate two different polarizations, e.g., see Para. 48-49).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakaida.
Claim 11: Sakaida does not explicitly teach the circuit board of Claim 7, further comprising a grounded cage of vias surrounding the RF signal route.
However the Examiner takes Official/Judicial Notice that a grounded case of vias surrounding the RF signal route is ‘old and well-known’ in the art.
Before the effective filing date of the invention, it would have been obvious to a skilled artisan to form the grounded case of vias surrounding the RF signal route of Sakaida in order to increase the isolation of the RF signal and reduce interference of the RF signal line.
Claim 12: Sakaida does not teach the circuit board of Claim 1, further comprising array of staircase antennas including the staircase antenna as one antenna element of the array.
However the Examiner takes Official/Judicial that forming an array of antennas given one antenna element is ‘old and well-known’ in the art.
Before the effective filing date of the invention, it would have been obvious to a skilled artisan to form an array of the antennas of Sakaida such that the circuit board includes an array of the antennas in order to improve the gain of the circuit board and/or to utilize beamforming for the circuit board.
Claim(s) 6, 17, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakaida in view of US 20090273522 A1 (hereinafter “Tatarnikov”).
Claim 6, 17, and 21: Sakaida does not explicitly teach the circuit board of Claim 1, the method of Claim 13, or the staircase antenna structure of Claim 20, respectfully, wherein the first patch antenna is wider than the second patch antenna, and the third patch antenna is wider than the second patch antenna.
However Tatarnikov teaches a circuit board (e.g., see dielectric and conductive layers in FIG. 3) and method of antenna formation comprising: a plurality of conductive layers (e.g., of the patches 322, 302 and ground 304) separated by dielectric (e.g., see 312, 332 in FIG. 3) in the circuit board; a first patch antenna (e.g., see 302) formed on a first conductive layer of the plurality of conductive layers of the circuit board; a second patch antenna (e.g., see 322) formed on a second conductive layer of the plurality of conductive layers of the circuit board; a first via (e.g., see 308 through dielectric) in the circuit board connected to the first patch antenna and configured to carry a radio frequency (RF) signal (e.g., see Para. 25); and a second via (e.g., see 328) in the circuit board connecting the first patch antenna to the second patch antenna (e.g., as shown). Further Tatarnikov teaches the circuit board of Claim 2, wherein first patch antenna is wider than the second patch antenna (e.g., see 302 wider than 322 in FIG. 3).
Before the effective filing date of the invention, it would have been obvious to a skilled artisan to form the first patch antenna is wider than the second patch antenna as taught by Tatarnikov in order to modify the resonant frequency of the first patch antenna, e.g., to operate it at a lower frequency, or to modify the beam of the signal radiated from the first patch or to reduce the interference between the two antennas when used separately, or to ensure further current passes through one of the antenna layers to induce additional current to lower the band of the signal or form additional inductive impedance. Accordingly, it would have further been obvious to a skilled artisan to form the third patch antenna is wider than the second patch antenna for similar reasons to and given the first patch antenna is wider than the second patch antenna.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAL PATEL whose telephone number is (571)270-7443. The examiner can normally be reached Monday - Friday, 8:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dimary Lopez can be reached at (571) 270-7893. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.P/Examiner, Art Unit 2845
/DIMARY S LOPEZ CRUZ/Supervisory Patent Examiner, Art Unit 2845