DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 27 October 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nasu et al. (US 2022/0140141 A1).
Regarding claim 1, Nasu discloses a lateral oriented Metal-Oxide-Semiconductor (MOS) device (Fig 6) comprising a semiconductor body (20) having a first surface, the semiconductor body comprising: a first region (51) having a first conductivity type; a trench (53) extending from the first surface into the first region, the trench comprising an insulating element (69) and a conductive element (63), wherein the insulating element is arranged in between the conductive element and the first region, and wherein the insulating element has a substantially uniform width; second and third regions (85) having a second conductivity type, the second conductivity being different from the first conductivity type, wherein the second and third regions extend from the first surface into the first region to a shallower depth than the trench so that the second and third regions are located on either side of the trench and adjacent to the trench, and are not in contact with one another; and a further insulating region (100) on the first surface comprising openings to provide electrical contact (144) to the second and third regions.
Regarding claim 2, Nasu discloses that the first region is a moderately doped substrate (low concentration can also be understood as moderately doped given that both terms are relative and are interpreted broadly).
Regarding claim 3, Nasu discloses that the first region is an EPI layer arranged over a substrate (¶83).
Regarding claim 4, Nasu discloses a further electrical contact (69) arranged to provide electrical contact to the conductive element in the trench, wherein the further electrical contact is located on a plane perpendicular to the first surface.
Regarding claim 5, Nasu discloses a lightly doped implanted channel of the first conductivity type (97) located in the first region, wherein the implanted channel connects the second and third regions respectively.
Regarding claim 6, Nasu discloses that the second and third regions are heavily doped (85, n being heavily doped compared to p-).
Regarding claim 7, Nasu discloses that the further insulating region is arranged to insulate the conductive element along the first surface.
Regarding claim 8, Nasu discloses that the second and third regions form the source and drain terminals of a MOS Field Effect Transistor (MOSFET) device, and wherein the conductive element forms the gate terminal of the MOSFET device (while integrated into further components, per Fig 1, the cited portions form a MOSFET).
Regarding claim 9, Nasu discloses that the conductive element is of metal or of poly-silicon (¶101).
Regarding claim 11, Nasu discloses a further electrical contact (69) arranged to provide electrical contact to the conductive element in the trench, wherein the further electrical contact is located on a plane perpendicular to the first surface.
Regarding claim 12, Nasu discloses a lightly doped implanted channel (97) of the first conductivity type located in the first region, wherein the implanted channel connects the second and third regions respectively.
Regarding claim 13, Nasu discloses that the second and third regions are heavily doped (n being heavily doped relative to p-).
Regarding claim 14, Nasu discloses that the further insulating region is arranged to insulate the conductive element along the first surface.
Regarding claim 15, Nasu discloses that the second and third regions form the source and drain terminals of a MOS Field Effect Transistor (MOSFET) device, and wherein the conductive element forms the gate terminal of the MOSFET device (while integrated into further components, per Fig 1, the cited portions form a MOSFET).
Regarding claim 16, Nasu discloses that the conductive element is of metal or of poly-silicon (¶101).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Nasu.
Regarding claim 10, Nasu discloses that the insulating element (¶280, the insulating element is formed by oxidation) is of silicon dioxide, Nasu does not specify that the further insulating regions are of silicon dioxide, however, in the semiconductor arts it is understood that when the material of an insulator is not specified then that insulator is silicon dioxide by default.
Alternatively, it would have been obvious to one of ordinary skill in the art at the time of filing to select silicon dioxide as the material for the further insulating regions as silicon dioxide is a common and well-understood insulating material in the art which is typically used for such purposes.
Response to Arguments
Applicant’s arguments, see pages 7 and 8, filed 06 April 2026, with respect to the 112 rejection of claim 2, have been fully considered and are persuasive. The rejection of claim 2 under 112(b) has been withdrawn.
Applicant’s arguments with respect to claim(s) 1-16 in view of the prior art have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P SHOOK whose telephone number is (571)270-7890. The examiner can normally be reached 9:00 am - 5:00 pm, Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached at (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL P SHOOK/Primary Examiner, Art Unit 2896
Prosecution Insights