DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections In claim 8, at line 9: replace “the congestion metric” with “the routing congesting metric” to correct an antecedent basis issue. Because claims 9-18 depend from claim 8 and inherit this defect, these claims are objected to as well. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer . Claims 19 and 20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 18 and 19 of copending Application No. 18/330,057 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the reference application’s claims 18 and 19 anticipate each and every limitation of instant claims 19 and 20. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Clai ms 1-7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Step 1: Statutory Categories. Claim 1 recites a “logic cell layout process”. The claim sets forth a series of steps and therefore falls within the statutory category of a process. Step 2A, Prong One: Recitation of a Judicial Exception. Claim 1 recites the steps of “transforming a circuit netlist…into a plurality of lattice graphs”, “operating a routability model to transform the lattice graphs into congestion probabilities and routability probabilities”, and “applying the…probabilities to influence transistor device placement”. The calculation of routing and congestion probabilities for advanced technology nodes cannot practically be performed in the human mind, therefore do not fall under the “mental process” grouping as clarified in the August 2025 Memorandum on Subject Matter Eligibility ( https://www.uspto.gov/sites/default/files/documents/memo-101-20250804.pdf ). However, the claim explicitly recites mathematical concepts. Specifically, generating “congestion probabilities and routability probabilities” via a “ routability model” describes mathematical calculations and statistical relationships. Therefore, the claim recites an abstract idea under the mathematical concepts grouping (MPEP § 2106.04 (a)(2)). Step 2A, Prong Two: Integration into a Practical Application. The additional elements in the claim include transforming a netlist into lattice graphs and “applying the…probabilities to influence transistor device placement in the logic cell layout”. When evaluating the claim as a whole, these additional elements do not integrate the abstract idea into a practical application. The August 2025 Memorandum reminds examiners to consider whether the claim recites only the idea of a solution or covers a practical solution to a problem, and cautions against limitations that amount to mere instructions to “apply it”. The step of “applying the…probabilities to influence transistor device placement” operates at a high level of generality and merely instructs the practitioner to apply the mathematical concept to the field of EDA. The claim fails to recite details of how the solution to the problem is accomplished. Furthermore, as emphasized in the December 2025 Memorandum ( https://www.uspto.gov/sites/default/files/documents/smeds-corps.pdf ) incorporating Ex Parte Desjardins , while software can provide non-abstract improvement to the technical field, the claim must be evaluated to ensure it reflects the disclosed improvement (MPEP § 2106.05(a)). Unlike Desjardins , which recited specific parameter adjustments that protected prior machine learning tasks to solve a specific technical problem, claim 1 recites no specific operational steps, parameter adjustments, or structural limitations that dictate how the placement is actually influenced. Additionally, claim 1 lacks any recitation of computer hardware or a technological environment, relying purely on abstract steps. Thus, the additional elements merely append the instruction to apply the mathematical concept to a generic layout process. The claim does not integrate the abstract idea into a practical application. Step 2B: Inventive concept. Claim 1 recites the additional elements of taking a netlist and making graph representations, and influencing positioning transistors . Preparing or formatting data so that a mathematical model can process it is a prerequisite step to applying the abstract idea. Under MPEP 2106.05(g), mere data gathering, regardless of whether the specific data format (lattice graphs) is novel, does not supply an inventive concept if claimed at a purely functional level without a specific, unconventional technological mechanism to achieve it. Furthermore, influencing the position of transistors is purely functional post-solution activity. It merely instructs the user to take the result of the abstract mathematical calculation and use it for its intended purpose in the field of EDA. The claim provides no specific rules, parameter adjustments, or algorithmic steps defining how the placement is physically or technologically altered. Under MPEP § 2106.05(g), linking the use of an abstract idea to a particular technological environment without reciting a specific way to achieve a physical result is insignificant extra solution activity. When viewed as an ordered combination, the steps of claim 1 fail to supply an inventive concept because they consist entirely of gathering information (transforming the netlist into graphs), analyzing information using abstract concepts (operating a routability model to calculate probabilities), and outputting the information for generic purposes (applying the probability to influence placement). Finally, an inventive concept must provide non-abstract improvement to a computer or technological environment. Claim 1 is entirely hardware agnostic; t does not recite a computer, a processor, a memory, or any physical machinery whatsoever. Because the claim lacks any physical or technological implementation, the ordered combination cannot possibly improve the functioning of a computer or provide a physical transformation. The steps remain entirely conceptual and methodological. Therefore, claim 1 and is dependent claims 2-7 are not patent eligible. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph , as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 1, at line 2: the phrase “the logic cell” lacks antecedent basis that renders the claims indefinite. A “logic cell” was never introduced on its own, it is only part of the preamble phrase “A logic cell layout process”. In claim 1, at line 4: the phrase “the logic cell layout” lacks antecedent basis that renders the claims indefinite . “A logic cell layout process” is recited in the preamble, however, th is does not necessitate the physical layout itself as data structure the claim will act upon. Claims 2-7 are rejected for their dependency on rejected base claim 1. Allowable Subject Matter Claims 8-18 are allowable over the prior art. (Claims 8-18 remain objected to, see above.) Claims 1-7 and 19-21 would be allowable if amended to overcome the applicable § 101 or double patenting rejections set forth above. (Claim 21 is objected to for depending from rejected base claim 19.) Claims 1-7, 8-18, and 19-21 would be allowable because the prior art of record does not teach or suggest a method, device, or system having all the combinations of steps or elements as recited in independent claims 1, 8, or 19, particularly including, among other things, the following: In claim 1, operating a routability model to transform the lattice graphs into congestion probabilities and routability probabilities for the logic cell layout; applying the congestion probabilities and routability probabilities to influence transistor device placement in the logic cell layout. In claim 8, generate a moving window across a circuit layout; at each of a plurality of locations of the moving window, determine a pin density; combine the pin densities from the moving window locations into a routing congestion metric for the circuit layout . In claim 19, determine pin density at a plurality of locations of the layout; and form a control signal to the device placer, the control signal formed by combining the pin densities and routing probabilities into a routing difficulty metric for the layout. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner FILLIN "Examiner name" \* MERGEFORMAT SURESH MEMULA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-8046 , and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email ( suresh.memula@uspto.gov ) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SURESH MEMULA/ Primary Examiner, Art Unit 2851