Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to claim 4 corrects the indefiniteness issue of claim 4. The 112 rejection of claim 4 is withdrawn.
Applicant’s amendment to claim 1 corrects typographical issues. The objection to claim 1 is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 7, and 11 – 12 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20140326940 A1 hereinafter Noda.
For claim 7, Noda teaches “A semiconductor memory device comprising: a first wiring extending in a first direction (fig. 2 numeral BL; fig. 14A numeral 114a’ and 114b’, Par. [0042 – 0045]); a second wiring extending in a second direction, the second direction intersecting with the first direction (fig. 2 numeral WL; fig. 14A numeral 103, Par. [0038]); a first electrode (fig. 14A numeral 104’), a second electrode (fig. 14A numeral 106’), and a third electrode (fig. 14A numeral 109’) disposed between the first wiring and the second wiring and facing each other in a third direction (fig. 14A shows electrodes 104’, 106’ and 109’ stacked facing each other), the third direction intersects with the first direction and the second direction (fig 2 shows first direction Y, second direction X, and the third direction Z that intersects the directions X an Y. Memory MC in figure 2 includes the three electrodes shown in figure 14A; Par. [0042]). The memory cell is shown to be in a third direction Z intersecting the first and second directions X and Y); a selector layer disposed between the first electrode and the second electrode (fig. 14A numeral 105’); a resistance change film disposed between the second electrode and the third electrode (fig. 14A numeral 107’), and an insulating film disposed between the third electrode and the first wiring (fig. 14A numeral 113’ and fig. 15B numeral 113’ show an insulating film disposed in a space between the electrode 109’ and the first wiring 114’), wherein the third electrode includes a first surface and a second surface opposite the first surface (fig. 14A shows the electrode 109’ having two surfaces opposite each other in the Y direction), the first surface being in contact with both of the first wiring and the insulating film (fig. 14A shows electrode 109’ having a first surface in the Y direction in contact with both the first wiring portion 114a’ and the insulating film 113’).”
For claim 11, Noda teaches “The semiconductor memory device according to claim 7, wherein the selector layer is a non-ohmic element (Par. [0030]; Par. [0035]; Par. [0038]).”
For claim 12, Noda teaches “The semiconductor memory device according to claim 11, wherein the non-ohmic element is a chalcogen or a chalcogenide (Par. [0005]; Par. [0032]).”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 6, and 9 – 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140326940 A1 hereinafter Noda in further view of US 20200044149 A1 hereinafter Yamakawa.
For claim 1, Noda teaches a semiconductor memory device comprising: a first wiring extending in a first direction (Noda, fig. 2 numeral BL; fig. 14A numeral 114a’ and 114b’, Par. [0042 – 0045]); a second wiring extending in a second direction, the second direction intersecting with the first direction (fig. 2 numeral WL; fig. 14A numeral 103, Par. [0038]); a resistance change film disposed between the first wiring and the second wiring (fig. 14A numeral 107’) ; an electrode disposed between the resistance change film and the first wiring (fig. 14A numeral 109); and a first film selectively disposed between the electrode and the first wiring (fig. 14A numeral 113’ and fig. 15B numeral 113’ show a first film disposed in a space between the electrode 109’ and the first wiring 114’), wherein the electrode includes a first surface and a second surface opposite the first surface (fig. 14A shows the electrode 109’ having two surfaces opposite each other in the Y direction), the first surface being in contact with both of the first wiring and the first film (fig. 14A shows electrode 109’ having a first surface in the Y direction in contact with both the first wiring portion 114a’ and the first film 113’). Noda is silent regarding the resistance change film comprising at least one element selected from a group consisting of germanium, antimony, and tellurium. Noda does state that the resistance change film can compose different materials depending on the desired resistance values of the device (Par. [0032]).
Yamakawa teaches a semiconductor memory device comprising: a first wiring extending in a first direction (Yamakawa, fig. 3 numeral BL); a second wiring extending in a second direction, the second direction intersecting with the first direction (fig. 3 numeral WL1); a resistance change film disposed between the first wiring and the second wiring (fig. 4A numeral 24) and including at least one element selected from the group consisting of germanium, antimony, and tellurium (Par. [0039]).
It would have been obvious before the effective filing date of the immediate invention to combine the materials in Yamakawa with the resistance change film in Noda in order to improve memory capacity and minimize writing errors caused by thermal crosstalk (Yamakawa, Par. [0044]). One would be driven to change the materials used in the resistance change film in order to achieve optimal thermal resistance in the device to prevent memory errors as described in Yamakawa (Par. [0044 - 0045]).
For claim 2, Noda and Yamakawa teach all of claim 1. Noda also shows a center portion of the first surface of the electrode is in contact with the first film (Noda, fig. 14A shows electrode 109’ with the side in the Y direction having a center portion in contact with the first film 113).
For claim 3, Noda and Yamakawa teach all of claim 1. Noda also shows a center portion of the first surface of the electrode is in contact with the first wiring (Noda, fig. 14A shows electrode 109’ with the side in the Y direction having a center portion in contact with the first wiring 114b’).
For claim 4, Noda and Yamakawa teach all of claim 1. Noda also teaches an area of the electrode in contact with the first wiring and an area of the electrode in contact with the first film are aligned with a pattern of the electrode (fig. 14A shows electrode 109’ aligned in the X direction with portions of the first wiring 114a’ and the first film 113 that are in contact with the electrode).
For claim 5, Noda and Yamakawa teaches all of claim 1. Noda and Yamakawa do not explicitly state that the thermal conductivity of the first film is lower than a thermal conductivity of the first wiring. However, Yamakawa teaches the thermal conductivity of the insulating layer being low (Par. [0041] and that one function of the device is to dissipate heat through the other layers including the wirings (Par. [0044 - 0045]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the thermal conductivity of the first film would be lower than the thermal conductivity of the first wiring, as Yamakawa teaches dissipating heat through the wiring in part by having the first film having a lower thermal conductivity in order to avoid thermal crosstalk between memory cells (Yamakawa, Par. [0044]).
For claim 6, Noda and Yamakawa teach all of claim 1. Noda also teaches the first film being an insulating film (Noda, Par. [0040 – 0041]).
For claim 9, Noda and Yamakawa teach all of claim 1. Noda also teaches the resistance change film has an amorphous state or a crystalline state depending on a temperature of the resistance change film (Par. [0005]; Par. [0032]; Par. [0031]).
For claim 10, Noda and Yamakawa teach all of claim 6. Noda also teaches the insulation film including silicon oxide or silicon nitride (Noda, Par. [0040]; Par. [0059]).
Claim(s) 8 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140326940 A1 hereinafter Noda in further view of US 20140145140 A1 hereinafter Kim.
For claim 8, Noda teaches all of claim 7. Noda does not explicitly teach that a barrier metal layer is between the second electrode and the resistance change film and between the third electrode and the resistance change film. Noda does teach that a barrier metal is used and could be inserted into the device between the resistive change film and the electrodes (Noda, Par. [0031]; Par. [0035]).
Kim teaches a barrier metal layer (Kim, fig. 2B numeral 110, 130) between the electrodes (fig. 2B numeral 100, 140, 160) and the resistance change film (fig. 2B numeral 120).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the barrier metal layers in Kim with the electrodes in Noda in order to reduce heat dissipation between the resistance change film and the adjacent layers such as the electrodes (Kim, Par. [0055]).
For claim 13, Noda and Kim teach all of claim 8. Kim also teaches the barrier metal layer including one of WN, TiN, Ta, or TaN (Kim, Par. [0084]). Noda also teaches TiN and TaN as suitable materials for barrier metal layers (Noda, Par. [0035]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815