DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (i.e., claims 1-15) in the reply filed on 05/01/2026 is acknowledged.
Claims 16-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected inventions, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 9,836,699 to Rigetti et al. (“Rigetti”).
As to independent claim 1, a system (Fig. 1), comprising: a quantum processor comprising a plurality of qubits (14:47-49. Rigetti teaches a quantum processor includes multiple qubit devices.); one or more interconnect chips bonded to the quantum processor (10:10-34, 11:49-67, 12:1-3. Rigetti teaches an interposer attached/bonded to the quantum circuit device/circuit wafer. Under BRI, Rigetti’s interposer corresponds to “interconnect chip” because it is a chip/package-level intermediate structure that provides signal interconnection between cables and the quantum circuit device.); and one or more cable connections coupled to the one or more interconnect chips (10:12-16, 11:51-55, 15:25-29. Rigetti teaches a connectorization layer of the interposer having terminals for connecting to cables.), wherein the one or more interconnect chips comprise one or more signal routings from the one or more cable connections to the quantum processor (10:15-22, 11:15-25, 56-61. Rigetti teaches the interposer includes signal lines electrically coupled to the cable terminals and to the quantum circuit device/circuit wafer.) wherein a first signal can pass from the one or more cable connections to at least one of the plurality of qubits (10:22-25, 15:1-8, 17-29, 61-65. Rigetti teaches signals pass from cables through the interposer to the quantum circuit device, and further teaches control signals are applied to qubit devices.).
As to claim 2, the system of claim 1, wherein the quantum processor is bonded to the one or more interconnect chips (11:49-67, 12:1-3. Rigetti teaches the quantum processor is bonded to the one or more interconnect chips. In particular, Rigetti teaches attaching an interposer to a circuit wafer for a quantum circuit device and further teaches the attaching of the interposer to the circuit wafer can include wafer bonding a wafer of the IC layer to the circuit wafer. Rigetti also teaches the interposer can be attached to the circuit wafer using a flip-chip method. Thus, Rigetti teaches bonding the quantum circuit device/circuit wafer, which corresponds to the claimed quantum processor, to the interposer, which corresponds to the claimed interconnect chip.).
As to claim 3, the system of claim 1, wherein the quantum processor is bonded to a substrate, and wherein a second signal passes from the substrate to the quantum processor (10:34-41, 11:15-25, 56-61. Rigetti’s quantum circuit device/circuit wafer supporting quantum circuits corresponds to the claimed quantum processor. Rigetti teaches an integrated circuit layer includes a substrate bonded to the circuit wafer. Thus, Rigetti teaches the quantum processor bonded to a substrate. Rigetti also teaches signal lines on/through the interposer substrate or PCB are electrically connected to the circuit wafer/quantum circuit device. Those signal lines carry DC and microwave signals. This teaches a signal passing from the substrate to the quantum processor.).
As to claim 9, the system of claim 1, wherein the one or more cable connections comprise a reusable connection (49:29-59, 50:48-52, 51:18-26, 52:29-34. Rigetti teaches a multilayer interposer for connecting a quantum circuit device to cables and a connectorization layer having connectors for cables. Rigetti further teaches spring loaded connections may be used in the interposer assembly. Rigetti also disclose thinnerposer/fuzzbutton interconnects in the cable connection path, including fuzz buttons registered with electrical contacts connected to cables and fuzz buttons registered with cable connectors on a connectorization layer. Because these spring loaed/fuzz button structures are compressible connector-type connections, Rigetti teaches reuseable connection under BRI.).
As to claim 15, the system of claim 1, wherein the quantum processor comprises an interposer bonded to a quantum chip (10:10-13,31-34, 11:49-67, 12:1-3. Rigetti teaches a quantum computing apparatus including a quantum circuit device and an interposer, and further teaches the quantum circuit device includes a circuit wafer supporting a quantum circuit. Rigetti teaches attaching the interposer to the circuit wafer and further discloses such attachment can include wafer bonding or flip-chip attachment. The circuit wafer supporting the quantum circuit reasonably corresponds to the claimed quantum chip, and the interposer bonded to that circuit wafer teaches the claimed interposer bonded to a quantum chip.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 rejected under 35 U.S.C. 103 as being unpatentable over Rigetti in view of US Patent No. 10,163,798 to Alur et al. (“Alur”).
Rigetti teaches the limitations of claims 1 and 3 from which claim 4 depends. Rigetti, however, does not teach the one or more interconnect chips are bonded to the substrate via an adhesive.
Alur teaches a bridge die seated on an adhesive (3:30-32, 8:64-65), where a bridge die is an interconnect die/chip and the adhesive bonds it to a package substrate.
It would have been obvious to a PHOSTIA to have combined the teachings of Rigetti and Alur to implement the known technique where a bridge/interconnect die is seated in a substrate recess on adhesive and planarized for high density interconnect packaging. The combination uses Alur’s technique to improve mechanical support, package flatness, high density routing, and manufacturability.
As to claim 5, the system of claim 4, wherein the substrate further comprises a milled portion having a surface beneath a top surface of the substrate, and wherein the one or more interconnect chips are bonded to the milled portion (Alur: 8:64:65. The recess/cavity is the claimed milled portion under BRI.).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Rigetti in view of Alur and in further view of US Patent No. 11,348,897 to Elsherbini et al. (“Elsherbini”).
The combination of Rigetti in view of Alur teach all the limitations of claims 1 and 3-5 from which claim 6 depends. The combination, however, does not explicitly teach the one or more interconnection chips are substantially coplanar with the top surface of the substrate.
Elsherbini teaches the top surface of the die is substantially coplanar with the top surface of the package substrate (11:39-41).
It would have been obvious to a PHOSTIA to combine the teachings of Rigetti in view of Alur and Elsherbini to apply Elsherbini’s coplanar packaging arrangement to the Rigetti architecture to provide a planar package surface that facilitates accurate registration of electrical contacts, improves reliable and robust interlayer/interconnect bonding, and supports high density routing in a predictable manner.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti in view of Alur and Elsherbini and in even further view of US Patent No. 7,042,318 to Barnes et al. (“Barnes”).
The combination of Rigetti, Alur and Elsherbini teach all the limitations of claims 1 and 3-6 from which claim 7 depends. The combination, however, does not teach the one or more cable connections comprise a soldered element.
Barnes teaches a coaxial interface to a planar transmission structure of a PCB is provided in a shielded edge launch connector, center pin of the shielded edge launch connector is soldered to a solder pad on the PCB, shielding incorporated in the shielded edge launch connector is soldered to ground areas on a surface of PCB (Abstract).
It would have been obvious to further modify the combination of Rigetti, Alur, and Elsherbini with Barnes to use Barnes’s coaxial edge launch soldered connection structure of Rigetti’s cable connectorization layer to provide a predictable microwave/RF cable-to-interposer transition with controlled impedance.
As to claim 8, the system of claim 7, wherein the soldered element is soldered directly to the one or more interconnect chips (Barnes: Abstract. Center pin soldered to solder pad on PCB, shielding soldered to PCB ground areas.).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Rigetti in view of US Pub. No. 2017/0186710 to Yoon et al. (“Yoon”).
Rigetti teaches the limitations of claim 1 from which claim 13 depends. Rigetti, however, does not teach one or more TSVs coupled to a ground plane from the one or more interconnect chips.
Yoon teaches a glass interposer having a signal layer on one side, a ground plane on the opposite side, and metalized through-glass vias extending through the interposer substrate between the signal layer and ground plane (¶ 0031).
It would have been obvious to a PHOSITA to modify Rigetti’s interposer-based quantum computing apparatus to include TSV coupled to a ground plane, as taught by Yoon. The modification provides a predictable RF/microwave packaging benefit of improved grounding, shielding, substrate mode control, reduced interference, and low loss signal routing in an interposer package.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Rigetti in view of US Pub. No. 2021/0296749 to Degraw et al. (“Degraw”).
Rigetti teaches the limitations of claim 1 from which claim 14 depends. Rigetti, however, does not teach the one or more cable connections are configured to receive a superconducting cable.
Degraw teaches metal connectors soldered to ends of Nb/Ti coaxial cables, connectors are attached to/receive Nb/Ti coaxial cable/wire, Nb/Ti coaxial cable becomes superconducting around 11k, and cable used in a qubit system as signal readout line (¶ 0048-0050).
It would have been obvious to a PHOSITA to configure Rigetti’s cable connections to receive a superconducting cable, as taught by Degraw, to improve microwave signal quality in the quantum readout/control path, reduce attenuation, reduce impedance mismatch, or avoid undesirable signal reflections in a superconducting quantum computing system.
Allowable Subject Matter
Claims 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10-12 would be allowable because the prior art of record does not teach or suggest a system having all the combinations of elements required by and recited in claim 10. Claims 11-12 depend from claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851
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