DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The amendments filed April 2, 2026 have been entered. Claims 1-20 remain pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 17, 2026 w is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Oshima (US 2016/0342463) in view of Sundararaman et al. (US 2016/0070652).
Regarding claim 1, Oshima teaches a device (Fig. 1, storage device 104), comprising:
a memory (Fig. 1, non-volatile semiconductor memory 112);
a host interface (Fig. 1, host interface 106) configured to receive, over a computer bus from a host (Fig. 1 depicts a bus communication between host system 102 and host interface 106), data access commands identifying first logical addresses specified in first storage spaces implemented using portions of the memory (“Front end 108 communicates with host system 102 to receive, organize, and forward commands and data from host system 102,” [0019] teaching that the front end 108 receives commands and data from host system 102, where Fig. 1 shows front end communicating with host interface, see also “To write data to NAND 112, host system 102 provides a write command, write data, and a logical address to front end 108 via host interface 106,” [0035] and “To read data from NAND 112, host system 102 provides a read command and a logical address to front end 108 via host interface 106,” [0036], providing example write and read commands with a logical address attached to the command to identify physical locations of the memory to write to/read from); and
a circuit (Fig. 1, back end 110, where [0033] provides hardware implementations for back end 110 teaching a circuit) configured to translate first logical addresses specified in first storage spaces implemented using portions of the memory into second logical addresses specified in a second storage space corresponding to a capacity of the memory (“Back end 110 includes multiple functional units, including … a logical-to-physical address translation unit 132” [0025], “For efficiency, it is advantageous for logical-to-physical translation unit 132 to use a logical address as an index to a single lookup table that encompasses all namespaces managed by SSD controller 105. However, the namespace-based addresses illustrated in FIG. 2 are not amenable for use in such a table,” [0040], “Thus, instead of using namespace-based addresses as indexes to logical-to-physical lookup tables, logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table. Within the linear address space that is associated with the linear, internal address, the namespaces are arrayed in a back-to-back manner, so that the linear addresses corresponding to one namespace are adjacent to the linear addresses corresponding to the subsequent namespace. This effectively converts the namespace-based address space into an address space that includes a single set of numbers that begin at 0 and increase to a maximum number,” [0041], see also Figs. 2 and 3, with Fig. 3 showing that the output of the conversion to the internal address is specifically a logical address, and the citations above showing that these are logical addresses in the namespace; regarding the second storage space corresponding to a capacity of the memory, see the internal address space in [0043] and Figs. 4 and 5 showing the entire logical address space of the NAND storage);
wherein the circuit is configured to divide the first logical addresses in the first storage spaces into first blocks (“The use of namespaces means that logical addresses provided by host system 102 to SSD controller 105 include a namespace identifier, which identifies a namespace (and can be, for example, a short sequence of bits), in addition to a logical block address, which identifies a logical block within that namespace,” [0038], teaching that the namespaces can be identified by block addresses, reading on the division of the first spaces and addresses into blocks, see also “The flow in the diagram begins with the host system 102 and ends with the back end 110 of the SSD controller 105. To access (read or write) particular data within storage device 104, host system 102 provides an LBA-based address 602 that includes a namespace identifier (“NSID”) and that specifies a logical block address (“LBA”) within the namespace associated with the NSID. The LBA specifies a particular block within the associated namespace. Note that because namespaces are independent logical subdivisions of storage for storage device 104, an LBA in one namespace points to a different location in NAND 112 than the same LBA in a different namespace,” [0051]).
Oshima fails to teach where the translation occurs based on a plurality of block sizes.
Sundararaman’s disclosure relates to a storage device and interface and as such comprises analogous art in the same field of endeavor of storage management.
As part of this disclosure, Sundararaman provides for a translation between IO namespaces to storage resources, where “The virtual blocks may be adapted to provide a desired storage granularity (e.g., block size),” [0070], with the ability to select different block sizes based on different factors, see [0099], and the example of [0153] showing different name spaces and storage resources with different block sizes, see also the Fig. 2B embodiment.
An obvious modification can be identified: providing flexibility to provide a desired block size for different virtual blocks and different underlying blocks, reading upon where a translation between virtual blocks and underlying blocks is based on a plurality of block sizes.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Sundararaman’s variable block size into Oshima’s system, as a flexible block size allows for the ability to account for different performance factors such as “memory overhead (e.g., larger virtual blocks 145 may result in a fewer number of entries in the forward map 125), garbage collection complexity, sequential storage performance of the storage resource(s) 190, I/O properties of the clients 106 (e.g., preferred client block size), and/or the like,” [0099].
Regarding claim 2, the combination of Oshima and Sundararaman teaches the device of claim 1, and Oshima further teaches wherein the first storage spaces include a namespace allocated from a storage capacity of the memory (see Fig. 2 showing name spaces allocated, where Figs. 3, 4, and 5 show how the namespace correlates to an internal linear addressing, where the linear internal addressing refers to the SSD’s internal address space, see [0043]).
Regarding claim 3, the combination of Oshima and Sundararaman teaches the device of claim 2, and Oshima further teaches wherein the second storage space includes the storage capacity (see the SSD internal address space in [0043], see also Figs. 4 and 5 showing the entire logical address space of the NAND storage).
Regarding claim 4, the combination of Oshima and Sundararaman teaches the device of claim 1, and the combination further teaches wherein the circuit is configured to divide, according to the plurality of block sizes, the first logical addresses in the first storage spaces into first blocks (“The use of namespaces means that logical addresses provided by host system 102 to SSD controller 105 include a namespace identifier, which identifies a namespace (and can be, for example, a short sequence of bits), in addition to a logical block address, which identifies a logical block within that namespace,” [0038], teaching that the namespaces can be identified by block addresses, reading on the division of the first spaces and addresses into blocks, see also “The flow in the diagram begins with the host system 102 and ends with the back end 110 of the SSD controller 105. To access (read or write) particular data within storage device 104, host system 102 provides an LBA-based address 602 that includes a namespace identifier (“NSID”) and that specifies a logical block address (“LBA”) within the namespace associated with the NSID. The LBA specifies a particular block within the associated namespace. Note that because namespaces are independent logical subdivisions of storage for storage device 104, an LBA in one namespace points to a different location in NAND 112 than the same LBA in a different namespace,” [0051]; regarding the according to the plurality of block sizes, as discussed in the claim 1 rationale, Sundararaman’s disclosure provides for translation between IO namespaces and storage resources, with the ability to translate it based on a desired storage granularity/block size and the ability to select different block sizes, reading on this limitation) and map the first blocks into second blocks in the second storage space (“Logical-to-physical translation unit 132 translates logical addresses, e.g., logical block addresses (LBAs), to physical addresses, e.g., physical block addresses, of non-volatile semiconductor memory 112 during reading or writing data,” [0028], “logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table,” [0041] teaching that the internal linear address space addresses are also provided as blocks).
Regarding claim 5, the combination of Oshima and Sundararaman teaches the device of claim 4, and Oshima further teaches wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces (as seen in Fig. 2, Oshima’s namespaces are ordered in a sequential manner, with each address being provided continuously within the respective namespace to provide for increasing offsets; this is also seen in Figs. 4 and 5).
Oshima fails to teach where fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space.
As seen in Oshima Figs. 4 and 5, Oshima’s internal linear address spaces provides for a sequential, continuous mapping from the namespace addresses to the linear address space.
As further provided in Sundararaman’s disclosure, in the Fig. 2B embodiment, the general address space 122 shows how discontinuous parts of the address space may be mapped to virtual blocks assigned to a given resource/namespace (see virtual blocks 145A being mapped arbitrarily within total address space with one arrow from the left side of the address space 122 and another arrow being mapped from close to the right side of the address space 122).
A further modification can be identified: incorporating Sundararaman’s disclosure of discontinuous mapping between an overall address space and the individual namespaces. Such a modification reads upon the limitation of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Sundararaman’s disclosure of discontinuous mapping between address spaces into Oshima’s disclosure, as this allows for flexibility to reuse parts of the logical address space as they are available instead of potentially having to shift data around in order to adjust boundaries of namespaces.
Regarding claim 6, the combination of Oshima and Sundararaman teaches the device of claim 5, and the combination further teaches wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks (as part of the incorporation of Sundararaman in the claim 4 rationale, Sundararaman [0153] provides for different block sizes while still providing for 2kb virtual blocks for the different LIDs, providing for a 2kb common size).
Regarding claim 7, the combination of Oshima and Sundararaman teaches the device of claim 6, and the combination further teaches wherein each of the first storage spaces is divided by no more than two block sizes (as shown in the claims 4 and 6 rationale, Sundararaman provides for different block size resources, where Fig 2B shows that each individual namespace 145A and 190A through 145N and 190N map different block sizes in 190A-190N onto the single common block size in 145A-145N, teaching that each of the namespaces utilizes both its own individual block size and the common size, with the following citations coming from Sundararaman);
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size (“In the FIG. 2B embodiment, the storage resource 190A may be configured with a block size of 1 kb, the storage resource 190B may have a block size of 2 kb, and the storage resource 190N may have a block size of 512 bytes. The translation module 124 may configure the LIDs to reference 2 kb blocks,” [0153], so each of the namespaces utilizes a smaller block size than the common block size); and
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size (“In the FIG. 2B embodiment, the storage resource 190A may be configured with a block size of 1 kb, the storage resource 190B may have a block size of 2 kb, and the storage resource 190N may have a block size of 512 bytes. The translation module 124 may configure the LIDs to reference 2 kb blocks,” [0153], each namespace utilizes one block size, i.e. no more than one block having a block size different from the common lock size).
Regarding claim 8, the combination of Oshima and Sundararaman teaches the device of claim 7, and Oshima further teaches wherein the circuit is configured at least in part via firmware (“In various embodiments, the functional blocks included in front end 108 and back end 110 represent hardware or combined software and hardware elements for performing associated functionality. Thus, any or all of the functional blocks may be embodied as firmware executing in a processing unit,” [0033]).
Regarding claim 9, the combination of Oshima and Sundararaman teaches the device of claim 7, and the combination further teaches wherein the circuit is configured to consolidate at least two of the first blocks into being mapped within a third block having the common block size in the second storage space (as discussed in the claim 7 rationale, incorporating the claims 4 and 6 rationale, Sundararaman’s disclosure provides for different block sizes for the different name spaces while providing for a larger common virtual block for the overall logical address space; in order to make this work, “The translation module 124 may configure the LIDs to reference 2 kb blocks, which may comprise mapping two virtual addresses 195A to each virtual block 145A, mapping one virtual address 195B to each virtual block 145B, mapping four virtual addresses 195N to each virtual block 145N, and so on,” [0153], teaching that smaller blocks are consolidated into blocks of the common size).
Regarding claim 10, Oshima teaches a method, comprising:
allocating a plurality of first storage spaces respectively from a plurality of portions of a memory of a device (Figs. 2, 4, 5, allocating namespaces from an internal logical address space of a storage device, see also Fig. 1 for the storage device));
receiving, in a host interface of the device over a computer bus from a host, data access commands identifying first logical addresses specified in the first storage spaces (“To write data to NAND 112, host system 102 provides a write command, write data, and a logical address to front end 108 via host interface 106,” [0035] and “To read data from NAND 112, host system 102 provides a read command and a logical address to front end 108 via host interface 106,” [0036], providing example write and read commands with a logical address attached to the command to identify physical locations of the memory to write to/read from);
translating, by the device, first logical addresses specified in the first storage spaces into second logical addresses specified in a second storage space defined in the memory (“Back end 110 includes multiple functional units, including … a logical-to-physical address translation unit 132” [0025], “For efficiency, it is advantageous for logical-to-physical translation unit 132 to use a logical address as an index to a single lookup table that encompasses all namespaces managed by SSD controller 105. However, the namespace-based addresses illustrated in FIG. 2 are not amenable for use in such a table,” [0040], “Thus, instead of using namespace-based addresses as indexes to logical-to-physical lookup tables, logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table. Within the linear address space that is associated with the linear, internal address, the namespaces are arrayed in a back-to-back manner, so that the linear addresses corresponding to one namespace are adjacent to the linear addresses corresponding to the subsequent namespace. This effectively converts the namespace-based address space into an address space that includes a single set of numbers that begin at 0 and increase to a maximum number,” [0041], see also Figs. 2 and 3, with Fig. 3 showing that the output of the conversion to the internal address is specifically a logical address, and the citations above showing that these are logical addresses in the namespace); and
dividing the first logical addresses in the first storage spaces into first blocks (“The use of namespaces means that logical addresses provided by host system 102 to SSD controller 105 include a namespace identifier, which identifies a namespace (and can be, for example, a short sequence of bits), in addition to a logical block address, which identifies a logical block within that namespace,” [0038], teaching that the namespaces can be identified by block addresses, reading on the division of the first spaces and addresses into blocks, see also “The flow in the diagram begins with the host system 102 and ends with the back end 110 of the SSD controller 105. To access (read or write) particular data within storage device 104, host system 102 provides an LBA-based address 602 that includes a namespace identifier (“NSID”) and that specifies a logical block address (“LBA”) within the namespace associated with the NSID. The LBA specifies a particular block within the associated namespace. Note that because namespaces are independent logical subdivisions of storage for storage device 104, an LBA in one namespace points to a different location in NAND 112 than the same LBA in a different namespace,” [0051]).
Oshima fails to teach where the translation occurs based on a plurality of block sizes.
Sundararaman’s disclosure relates to a storage device and interface and as such comprises analogous art in the same field of endeavor of storage management.
As part of this disclosure, Sundararaman provides for a translation between IO namespaces to storage resources, where “The virtual blocks may be adapted to provide a desired storage granularity (e.g., block size),” [0070], with the ability to select different block sizes based on different factors, see [0099], and the example of [0153] showing different name spaces and storage resources with different block sizes, see also the Fig. 2B embodiment.
An obvious modification can be identified: providing flexibility to provide a desired block size for different virtual blocks and different underlying blocks, reading upon where a translation between virtual blocks and underlying blocks is based on a plurality of block sizes.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Sundararaman’s variable block size into Oshima’s system, as a flexible block size allows for the ability to account for different performance factors such as “memory overhead (e.g., larger virtual blocks 145 may result in a fewer number of entries in the forward map 125), garbage collection complexity, sequential storage performance of the storage resource(s) 190, I/O properties of the clients 106 (e.g., preferred client block size), and/or the like,” [0099].
Claims 11, 12, 13, 14, 15, and 16 are rejected according to the rationale of claims 4, 5, 6, 7, 3 (incorporating the rejection to claim 2), and claim 9 respectively.
Regarding claim 17, Oshima teaches a non-transitory computer storage medium storing instructions which, when executed by a device having a memory, cause the device to perform a method (“One embodiment disclosed herein provides A non-transitory computer readable medium. The non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform a method”, [0007]) identical to the method of claim 10 (with the exception that the last limitation of claim 10 is no longer recited in claim 17) and rejected according to the same rationale.
Claims 18, 19, and 20 are rejected according to the rationale of claims 11, 13 (incorporating the rejection to claim 12), and claim 9 (incorporating the rejection to claim 7) respectively.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 19/022,041 in view of Oshima and Sundararaman.
As seen in the table below, the majority of limitations are disclosed in the copending claims, with the difference in claim limitations to be discussed after. For clarity of record, only a comparison of claims 1-9 are shown, as claims 10-20 will feature similar analysis, just with different statutory categories.
Claim 1, instant application
Claim 1, co-pending 19/022,041
A device, comprising:
a memory;
a host interface configured to receive, over a computer bus from a host, data access commands identifying first logical addresses specified in first storage spaces implemented using portions of the memory; and
a circuit configured to translate, based on a plurality of block sizes, the first logical addresses specified in the first storage spaces implemented using the portions of the memory into second logical addresses specified in a second storage space corresponding to a capacity of the memory;
wherein the circuit is configured to divide the first logical addresses in the first storage spaces into first blocks.
A device, comprising:
a memory; and
a circuit configured to translate first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory.
Claim 2, instant application
Claim 2, co-pending 19/022,041
The device of claim 1, wherein the first storage spaces include a namespace allocated from a storage capacity of the memory.
The device of claim 1, wherein the first storage spaces include a namespace allocated from a storage capacity of the memory.
Claim 3, instant application
Claim 3, co-pending 19/022,041
The device of claim 2, wherein the second storage space includes the storage capacity.
The device of claim 2, wherein the second storage space includes the storage capacity.
Claim 4, instant application
Claim 4, co-pending 19/022,041
The device of claim 1, wherein the circuit is configured to divide, according to the plurality of block sizes, the first logical addresses in the first storage spaces into the first blocks and map the first blocks into second blocks in the second storage space.
The device of claim 1, wherein the circuit is configured to divide, according to a plurality of block sizes, the first logical addresses in the first storage spaces into first blocks and map the first blocks into second blocks in the second storage space.
Claim 5, instant application
Claim 5, co-pending 19/022,041
The device of claim 4, wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space.
The device of claim 4, wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space.
Claim 6, instant application
Claim 6, co-pending 19/022,041
The device of claim 5, wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.
The device of claim 5, wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.
Claim 7, instant application
Claim 7, co-pending 19/022,041
The device of claim 6, wherein each of the first storage spaces is divided by no more than two block sizes;
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size; and
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size.
The device of claim 6, wherein each of the first storage spaces is divided by no more than two block sizes;
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size; and
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size.
Claim 8, instant application
Claim 8, co-pending 19/022,041
The device of claim 7, wherein the circuit is configured at least in part via firmware.
The device of claim 7, wherein the circuit is configured at least in part via firmware.
Claim 9, instant application
Claim 9, co-pending 19/022,041
The device of claim 7, wherein the circuit is configured to consolidate at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.
The device of claim 7, wherein the circuit is configured to consolidate at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.
As seen above, co-pending claim 1 is unable to teach the host interface, the wherein limitation, and where the circuit is configured to translate the addresses based on a plurality of block sizes.
As seen in the obviousness rejection under 35 U.S.C. 103 above, Oshima discloses the host interface limitation in its entirety and the wherein clause in its entirety.
An obvious modification can be identified: incorporating Oshima’s teaching of a host interface and providing namespaces with LBA-based addressing into the co-pending claimed invention. Such a modification reads upon the host interface limitation and the wherein clause.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Oshima into the claimed invention, as the host interface allows for the communication between host system and memory device, which is necessary for operation, and the namespace/LBA-based addressing allows for the host to provide different workloads to different namespaces/the different logical subdivisions and blocks allows for a user to have greater control over how the memory system is divided for use.
As noted in the obviousness rejection, Oshima fails to teach where the translation occurs based on a plurality of block sizes, so the combination fails to teach this feature.
This feature is taught by Sundararaman as shown in the obviousness rejection, and the rationale and motivation for incorporating Sundararaman’s teaching are incorporated here.
This is a provisional nonstatutory double patenting rejection as neither set of claims are patented yet.
Response to Arguments
Applicant's arguments filed April 2, 2026 have been fully considered but they are not persuasive.
The arguments focus on examiner’s response to arguments provided in the prior office action mailed January 2, 2026, focusing again on Sundararaman’s intermediate translation layer’s inability to be combined with Oshima’s disclosure. Applicant has now shifted the argument to focus on how Sundararaman’s disclosure provides for address translation layer and FTL’s within a given solid-state storage medium, arguing how Sundararaman already having a FTL points to an inability to incorporate the intermediate translation layer’s functionality into Oshima’s solid state drive. However, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The obviousness rationale presents how it is the functionality of Sundararaman’s intermediate translation layer can be incorporated into Oshima’s system, with the improvement suggestions focusing on performance factors that are not solely dependent on the storage resources. This line of argumentation is unpersuasive.
Conclusion
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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