DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: MICROELECTRONIC STRUCTURE COMPRISING LOGIC DEVICE AND PASSIVE DEVICE WITH THINNER SI LAYER
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: a reference # 172 in Figs. 17-18 are not mentioned in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7-9, 14-15, and 18-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2024/0332185 A1; hereinafter “Kim”).
Regarding claim 1, Kim teaches a microelectronic structure comprising: a logic device (101) (paragraphs 13 and 18); and a passive device (102) (paragraphs 13 and 23-26), wherein the passive device includes: a doped substrate (112 including 118) (Fig. 2 and paragraphs 25-26); a silicide layer (a silicide layer, not shown in Fig. 2, formed on and in contact with an upper surface of 162 in 102) located on a backside surface of the doped substrate (112L) (Fig. 2 and paragraph 38); and a metal plane (170) located on a backside surface of the silicide layer (Fig. 2 and paragraphs 15 and 40).
Regarding claim 2, Kim teaches wherein the doped substrate has a height/depth in the range of about 20 to 50 nm (112 having a thickness of 50 nm) (paragraph 16).
Regarding claim 7, Kim teaches wherein the passive device is a diode (paragraph 26).
Regarding claim 8, Kim teaches a microelectronic structure comprising: a logic device (101) that includes a backside contact (162_1 or a combination of 162_1 and a portion of 170 in 101) (paragraphs 13 and 18, and 36-39); and a passive device (102) (paragraphs 13 and 23-26), wherein the passive device includes: a doped substrate (112 including 118) (Fig. 2 and paragraphs 25-26); a silicide layer (a silicide layer, not shown in Fig. 2, formed on and in contact with an upper surface of 162 in 102) located on a backside surface of the doped substrate (112L) (Fig. 2 and paragraph 38); and a metal plane (170) located on a backside surface of the silicide layer (Fig. 2 and paragraphs 15 and 40).
Regarding claim 9, Kim teaches wherein the doped substrate has a height/depth in the range of about 20 to 50 nm (112 having a thickness of 50 nm) (paragraph 16).
Regarding claim 14, Kim teaches wherein the logic device further comprises: a source/drain (126_2) (Fig. 2 and paragraph 18); and a second silicide layer (a silicide layer, not shown in Fig. 2, formed on and in contact with an upper surface of 162 in 101) located on the backside surface of the source/drain (Fig. 2 and paragraph 38).
Regarding claim 15, Kim teaches wherein the backside contact is connected to a backside surface of the second silicide layer (Fig. 2).
Regarding claim 18, Kim teaches wherein a backside surface of the backside contact of the logic device (the combination of 162_1 and the portion of 170 in 101) is substantially uniform/planar with the backside surface of the metal plane of the passive device (Fig. 2).
Regarding claim 19, Kim teaches wherein the passive device is a diode (paragraph 26).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Harrison et al. (US 2012/0007244 A1; hereinafter “Harrison”).
Regarding claim 20, Kim teaches a method comprising: forming a logic device (101) that includes a backside contact (162_1) (paragraphs 13 and 18, and 36-39); and forming a passive device (102) (paragraphs 13 and 23-26), wherein the passive device includes: a doped substrate (112 including 118) (Fig. 2 and paragraphs 25-26); a silicide layer (a silicide layer, not shown in Fig. 2, formed on and in contact with an upper surface of 162 in 102) located on a backside surface of the doped substrate (112L) (Fig. 2 and paragraph 38); and a metal plane (170) located on a backside surface of the silicide layer (Fig. 2 and paragraphs 15 and 40), wherein a height/depth of the doped substrate is about 50 nm (112 having a thickness of 50 nm) (paragraph 16).
Kim does not explicitly teach that a combined height/depth of the doped substrate, the silicide layer, and the metal plane is in the range of about 30 to 80 nm since Kim does not teach a thickness for the silicide layer and a thickness for the metal plane in numerical values. Harrison teaches a microelectronic structure (a semiconductor device including transistors as active/logic devices and resistors or capacitors as passive devices) (Fig. 1a and paragraphs 21-22) comprising: a silicide layer (405) on a backside surface of a substrate (203 of 200) and a metal plane (400) on a backside surface of the silicide layer, wherein a thickness of the silicide layer is about 2 nm and a thickness of the metal plane is about 10 nm as adjusting thicknesses involves a routine experimentation in the art (Figs. 1a-1b and paragraphs 25-28). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kim with that of Harrison for obtaining the desired thickness values for the silicide layer and the metal plane through the routine experimentation in the art. It is also noted that the combined height/depth of the doped substrate, the silicide layer, and the metal plane would be in the range of about 30 to 80 nm (Kim, 112 having the thickness of 50 nm and Harrison, 405 having the thickness of 2 nm and 400 having the thickness of 10 nm, resulting 62 nm total).
Claims 3-6 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 1 and 8 above, and further in view of Harrison.
Regarding claim 3-4 and 10-11, Kim does not explicitly teach that a combined height/depth of the silicide layer and the metal plane is in the range of about 10 to 300 nm (claims 3 and 10) and a combined height/depth of the doped substrate, the silicide layer, and the metal plane is in the range of about 30 to 80 nm (claims 4 and 11) since Kim does not teach a thickness for the silicide layer and a thickness for the metal plane in numerical values. Harrison teaches a microelectronic structure (a semiconductor device including transistors as active/logic devices and resistors or capacitors as passive devices) (Fig. 1a and paragraphs 21-22) comprising: a silicide layer (405) on a backside surface of a substrate (203 of 200) and a metal plane (400) on a backside surface of the silicide layer, wherein a thickness of the silicide layer is about 2 nm and a thickness of the metal plane is about 10 nm as adjusting thicknesses involves a routine experimentation in the art (Figs. 1a-1b and paragraphs 25-28). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kim with that of Harrison for obtaining the desired thickness values for the silicide layer and the metal plane through the routine experimentation in the art. For claims 6 and 11, It is also noted that the combined height/depth of the doped substrate, the silicide layer, and the metal plane would be in the range of about 30 to 80 nm (Kim, 112 having the thickness of 50 nm and Harrison, 405 having the thickness of 2 nm and 400 having the thickness of 10 nm, resulting 62 nm total).
Regarding claims 5 and 12, Kim teaches wherein the silicide layer forms a single uniform layer across the backside surface of the doped substrate (a single uniform layer of the silicide layer across 112L) (paragraph 38), and wherein the metal plane forms a single uniform layer across the backside surface of the silicide layer (Fig. 2).
Regarding claims 6 and 13, Kim teaches wherein the silicide layer and the metal plane increases the current flow through the doped substrate (Fig. 2, the silicide structure between the metal and semiconductor layer is known to improve electrical performance (i.e., a current flow between the metal and the semiconductor layer)).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claim 16, while Kim does not explicitly teach that the backside contact has a height/depth in the range of about 30 to 80 nm, it would have been obvious to one of ordinary skill in the art to adjust the thickness of the backside contact in a desired value, including the claimed value of about 30 to 80 nm, through a routine experimentation in the art.
Regarding claim 17, Kim teaches wherein the backside contact has a height/depth is substantially equal to the combined height/depth of the doped substrate, the silicide layer, and the metal plane (a thickness of 162_1 in 101 is substantially equal to the combined thickness of 112, 162_2 and the silicide layer between 112 and 162_2 in 102) (Fig. 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893