DETAILED ACTION
This Office Action is in response to Application filed 09 June 2023.
Claims 1-20 are pending. The claims have been considered and examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claims 1-3 be found allowable, claims 18-20 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4, 12, 15, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the DTS” in lines 14 and 16. There is insufficient antecedent basis for this limitation in the claim. Claim 1 previously cites a first DTS and a second DTS, it is believed that “the DTS” on line 14 should read “the first DTS” and “the DTS” on line 16 should read “the second DTS”. The claim will be interpreted as such for the purposes of further examination.
Claim 4 recites the limitation “the DTS” in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 1 previously cites a first DTS and a second DTS, it is believed that “the DTS” on line 3 of claim 4 should read “the second DTS”. The claim will be interpreted as such for the purposes of further examination.
Claim 12 recites the limitation “the DTS” in lines 10 and 12. There is insufficient antecedent basis for this limitation in the claim. Claim 12 previously cites a first DTS and a second DTS, it is believed that “the DTS” on line 10 should read “the first DTS” and “the DTS” on line 12 should read “the second DTS”. The claim will be interpreted as such for the purposes of further examination.
Claim 15 recites the limitation "the DTS" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 12 previously cites a first DTS and a second DTS, it is believed that “the DTS” on line 3 of claim 15 should read “the second DTS”. The claim will be interpreted as such for the purposes of further examination.
Claim 18 recites the limitation "the DTS" in lines 14 and 16. There is insufficient antecedent basis for this limitation in the claim. Claim 18 previously cites a first DTS and a second DTS, it is believed that “the DTS” on line 14 should read “the first DTS” and “the DTS” on line 16 should read “the second DTS”. The claim will be interpreted as such for the purposes of further examination.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 12-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to “logic”. As per claims 12-17, the claimed system has been read in view of applicant’s specification (see paragraph 0035). The claimed apparatus appears to include elements which could be interpreted as including only software. Software is not one of the four categories of invention and therefore these claims are not statutory. Software is not a series of steps or acts and thus is not a process. Software is not a physical article or object and as such is not a machine or manufacture. Software is not a combination of substances and therefore not a composition of matter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-14, 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peattie et al., U.S. Patent 11,442,844, hereinafter referred to as “Peattie”.
Referring to claim 1, Peattie discloses a system for debugging integrated circuits (See Col. 1, lines 34-45). - An electronic system comprising:
Peattie discloses an integrated circuit for debugging (See Col. 1, lines 34-45). - a platform that includes a component;
Peattie discloses a debug hub connected to debug cores (See Col. 4, lines 8- 15 and Col. 4, lines 8-21). Peattie discloses switch connected to high-speed interfaces (See Col. 4, lines 22-37). - one or more ports to communicatively couple with a first debug and test system (DTS) and a second DTS; and
Peattie discloses a debug hub and debug packet controller between the debug cores and the high-speed interfaces (See Col. 5, lines 13-21 and Col. 4, line 48 to Col. 5, line 3). - logic communicatively positioned between the component and the one or more ports, wherein the logic is configured to:
Peattie discloses determining the target debug core based on the address specified by the debug command and debug commands having packet headers (See Col. 7, lines 9-20, Col. 8, lines 59-67). - identify, based on a header of a first packet, that the first packet is related to a first debug process of the component, wherein the first debug process is performed by the first DTS;
Peattie discloses determining the target debug core based on the address specified by the debug command and debug commands having packet headers (See Col. 7, lines 9-20, Col. 8, lines 59-67). Peattie discloses multiple debug cores, thus target debug core can be a second debug core (See Col. 3, lines 8-15). - identify, based on a header of a second packet, that the second packet is related to a second debug process of the component, wherein the second debug process is performed by the second DTS;
Peattie discloses routing the debug command to a selected debug core (See Col. 5, lines 40-52). - route, based on the identification that the first packet is related to the first debug process, the first packet between the component and the DTS; and
Peattie discloses routing the debug command to a selected debug core (See Col. 5, lines 40-52). Peattie discloses multiple debug cores, thus target debug core can be a second debug core (See Col. 3, lines 8-15). - route, based on the identification that the second packet is related to the second debug process, the second packet between the component and the DTS.
Referring to claim 2, Peattie discloses the debug commands can be writes and reads (See Col. 4, lines 8-21). - The electronic system of claim 1, wherein the first packet is related to a read operation or a write operation of the component performed by the first DTS.
Referring to claim 3, Peattie discloses performing simultaneous write and read commands (See Col. 7, line 64 to Col. 8, line 12). Peattie discloses multiple debug cores, thus two debug processes can overlap (See Col. 3, lines 8-15). - The electronic system of claim 1, wherein the first debug process and the second debug process at least partially overlap in time.
Referring to claim 5, Peattie discloses control signals of registers are used to select transmitting debug commands to debug cores (See Col. 8, lines 24-39). - The electronic system of claim 1, wherein the logic is configured to route the first packet or the second packet based on pre-defined entries in a register set that is related to debug processes of the electronic system that may be performed by a plurality of DTSs.
Referring to claim 6, Peattie discloses a network that wired, such as LAN (See Col. 20, line 54 to Col. 21, line 7). - The electronic system of claim 1, wherein the first DTS is physically coupled with the platform.
Referring to claim 7, Peattie discloses a network that includes wireless network (See Col. 20, line 54 to Col. 21, line 7). - The electronic system of claim 1, wherein the first DTS is wirelessly coupled with the platform.
Referring to claim 8, Peattie discloses determining the target debug core based on the address specified by the debug command and debug commands having packet headers (See Col. 7, lines 9-20, Col. 8, lines 59-67). - The electronic system of claim 1, wherein the logic is configured to identify that the first packet is related to the first debug process of the component based on an identifier in the header of the first packet, wherein the identifier is related to the first DTS.
Referring to claim 9, Peattie discloses a debug hub and debug packet controller between the debug cores and the high-speed interfaces (See Col. 5, lines 13-21 and Col. 4, line 48 to Col. 5, line 3). Peattie discloses the debug hub connects to different debug cores (See Col1, lines 34-45). - The electronic system of claim 1, wherein the logic is a first logic, and wherein the component includes a second logic that is configured to manage different debug regions of the component.
Referring to claim 10, Peattie discloses using virtual addresses for each debug core (See Col. 7, lines 21-31). - The electronic system of claim 1, wherein the logic is a first logic, and wherein the component includes a second logic that is configured to virtualize a debug instances.
Referring to claim 11, Peattie discloses including using a high speed seriali interface (See Col. 3, lines 54-62). - The electronic system of claim 1, wherein the logic is a first logic, and wherein the component includes a second logic that is configured to serialize debug instances.
Claims 12-14, 16, and 17 are rejected for similar reasons as claims 1-3, 5 and 8, respectively, see above rejections. Additionally, Peattie discloses program instructions causing a processor to carry out the inventive arrangements (See Col. 20, line 54 to Col. 21, line 7).
Claims 18-20 are rejected for similar reasons as claims 1-3, respectively, see above rejections.
Allowable Subject Matter
Claim(s) 4 and 15 is/are objected to as being dependent upon a rejected base claim, but would be allowable, over the prior art, if rewritten in independent form including all of the limitations of the base claim and any intervening claims; and if any other above applicable 112 and 101 rejections are also overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent App. Pub. 2026/0081861 to Eder et al.
- Debugging using packet based network protocol
U.S. Patent App. Pub. 2021/0389371 to Liew et al.
- Debug data communication system for multiple chips
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D MANOSKEY whose telephone number is (571)272-3648. The examiner can normally be reached M-F 7:30am to 3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH D MANOSKEY/Primary Examiner, Art Unit 2113 August 17, 2026
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