DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f) unless otherwise noted in this application.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1:
Claim 1 recites, “reading the first test data with a second speed clock… and… writing second test data into the rewritable non-volatile memory module with the second speed clock”. However, the specification only ever discloses reading test data with a high-speed clock and writing data to the rewritable non-volatile memory module with a high-speed clock [0053], but does not recite writing data to the rewritable non-volatile memory module with the high-speed clock. Accordingly, the disclosure does not disclose with the specificity now claimed that the two high-speed clocks are the same clocks. For example, I can ride a bike at “high speed” at 20 mph, and drive at “high speed” at 70 mph. Although both may be referred to as “high speed” in each of their contexts, neither speed is the same. Therefore, what is “high speed” for writing may not be the same as what is “high speed” for reading. The disclosure does not indicate the two “high speeds” are the same, nor does not provide enough details to ascertain whether the context requires that they are the same. Accordingly, the claimed subject matter is regarded as new matter.
Regarding claims 8 and 15:
Claims 8 and 15 are rejected for reasons analogous to those indicated for claim 1 for reciting analogous limitations.
Regarding claims 2-7, 9-14 and 16-21:
Claims 2-7, 9-14 and 16-21 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-21 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2024/0257848 A1 (Ku) in view of US Patent No. US 11,398,288 B1 (Reusswig) in further view of US Patent No. US 10,971,215 B1 (Yang) in further view of US Patent Application Publication No. US 2021/0081109 A1 (Wang) in further view of US Patent Application Publication No. US 2019/0129818 A1 (Kannan).
Regarding claim 1 and analogous claims 8 and 15:
Ku teaches a memory control circuit unit ((400) [Fig .3]) configured to control a rewritable non-volatile memory module (the memory controller is for controlling the memory connected to the memory interface (460), such as non-volatile memory devices (140) [0038] [0081] [Fig. 1] [Fig. 3]), the memory control circuit unit comprising: a host interface configured to be coupled to a host system (host I/F (440), which couples the memory device to an external host [0076] [0080] [Fig. 3]); a memory interface (460) configured to be coupled to the rewritable non-volatile memory module (140)); and a memory management circuit (training control circuit (430), buffer memory (420), ECC engine (450), and processor (410)) coupled to the host interface (440) and the memory interface (460) (coupled through the bus [Fig. 3]), wherein the memory management circuit is configured to: activate an interface parameter updating operation (discloses that a training operation may be performed in response to the memory controller detecting a change in the operating environment of the memory system, such as a change in temperature [0157-0158]. The interface may an ONFI interface [0081]) and update at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module during the interface parameter updating operation (by teaching that the training control circuit can perform training on the memory package and set training values on the plurality of memory devices (140) [0078], where the training includes setting the different delays for the different memory regions of the memory devices (140) in an address-delay map (ADM) [0043-0045]. The delays allows the memory devices (140) to be accessed with optimal phase differences between the data signal (DQ) and the data strobe signal (DQS) [0116-0122] [0142] [0148-0151]. The training involves storing training data TDAT into the memory device and then reading out the read training data RDAT from the memory device. The data are then compared to determine pass/fail maps [0045] [0078] [0135] [0148-0158]), wherein the at least one interface parameter affects sampling quality of data transmitted between the memory interface and the rewritable non-volatile memory module (by teaching that the delay values affect the valid windows representing pass regions of the transmitted data (affects sampling quality of data transmitted) [0010] [0051] [0142-0145] [0010]).
Ku does not explicitly disclose, but Reusswig teaches the interface training operation comprising writing first test data into the rewritable non-volatile memory module with a first interface speed and then reading the first test data with a second interface speed having a speed higher than that of the first interface speed to determine a read window size of a DQ signal, and after the read window size is determined, writing second test data into the rewritable non-volatile memory module with the second interface speed to obtain a write window size of the DQ signal (by teaching that an interface training operation involves setting the read speed to slow (704) (first interface speed) for a write operation and setting the interface write parameters (706) [Col 15: lines 17-60]. The interface may be a ONFI interface [Col 4: lines 55-58] [Col 7: lines 1-3] [Col 8: lines 37-44]). Next, transferring the data pattern to a buffer of the storage medium (104) (708) [Col 15: lines 45-67]. The storage medium includes non-volatile NAND flash memory cells [Col 4: lines 44-84]. Then, setting the write speed to fast (710) (second interface speed) and setting the read parameters (712) [Col 16: lines 1-14]. Next, transferring the data to a buffer and then comparing the buffers for errors and determining an optimal read window size based on testing a plurality of parameter sets and determining the middle of the window in the parameter sets where errors occurred and did not occur (716) [Fig. 6] [Fig. 7] [Col 16: line 15 – Col 17: line 5]. After the read parameters are trained, the write parameters may also be trained. Training the write parameters after the read parameters allows testing the write parameters to be performed by reading the write data quickly with the parameters determined during the previous IFT read operations [Col 19: lines 38-52]. The write parameters may be trained at a fast interface write speed (i.e., second interface speed) [Col 19: line 65 – Col 20: line 5]. The write parameters are trained until an optimal write window size is determined based on a plurality of parameter sets tested where errors occurred and did not occur and selecting the parameter set in the middle of the window with no errors [Col 21: lines 7-41] [Fig. 6]. The system tests for errors of the read and written data, which are transmitted on the DQ lines, and accordingly, the valid data windows as reflected by the error counts reflect the read and write window sizes of the DQ signals [Fig. 6] [Col 9: lines 7-22] [Col 11: lines 60-67]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the writing of data with a double data rate interface during the interface parameter updating operation including writing the test data to determine appropriate delays as taught by Ku to include determining read parameters by writing the test data with a slow speed by using a slow interface speed as taught by Reusswig and then reading the test data back with a high speed by using a high interface speed to determine an optimal read data window as taught by Reusswig, and afterward, determining write parameters that obtain an optimal write data window by writing test data with a fast interface speed and reading it back with the previously determined read parameters as taught by Reusswig.
One of ordinary skill in the art would have been motivated to make this modification because it would have allowed the system to ensure the test data was written without errors and determine a read window to appropriately set the read parameters as taught by Reusswig in [Col 15: lines 17-33], furthermore, training the write parameters after the read parameters would allow the system to determine a write window to appropriately set the write parameters at a faster speed by using the previously determined read parameters to read the write test data written during the test as taught by Reusswig in [Col 19: lines 45-52] [Col 21: lines 23-41].
Reusswig does not explicitly disclose that high or low speed data transfer rate is controlled with a high or low speed clock of the interface, but Yang teaches that high or low speed data transfer rate is effected with a high or low speed clock of the interface (by teaching that setting the transfer speed to slow involves setting the interface clock of an ONFI interface to a slower speed [Yang, Fig. 3], which causes a reduction in transfer errors due to a larger data eye [Yang, Fig. 3] [Yang, Col 6: lines 14-22] [Yang, Col 12: line 10 – Col 13: line 40], and setting the transfer speed to high speed involves setting the interface clock of the ONFI interface to a higher speed [Yang, Fig. 3], which causes an increase in transfer errors or a reduction in signal integrity due to a smaller data eye, but a higher data transfer speed [Yang, Fig. 3] [Yang, Col 6: lines 14-22] [Yang, Col 12: line 10 – Col 13: line 40]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the use of the ONFI interface to write and read test data with different transfer speeds as taught by Ku in view of Reusswig to include controlling the transfer speeds with the frequency of the interface clock as taught by Yang because it would have only required the combination of known elements according to known methods to yield predictable results. Ku in view of Reusswig contemplate an ONFI NAND flash interface and controlling the transfer speed to high and low speeds to transfer data for read and write operations of test data respectively, however, they do not disclose a mechanism for controlling the data transfer speeds for those operations. Yang also contemplates an ONFI NAND flash interface and teaches that controlling the data transfer speed may be accomplished with selection of an interface clock speed. Accordingly, one of ordinary skill in the art could have combined the mechanism of controlling the transfer speed with the interface clock speed as taught by Yang to control the transfer speeds of the different read and write operations as taught by Ku in view of Reusswig according to known methods and the results would have been predictable (both Yang and Reusswig appreciate the same relationship between transfer speed and errors/signal integrity). Furthermore, in combination, each element would continue to perform the same function that it did separately. Accordingly, it would have been obvious to one of ordinary skill in the art.
Ku discloses that the training operation may be performed in response to changes in the operating environment of the memory system, including temperature changes, but does not explicitly disclose that the memory management circuit is configured to: detect system status; activate an interface parameter updating operation in response to the system status meeting a target condition. However, Wang teaches that the memory management circuit (CPU (12) and temperature sensor (15) [Fig. 1]) is configured to: detect system status (the temperature sensor can measure a temperature (detect system status) of the SSD [0049] [Fig. 1]); activate an interface parameter updating operation in response to the system status meeting a target condition (by teaching that when the temperature acquired from the temperature sensor changes by a threshold amount or more (system status meeting a target condition), the PHY parameter control unit (123) acquires a new PHY parameter set corresponding to the current temperature from the PHY parameter table (22) and sets the PHY parameter set in the NAND PHY (131) [0095] [0101] [Fig. 10]. The PHY parameters are based on a variety of trainings and calibrations [0058]. The PHY parameters may be loaded rather than performing a new calibration and training for each change in temperature [0005-0006] [0053-0055]. There is one PHY parameter table (22) per NAND flash memory chip (5) connected to each channel (Ch). The parameters define parameters used to adjust the timing at which the signal is sent between the controller (4) (through the NAND interface (13)) and the NAND flash memory (5) [0036]. The parameters include parameters to cause a phase shift between the DQ and DQS signals so that they have an appropriate delay for each temperature [0060-0063] [Fig. 2]. A duty cycle adjustment (DCA) may also be performed for each temperature to obtain a duty setting value [0064-0067] [Fig. 3]. Transmission timings may be set based on a read training, with a delay for each temperature [0068] [Fig. 4]. Bit skew may also be adjusted [0069] [Fig. 5]. The effect of the read training and bit skew adjustment is that wide valid data windows are obtained [0071]. The read training and bit skew adjustment also center the sampling time in the middle of the valid data window [0073-0075] [Fig. 6]. Write training is also performed analogous to the read training [0076-0084] [Figs. 7-8]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the adjustment of the parameters based on a change in temperature as taught by Ku to include the CPU determining a change in temperature of the SSD based on a measurement from the temperature sensor, and reading a loading a corresponding parameter set that corresponds to the temperature settings for each chip of a NAND flash on each channel rather than performing a new calibration and training for each detected change in temperature as taught by Wang.
One of ordinary skill in the art would have been motivated to make this modification because loading the parameters from a table based on temperature allows the parameters to be updated without unnecessary calibration and training, which allows continuous access to the NAND flash memory as taught by Wang in [0055].
Ku does not explicitly disclose, but Kannan teaches, wherein the system status reflects at least one of error status of data read from the rewritable non-volatile memory module, clock status of the memory control unit, and data storage status of the rewritable non-volatile memory module (by teaching that the flash controller can be equipped with a flash age tracker (602), which monitors various aspects of the flash memories on a per-channel basis. The channels include a timer (604) (clock), an error tracker (606), a read tracker (608), and a write tracker (610). The error tracker (606) can keep track of degradation in the data that is read from the flash memory devices of that channel (215). In this way, depending on the errors tracked by the error tracker (system status reflects at least one of error status of data read from the rewritable non-volatile memory module), the time (clock status), the number of reads or writes (the data storage status of the rewritable non-volatile memory module), or other stimulus, the microcode sequence engine (213) could determine that an adjustment should be made to the frequency of operation, signal timing, signal voltages, or one or more of the signals generated by the software calibrated I/O module (223) [0186-0187], which includes shifting the edges (timing) of signals to determining the shape of the waveform, as well as clock the frequency of the signals and voltage [0185] [Fig. 6] [Fig. 7]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory management unit that detects system status such as temperature to trigger a training operation on the interface signals as taught by Ku in view of Wang to additionally include tracking an error rate, as well as read and write statuses to determine when to initiate a training/calibration operation of the interface signals as taught by Kannan.
One of ordinary skill in the art would have been motivated to make this modification because flash memory device characteristics may change over the lifespan of the flash memory die, which can degrade the performance of the storage system, accordingly, recalibrating based on metrics tracked by the flash age tracker can compensate for not only short term environmental conditions such as temperature variation, power supply variation, and noise, but also as a result of device wear arising from cumulative reads, writes, and erasure cycles as taught by Kannan in [0001] [0172] [00186-0087].
Regarding claim 2 and analogous claims 9 and 16:
The memory control circuit unit according to claim 1 is made obvious by Ku in view of Reusswig in further view of Yang in further view of Wang in further view of Kannan (Ku-Reusswig-Yang-Wang-Kannan.
Ku teaches that there may be a temperature sensor and does not explicitly disclose, but Wang teaches wherein the system status further system temperature status (by teaching that when the temperature acquired from the temperature sensor changes by a threshold amount or more (system status further reflects at least one of a system temperature status), the PHY parameter control unit (123) acquires a new PHY parameter set corresponding to the current temperature from the PHY parameter table (22) and sets the PHY parameter set in the NAND PHY (131) [0095] [0101] [Fig. 10]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the adjustment of the parameters based on a change in temperature as taught by Ku to include the CPU determining a change in temperature of the SSD based on a measurement from the temperature sensor, and reading a loading a corresponding parameter set that corresponds to the temperature settings for each chip of a NAND flash on each channel rather than performing a new calibration and training for each detected change in temperature as taught by Wang.
One of ordinary skill in the art would have been motivated to make this modification because loading the parameters from a table based on temperature allows the parameters to be updated without unnecessary calibration and training, which allows continuous access to the NAND flash memory as taught by Wang in [0055].
Regarding claim 3 and analogous claims 10 and 17:
The memory control circuit unit according to claim 2 is made obvious by Ku-Reusswig-Yang-Wang-Kannan.
Ku teaches that there may be a temperature sensor and does not explicitly disclose, but Wang teaches wherein the memory management circuit is further configured to: determine that the system status meets the target condition in response to at least one of a bit error rate of the data read from the rewritable non-volatile memory module exceeding a first threshold, a total number of error bits included in the data read from the rewritable non-volatile memory module exceeding a second threshold, the data read from the rewritable non-volatile memory module including an uncorrectable error, a clock frequency of the memory control circuit unit changing, system temperature changing, and a data storage amount of the rewritable non-volatile memory module reaching a third threshold (by teaching that when the temperature acquired from the temperature sensor changes by a threshold amount or more (the system status meets the target condition in response to the system temperature changing), the PHY parameter control unit (123) acquires a new PHY parameter set corresponding to the current temperature from the PHY parameter table (22) and sets the PHY parameter set in the NAND PHY (131) [0095] [0101] [Fig. 10]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the adjustment of the parameters based on a change in temperature as taught by Ku to include the CPU determining a change in temperature of the SSD based on a measurement from the temperature sensor, and reading a loading a corresponding parameter set that corresponds to the temperature settings for each chip of a NAND flash on each channel rather than performing a new calibration and training for each detected change in temperature as taught by Wang.
One of ordinary skill in the art would have been motivated to make this modification because loading the parameters from a table based on temperature allows the parameters to be updated without unnecessary calibration and training, which allows continuous access to the NAND flash memory as taught by Wang in [0055].
Regarding claim 4 and analogous claims 11 and 18:
The memory control circuit unit according to claim 1 is made obvious by Ku-Reusswig-Yang-Wang-Kannan.
Ku further discloses wherein the at least one interface parameter further affects at least one of a delay amount of a DQ signal transmitted between the memory interface and the rewritable non-volatile memory module, a delay amount of the DQS signal transmitted between the memory interface and the rewritable non-volatile memory module, the read window size of the DQ signal, and the write window size of the DQ signal (by teaching that the training control circuit can perform training on the memory package and set training values on the plurality of memory devices (140) [0078], where the training includes setting the different delays for the different memory regions of the memory devices (140) in an address-delay map (ADM) [0043-0045]. The delays allows the memory devices (140) to be accessed with optimal phase differences between the data signal (DQ) and the data strobe signal (DQS) [0116-0122] [0142] [0148-0151]).
Regarding claim 5 and analogous claims 12 and 19:
The memory control circuit unit according to claim 1 is made obvious by Ku-Reusswig-Yang-Wang-Kannan.
Ku does not explicitly disclose, but Wang teaches, wherein the operation of the memory management circuit updating the at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module comprises: updating the at least one interface parameter by using at least one first interface parameter corresponding to the target condition in response to the at least one first interface parameter being stored in system information (by teaching that when the temperature acquired from the temperature sensor changes by a threshold amount or more, the PHY parameter control unit (123) acquires a new PHY parameter set corresponding to the current temperature from the PHY parameter table (22) (system information) (in response to the at least one first interface parameter being stored in system information) and sets the PHY parameter set in the NAND PHY (131) (updates the at least one interface parameter by using at least one first interface parameter corresponding to the target condition) [0095] [0101] [Fig. 10]. The PHY parameters are based on a variety of trainings and calibrations [0058]. The PHY parameters may be loaded rather than performing a new calibration and training for each change in temperature [0005-0006] [0053-0055]. There is one PHY parameter table (22) per NAND flash memory chip (5) connected to each channel (Ch). The parameters define parameters used to adjust the timing at which the signal is sent between the controller (4) (through the NAND interface (13)) and the NAND flash memory (5) [0036]. The parameters include parameters to cause a phase shift between the DQ and DQS signals so that they have an appropriate delay for each temperature [0060-0063] [Fig. 2]. A duty cycle adjustment (DCA) may also be performed for each temperature to obtain a duty setting value [0064-0067] [Fig. 3]. Transmission timings may be set based on a read training, with a delay for each temperature [0068] [Fig. 4]. Bit skew may also be adjusted [0069] [Fig. 5]. The effect of the read training and bit skew adjustment is that wide valid data windows are obtained [0071]. The read training and bit skew adjustment also center the sampling time in the middle of the valid data window [0073-0075] [Fig. 6]. Write training is also performed analogous to the read training [0076-0084] [Figs. 7-8]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the adjustment of the parameters based on a change in temperature as taught by Ku to include the CPU determining a change in temperature of the SSD based on a measurement from the temperature sensor, and reading a loading a corresponding parameter set that corresponds to the temperature settings for each chip of a NAND flash on each channel rather than performing a new calibration and training for each detected change in temperature as taught by Wang.
One of ordinary skill in the art would have been motivated to make this modification because loading the parameters from a table based on temperature allows the parameters to be updated without unnecessary calibration and training, which allows continuous access to the NAND flash memory as taught by Wang in [0055].
Regarding claim 6 and analogous claims 13 and 20:
The memory control circuit unit according to claim 5 is made obvious by Ku-Reusswig-Yang-Wang-Kannan.
Ku does not explicitly disclose, but Wang teaches, wherein the operation of the memory management circuit updating the at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module further comprises: performing a scan window correction between the memory interface and the rewritable non-volatile memory module in response to the at least one first interface parameter corresponding to the target condition not being stored in the system information; and updating the at least one interface parameter by using at least one second interface parameter according to a correction result (by teaching that a PHY parameter set corresponding to a certain temperature may be obtained based on calibration/training while the SSD (3) is operating and is added to the PHY parameter table (22). In this case, the SSD can switch to a PHY parameter set corresponding to a measured temperature if it is present in the table. However, if the PHY parameter set for a corresponding temperature is not present in the table, the calibration/training routine may be performed to obtain the PHY parameter set for the corresponding current temperature (in response to the target condition not being stored in the system information) [0117]. Once the PHY parameter set is obtained by the training, it may be used by the NAND PHY and stored in the PHY parameter table [0117] [0120] [0122-0131] (updating the at least one interface parameter by using at least one second interface parameter according to a correction result). The calibration/training may include delay calibration (scan window correction) [Fig. 2] [0060-0063], duty calibration of RE and DQS (scan window correction) [Fig. 3] [0064-0067], read training of centering and bit skew (which includes delays of DQ and DQS signals and furthermore increases the width of and centers the valid data windows for sampling (scan window correction)) [Figs. 4-6] [0068-0075], and write training of centering and of bit skew (scan window correction) [Figs. 7-9] [0081-0086]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the adjustment of the parameters based on a change in temperature as taught by Ku to include the CPU determining a change in temperature of the SSD based on a measurement from the temperature sensor, and reading a loading a corresponding parameter set that corresponds to the temperature settings for each chip of a NAND flash on each channel rather than performing a new calibration and training for each detected change in temperature, unless the parameter table does not include a parameter set for the corresponding temperature, and then performing a calibration/training routine to obtain the parameters and update the NAND flash interface with the parameters and store them in the parameter table as taught by Wang.
One of ordinary skill in the art would have been motivated to make this modification because storing and loading the parameters from a table based on temperature allows the parameters to be updated without repeated calibration/training, which allows continuous access to the NAND flash memory as taught by Wang in [0132].
Regarding claim 7 and analogous claims 14 and 21:
The memory control circuit unit according to claim 6 is made obvious by Ku-Reusswig-Yang-Wang-Kannan.
Ku in view of Wang further make obvious, wherein the scan window correction comprises at least one of a duty cycle correction, read DQ training, write DQ training, a read scan window correction, and a write scan window correction (through the analysis performed for claim 6).
Response to Amendments/Arguments
In response to the amendments to the claims, the previous 35 USC §112(b) rejection has been withdrawn.
In response to the amendments to the claims, a new 35 USC §112(a) rejection has been made to claims 1-21 as seen in the corresponding rejection section above.
In response to the amendments to the claims, the 35 USC §103 rejection has been updated with respect to which portions of Reusswig are relied upon. Applicant’s arguments with respect to the prior art rejection of claims 1-21 do not depend on the new portions of Reusswig now cited. For example, Applicant only argues with respect to Reusswig [Fig. 7] and [Columns 15-17], without discussing any of the newly cited portions about training write parameters for obtaining an optimal write data window size, such as the portions in [Columns 19-21] and [Fig. 6] among others. Accordingly, Applicant’s argument is not persuasive in view of the newly cited portions of Reusswig as necessitated by the amendments to the claims as seen in the corresponding prior art rejection section above.
The rest of Applicants arguments depend from those above and accordingly are not persuasive.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent No. US 9,886,987 B1 (Brahmadathan) – teaches that transmission retraining/calibration may be performed in response to an unexpectedly high level of data transmission errors or a detected temperature/voltage change [Col 11: line 60 – Col 12: line 22].
US Patent Application Publication No. US 2024/0321338 A1 (Han) – teaches that duty cycle may be adjusted to obtain the optimal eye window size for DQ signals [0049-0069] [Fig. 3].
US Patent No. US 10,497,413 B1 (Lin) – teaches that skew settings can be stored for later use [Col 2: lines 25-30].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139