DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gorobets et al. (US 2005/0141313) in view of Yun et al. (US 2017/0277432), Fujiu (US 2013/0235662), Hsieh et al. (US 2019/0227708), and Intel et al. (Open NAND Flash Interface Specification).
In regards to claim 1, Gorobets teaches a memory comprising:
a plurality of memory blocks (“Flash memory comprises blocks of memory cells which are erasable together as a unit.”, paragraph 0127);
a buffer configured to cache data that is to be programmed into the plurality of memory blocks (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389); and
a control logic (controller 100, figure 1),
wherein the control logic is configured to:
receive a program command requesting programing of target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
determine a first lower page location in which the target data is to be programmed, and a second upper page location in which the target data is to be programmed, the first lower page location and the second upper page location being included in the plurality of memory blocks, the first lower page location being different from the second upper page location (“FIG. 45 illustrates yet another embodiment of saving duplicate copies of critical data concurrently to two different metablocks. … Each sector is saved in duplicates. The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
receive the target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
copy the target data to the buffer (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389);
program the target data, stored in the buffer, to the first lower page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
program the target data to the second upper page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560).
Gorobets fails to teach that the location determination is based on address information received after receiving the program command,
a foggy-program address being an address indicating a first location in which the target data is to be foggy-programmed,
a fine-program address being an address indicating a second location in which the target data is to be fine-programmed,
foggy-program the target data,
copy the foggy-programmed target data from the first location to the buffer and fine-program the copied foggy-programmed target data,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and the target data cannot be read from the outside of the memory,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data, and it is possible to read the target data from the outside of the memory, and
wherein the control logic is configured to receive, after receiving the program command, the address information during N address cycles, and parse the address information to determine the foggy-program address and the fine-program address, wherein N is a natural number of two or more.
Yun teaches that the location determination is based on address information received location received after receiving the program command (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; See figure 8B; “The opcode 42 may specify an operation corresponding to a command. For example, the operation may be a normal (e.g., single) read operation, a multi-read operation, a normal (e.g., single) write operation, a multi-write operation, etc.”, paragraph 0090),
an address indicating a first location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093),
an address indicating a second location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; “The duplicate/split flag 47 may be included to indicate, in the case of multi-access, whether the associated data is duplicate data or split data, or to indicate neither (e.g., if the command is a single-access command). As discussed further below, in some cases, data associated with a write command is to be duplicated and stored at two different physical locations.”, paragraph 0092);
it is possible to read the target data from the outside of the memory (“In the embodiments illustrated in FIG. 12, the read data RDAT transmitted to the host 200 may be either the first data DAT1 or the second data DAT2. In this situation, when the same data are stored at different physical addresses for data duplication or mirroring (e.g., duplicate/split flag indicates duplication), only one of the data read from the different physical addresses is transmitted to the host 200.”, paragraph 0118), and
parse the address information to determine the first program address and the second program address (“The address list may include at least two, i.e., N physical addresses. For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093)
“so that an access operation can be performed on at least two different physical block addresses with a single command” (paragraph 0087).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun such that the location determination is based on address information received after receiving the program command,
an address indicating a first location in which the target data is to be programmed,
an address indicating a second location in which the target data is to be programmed; and
it is possible to read the target data from the outside of the memory, and
parse the address information to determine the foggy-program address and the fine-program address
“so that an access operation can be performed on at least two different physical block addresses with a single command” (id.).
Gorobets in view of Yun fails to teach a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed,
foggy-program the target data,
copy the foggy-programmed target data from the first location to the buffer and fine-program the copied foggy-programmed target data,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and the target data cannot be read from the outside of the memory,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data,
wherein the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more.
Fujiu teaches a first location in which the target data is to be foggy-programmed (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101),
a second location in which the target data is to be fine-programmed (“a Fine write operation is performed to obtain the final threshold voltage distributions eR, A to G (Third Stage Program)”, paragraph 0102),
foggy-program the target data (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101),
fine-program the target data (“a Fine write operation is performed to obtain the final threshold voltage distributions eR, A to G (Third Stage Program)”, paragraph 0102),
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101; See also figure 15C), and
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data (Compare figure 15C to figure 15D)
in order to store more bits per cell (paragraph 0099)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun and Fujiu to include a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed,
foggy-program the target data,
fine-program the target data,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data
in order to store more bits per cell (id.).
Gorobets in view of Yun and Fujiu fails to teach copy the foggy-programmed target data from the first location to the buffer; and
fine-program the copied foggy-programmed target data,
the target data cannot be read from the outside of the memory,
wherein the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more.
Hsieh teaches copy the programmed target data from the first location to the buffer (“the user data stored in cache memory mirror 22 are copied and transferred to cache memory 20”, paragraph 0017) and program the copied programmed target data (“The user data are written into user data storage zone 24 from cache memory 20 via flash translation layer 16 in a write-back mode. … Then, data storage apparatus 12 repeats the above-mentioned process.”, paragraph 0017),
the target data cannot be read from outside of the memory (“The user data will not be read from cache memory mirror 22 if no power failure occurs during the writing of the user data.”, paragraph 0034)
“to restore the normal operation, without having to lose any of the user data” (paragraph 0017).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Fujiu, and Hsieh to include copy the foggy-programmed target data from the first location to the buffer and fine-program the copied foggy-programmed target data,
the target data cannot be read from outside of the memory
“to restore the normal operation, without having to lose any of the user data” (id.).
Gorobets in view of Yun, Fujiu, and Hsieh fails to teach that the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more. Intel teaches that the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more (“When both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit address cycles. The row addresses follow in one or more 8-bit address cycles.”, page 89, paragraph 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Fujiu, Hsieh, and Intel such that the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more in order to address a large number of bytes while reducing the number of pins.
In regards to claim 3, Yun further teaches that the control logic determines address information received during preceding (N/2) address cycles among the N address cycles as the first program address, and determines address information received during subsequent (N/2) address cycles among the N address cycles as the second program address (“For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093).
In regards to claim 8, Gorobets teaches an operating method of a memory comprising:
receiving a program command requesting programming of target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
determining a first lower page location in which the target data is to be programmed, and a second upper page location in which the target data is to be programmed, the first location and the second location being included in a plurality of memory blocks, the first location being different from the second location (“FIG. 45 illustrates yet another embodiment of saving duplicate copies of critical data concurrently to two different metablocks. … Each sector is saved in duplicates. The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
receiving the target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
copying the target data to a buffer that is configured to cache data to be programmed into the plurality of memory blocks (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389);
programming the target data, stored in the buffer, to the first lower page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560); and
programming the target data to the second upper page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560).
Gorobets fails to teach that the location determining is based on address information received after receiving the program command,
a foggy-program address being an address indicating a first location in which the target data is to be foggy-programmed,
a fine-program address being an address indicating a second location in which the target data is to be fine-programmed;
foggy-programming the target data to the first location;
copy the foggy-programmed target data from the first location to the buffer; and
fine-programming the copied foggy-programmed target data to the second location,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and the target data cannot be read from the outside of the memory,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data, and it is possible to read the target data from the outside of the memory, and
wherein the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more; and
parsing the address information to determine the foggy-program address and the fine- program address.
Yun teaches that the location determining is based on address information received after receiving the program command (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; See figure 8B; “The opcode 42 may specify an operation corresponding to a command. For example, the operation may be a normal (e.g., single) read operation, a multi-read operation, a normal (e.g., single) write operation, a multi-write operation, etc.”, paragraph 0090),
an address indicating a first location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093),
an address indicating a second location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; “The duplicate/split flag 47 may be included to indicate, in the case of multi-access, whether the associated data is duplicate data or split data, or to indicate neither (e.g., if the command is a single-access command). As discussed further below, in some cases, data associated with a write command is to be duplicated and stored at two different physical locations.”, paragraph 0092);
it is possible to read the target data from the outside of the memory (“In the embodiments illustrated in FIG. 12, the read data RDAT transmitted to the host 200 may be either the first data DAT1 or the second data DAT2. In this situation, when the same data are stored at different physical addresses for data duplication or mirroring (e.g., duplicate/split flag indicates duplication), only one of the data read from the different physical addresses is transmitted to the host 200.”, paragraph 0118); and
wherein the determining the addresses comprises:
parsing the address information to determine the foggy-program address and the fine- program address (“The address list may include at least two, i.e., N physical addresses. For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093)
“so that an access operation can be performed on at least two different physical block addresses with a single command” (paragraph 0087).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun such that the location determining is based on address information received after receiving the program command,
an address indicating a first location in which the target data is to be programmed,
an address indicating a second location in which the target data is to be programmed;
it is possible to read the target data from the outside of the memory, and
wherein the determining a foggy-program address and a fine-program address comprises:
parsing the address information to determine the foggy-program address and the fine- program address
“so that an access operation can be performed on at least two different physical block addresses with a single command” (id.).
Gorobets in view of Yun fails to teach a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed;
foggy-programming the target data to the first location;
copy the foggy-programmed target data from the first location to the buffer; and
fine-programming the copied foggy-programmed target data to the second location,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and the target data cannot be read from the outside of the memory,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data, and
wherein the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Fujiu teaches a first location in which the target data is to be foggy-programmed (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101),
a second location in which the target data is to be fine-programmed (“a Fine write operation is performed to obtain the final threshold voltage distributions eR, A to G (Third Stage Program)”, paragraph 0102);
foggy-programming the target data to the first location (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101);
fine-programming the target data to the second location (“a Fine write operation is performed to obtain the final threshold voltage distributions eR, A to G (Third Stage Program)”, paragraph 0102),
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101; See also figure 15C), and
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data (Compare figure 15C to figure 15D)
in order to store more bits per cell (paragraph 0099).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun and Fujiu to include a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed;
foggy-programming the target data to the first location; and
fine-programming the copied foggy-programmed target data to the second location,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data
in order to store more bits per cell (id.).
Gorobets in view of Yun and Fujiu fails to teach copy the programmed target data from the first location to the buffer; and
programming the copied programmed target data to the second location,
the target data cannot be read from the outside of the memory
wherein the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Hsieh teaches copy the programmed target data from the first location to the buffer (“the user data stored in cache memory mirror 22 are copied and transferred to cache memory 20”, paragraph 0017); and
programming the copied programmed target data to the second location (“The user data are written into user data storage zone 24 from cache memory 20 via flash translation layer 16 in a write-back mode. … Then, data storage apparatus 12 repeats the above-mentioned process.”, paragraph 0017)
the target data cannot be read from outside of the memory (“The user data will not be read from cache memory mirror 22 if no power failure occurs during the writing of the user data.”, paragraph 0034)
“to restore the normal operation, without having to lose any of the user data” (paragraph 0017).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, and Hsieh to include copy the programmed target data from the first location to the buffer; and
programming the copied programmed target data to the second location
the target data cannot be read from outside of the memory
“to restore the normal operation, without having to lose any of the user data” (id.).
Gorobets in view of Yun, Fujiu, and Hsieh fails to teach that the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Intel teaches that the determining a program addresses comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more (“When both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit address cycles. The row addresses follow in one or more 8-bit address cycles.”, page 89, paragraph 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Fujiu, Hsieh, and Intel such that the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more
in order to address a large number of bytes while reducing the number of pins.
In regards to claim 10, Yun further teaches that the determining a first program address and a second program address comprises:
determining address information received during preceding (N/2) address cycles among the N address cycles as the first program address (“For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093); and
determining address information received during subsequent (N/2) address cycles among the N address cycles as the second program address (“For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093).
In regards to claim 13, Gorobets teaches a storage device comprising:
a memory (memory system 20, figure 1) comprising:
a plurality of memory blocks (“Flash memory comprises blocks of memory cells which are erasable together as a unit.”, paragraph 0127);
a buffer configured to cache data that is to be programmed into the plurality of memory blocks (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389); and
a control logic (controller 100, figure 1),
wherein the control logic is configured to:
receive a program command requesting programming of target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
determine a first lower page location in which the target data is to be programmed, a second upper page location in which the target data is to be programmed, the first location being different from the second location (“FIG. 45 illustrates yet another embodiment of saving duplicate copies of critical data concurrently to two different metablocks. … Each sector is saved in duplicates. The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
receive the target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
copy the target data to the buffer (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389);
program the target data, stored in the buffer, to the first lower page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
program the target data to the second upper page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560); and
a controller configured to transmit the program command and the target data to the memory (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119).
Gorobets fails to teach that the location determination is based on address information received after receiving the program command,
a foggy-program address being an address indicating a first location in which the target data is to be foggy-programmed,
a fine-program address being an address indicating a second location in which the target data is to be fine-programmed,
foggy-program the target data to the first location indicated by the foggy-program address; and
copy the foggy-programmed target data from the first location to the buffer; and
fine-program the copied foggy-programmed target data to the second location indicated by the fine-program address;
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and the target data cannot be read from the outside of the memory,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data, and it is possible to read the target data from the outside of the memory, and
wherein the control logic is configured to receive, after receiving the program command, the address information during N address cycles, and parse the address information to determine the foggy-program address and the fine-program address, wherein N is a natural number of two or more.
Yun teaches that the location determination is based on address information received after receiving the program command (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; See figure 8B; “The opcode 42 may specify an operation corresponding to a command. For example, the operation may be a normal (e.g., single) read operation, a multi-read operation, a normal (e.g., single) write operation, a multi-write operation, etc.”, paragraph 0090),
a first program address being an address indicating a first location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093),
a second program address being an address indicating a second location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; “The duplicate/split flag 47 may be included to indicate, in the case of multi-access, whether the associated data is duplicate data or split data, or to indicate neither (e.g., if the command is a single-access command). As discussed further below, in some cases, data associated with a write command is to be duplicated and stored at two different physical locations.”, paragraph 0092), and
it is possible to read the target data from the outside of the memory (“In the embodiments illustrated in FIG. 12, the read data RDAT transmitted to the host 200 may be either the first data DAT1 or the second data DAT2. In this situation, when the same data are stored at different physical addresses for data duplication or mirroring (e.g., duplicate/split flag indicates duplication), only one of the data read from the different physical addresses is transmitted to the host 200.”, paragraph 0118), and
wherein the control logic is configured to parse the address information to determine the first program address and the second program address (“The address list may include at least two, i.e., N physical addresses. For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093)
“so that an access operation can be performed on at least two different physical block addresses with a single command” (paragraph 0087).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun such that the location determination is based on address information received after receiving the program command,
a first program address being an address indicating a first location in which the target data is to be programmed,
a second program address being an address indicating a second location in which the target data is to be programmed, and
it is possible to read the target data from the outside of the memory, and
wherein the control logic is configured to parse the address information to determine the foggy-program address and the fine-program address
“so that an access operation can be performed on at least two different physical block addresses with a single command” (id.).
Gorobets in view of Yun fails to teach a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed,
foggy-program the target data to the first location;
copy the foggy-programmed target data from the first location to the buffer; and
fine-program the copied foggy-programmed target data to the second location;
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and the target data cannot be read from the outside of the memory,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data, and
wherein the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Fujiu teaches a first location in which the target data is to be foggy-programmed (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101),
a second location in which the target data is to be fine-programmed (“a Fine write operation is performed to obtain the final threshold voltage distributions eR, A to G (Third Stage Program)”, paragraph 0102),
foggy-program the target data to the first location (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101); and
fine-program the target data to the second location (“a Fine write operation is performed to obtain the final threshold voltage distributions eR, A to G (Third Stage Program)”, paragraph 0102);
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states (“Next, the program operation to obtain intermediate threshold voltage distributions A', B', C', . . . , G' from the intermediate threshold voltage distribution LM, using the verify read voltages VVA', VVB', VVC', . . . , VVG', is performed (Foggy write (Second Stage Program)).”, paragraph 0101; See also figure 15C),
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data (Compare figure 15C to figure 15D)
in order to store more bits per cell (paragraph 0099).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun and Fujiu to include a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed,
foggy-program the target data to the first location;
fine-program the target data to the second location;
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted more finely than those of the foggy-programmed target data
in order to store more bits per cell (id.).
Gorobets in view of Yun and Fujiu fails to teach copy the programmed target data from the first location to the buffer; and
program the copied programmed target data to the second location;
the target data cannot be read from the outside of the memory,
wherein the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Hsieh teaches copy the programmed target data from the first location to the buffer (“the user data stored in cache memory mirror 22 are copied and transferred to cache memory 20”, paragraph 0017); and
program the copied programmed target data to the second location (“The user data are written into user data storage zone 24 from cache memory 20 via flash translation layer 16 in a write-back mode. … Then, data storage apparatus 12 repeats the above-mentioned process.”, paragraph 0017)
the target data cannot be read from the outside of the memory (“The user data will not be read from cache memory mirror 22 if no power failure occurs during the writing of the user data.”, paragraph 0034),
“to restore the normal operation, without having to lose any of the user data” (paragraph 0017).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Fujiu, and Hsieh to include copy the programmed target data from the first location to the buffer; and
program the copied programmed target data to the second location
the target data cannot be read from outside of the memory,
“to restore the normal operation, without having to lose any of the user data” (id.).
Gorobets in view of Yun, Fujiu, and Hsieh fails to teach that the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more. Intel teaches that the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more (“When both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit address cycles. The row addresses follow in one or more 8-bit address cycles.”, page 89, paragraph 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Fujiu, Hsieh, and Intel such that the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more in order to address a large number of bytes while reducing the number of pins.
Claims 6, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gorobets et al. (US 2005/0141313) in view of Yun et al. (US 2017/0277432), Fujiu (US 2013/0235662), Hsieh et al. (US 2019/0227708), Intel et al. (Open NAND Flash Interface Specification), and Kim (US 2020/0301586).
In regards to claim 6, Gorobets in view of Yun, Fujiu, Hsieh, and Intel teaches claim 1. Gorobets in view of Yun, Fujiu, Hsieh, and Intel fails to teach a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA,
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer.
Kim teaches a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059),
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059)
in order to avoid involving the CPU (paragraph 0059).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Fujiu, Hsieh, Intel, and Kim to include a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA,
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer
in order to avoid involving the CPU (id.).
In regards to claim 16, Gorobets in view of Yun, Fujiu, Hsieh, and Intel teaches claim 8. Gorobets in view of Yun, Fujiu, Hsieh, and Intel fails to teach that the copying of the foggy- programmed target data includes copying the foggy-programmed target data from the first location to the buffer using a direct memory access (DMA) engine. Kim teaches that the copying of the foggy- programmed target data includes copying the foggy-programmed target data from the first location to the buffer using a direct memory access (DMA) engine (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059) in order to avoid involving the CPU (paragraph 0059). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Fujiu, Hsieh, Intel, and Kim such that the copying of the foggy- programmed target data includes copying the foggy-programmed target data from the first location to the buffer using a direct memory access (DMA) engine in order to avoid involving the CPU (id.).
In regards to claim 17, Gorobets in view of Yun, Fujiu, Hsieh, and Intel teaches claim 13. Gorobets in view of Yun, Fujiu, Hsieh, and Intel fails to teach that the memory further comprises a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA,
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer.
Kim teaches that the memory further comprises a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059),
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059)
in order to avoid involving the CPU (paragraph 0059).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Fujiu, Hsieh, Intel, and Kim to include a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA,
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer
in order to avoid involving the CPU (id.).
Response to Arguments
Applicant’s arguments, see page 7, filed 16 April 2026, with respect to the 112(d) rejection have been fully considered and are persuasive. The 112(d) rejection has been withdrawn.
Applicant's remaining arguments, see pages 7-10, filed 16 April 2026, with respect to the obviousness rejections have been fully considered but they are not persuasive.
1) The Examiner recognizes that Hsieh is a recovery mechanism for power failure. However, the present application does as well (See paragraph 0137). The Examiner is interpreting Hsieh’s same sequence as specifying that, when a write operation is received, before the write operation can be complete, the data must be written into cache memory 20 and cache memory mirror 22. In Hsieh, the data is not written to its ultimate destination until it is written into user data storage zone 24.
2 and 3) Hsieh does require that the data in cache memory mirror 22 and user data storage zone 24 be programmed using different methods, namely SLC and MLC or TLC.
4) Hsieh does not teach away from employing different programming methods at different locations. In fact, Hsieh explicitly teaches employing different programming methods at different locations, namely SLC and MLC or TLC.
5) The Examiner recognizes that Hsieh uses different storage densities. However, the claims do not specify the storage densities. Using a finer threshold voltage distribution is different than storing data at higher densities. Comparing figures 15C and 15D of Fujiu shows two different threshold voltage distributions. Figure 15D’s is finer, but both store 8 levels or 3 bits per cell. The claims make no requirements regarding resource efficiency.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 19 May 2026
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