DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5 December 2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 6 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to contain a reference to a claim previously set forth. Claim 6 depends on claim 5, but claim 5 has been cancelled. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gorobets et al. (US 2005/0141313) in view of Yun et al. (US 2017/0277432), Ji et al. (US 2021/0191636), Hsieh et al. (US 2019/0227708), and Intel et al. (Open NAND Flash Interface Specification).
In regards to claim 1, Gorobets teaches a memory comprising:
a plurality of memory blocks (“Flash memory comprises blocks of memory cells which are erasable together as a unit.”, paragraph 0127);
a buffer configured to cache data that is to be programmed into the plurality of memory blocks (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389); and
a control logic (controller 100, figure 1),
wherein the control logic is configured to:
receive a program command requesting programing of target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
determine a first lower page location in which the target data is to be programmed, and a second upper page location in which the target data is to be programmed, the first lower page location and the second upper page location being included in the plurality of memory blocks, the first lower page location being different from the second upper page location (“FIG. 45 illustrates yet another embodiment of saving duplicate copies of critical data concurrently to two different metablocks. … Each sector is saved in duplicates. The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
receive the target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
copy the target data to the buffer (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389);
program the target data, stored in the buffer, to the first lower page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
program the target data to the second upper page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560).
Gorobets fails to teach that the location determination is based on address information received after receiving the program command,
a foggy-program address being an address indicating a first location in which the target data is to be foggy-programmed,
a fine-program address being an address indicating a second location in which the target data is to be fine-programmed,
foggy-program the target data,
copy the foggy-programmed target data from the first location to the buffer and fine-program the copied foggy-programmed target data,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted,
wherein the control logic is configured to receive, after receiving the program command, the address information during N address cycles, and parse the address information to determine the foggy-program address and the fine-program address, wherein N is a natural number of two or more.
Yun teaches that the location determination is based on address information received location received after receiving the program command (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; See figure 8B; “The opcode 42 may specify an operation corresponding to a command. For example, the operation may be a normal (e.g., single) read operation, a multi-read operation, a normal (e.g., single) write operation, a multi-write operation, etc.”, paragraph 0090),
an address indicating a first location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093),
an address indicating a second location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; “The duplicate/split flag 47 may be included to indicate, in the case of multi-access, whether the associated data is duplicate data or split data, or to indicate neither (e.g., if the command is a single-access command). As discussed further below, in some cases, data associated with a write command is to be duplicated and stored at two different physical locations.”, paragraph 0092); and
parse the address information to determine the first program address and the second program address (“The address list may include at least two, i.e., N physical addresses. For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093)
“so that an access operation can be performed on at least two different physical block addresses with a single command” (paragraph 0087).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun such that the location determination is based on address information received after receiving the program command,
an address indicating a first location in which the target data is to be programmed,
an address indicating a second location in which the target data is to be programmed, and
parse the address information to determine the foggy-program address and the fine-program address
“so that an access operation can be performed on at least two different physical block addresses with a single command” (id.).
Gorobets in view of Yun fails to teach a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed,
foggy-program the target data,
copy the foggy-programmed target data from the first location to the buffer and fine-program the copied foggy-programmed target data,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted,
wherein the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more.
Ji teaches a first location in which the target data is to be foggy-programmed (“a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states”, abstract),
a second location in which the target data is to be fine-programmed (“a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states”, abstract),
foggy-program the target data (“a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states”, abstract),
fine-program the target data (“a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states”, abstract),
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states (“Each of the memory cells may have a threshold voltage that belongs to a threshold voltage distribution of any one of the erased state E and the first to seventh intermediate states I1 to I7 by the foggy program operation.”, paragraph 0111), and
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted (See figure 6; “FIG. 6 is a diagram illustrating threshold voltage distributions formed when the foggy program operation and the fine program operation are performed on memory cells of one page. In detail, dashed lines indicate threshold voltage distributions of the memory cells after the foggy program operation has been performed. Solid lines indicate threshold voltage distributions of the memory cells after the fine program operation has been performed.”, paragraph 0108)
“so that each memory cell has a threshold voltage corresponding to any one state” (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun and Ji to include a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed,
foggy-program the target data,
fine-program the target data,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states, and
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted
“so that each memory cell has a threshold voltage corresponding to any one state” (abstract).
Gorobets in view of Yun and Ji fails to teach copy the foggy-programmed target data from the first location to the buffer and fine-program the copied foggy-programmed target data,
wherein the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more.
Hsieh teaches copy the programmed target data from the first location to the buffer (“the user data stored in cache memory mirror 22 are copied and transferred to cache memory 20”, paragraph 0017) and program the copied programmed target data (“The user data are written into user data storage zone 24 from cache memory 20 via flash translation layer 16 in a write-back mode. … Then, data storage apparatus 12 repeats the above-mentioned process.”, paragraph 0017) “to restore the normal operation, without having to lose any of the user data” (paragraph 0017). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, and Hsieh to include copy the foggy-programmed target data from the first location to the buffer and fine-program the copied foggy-programmed target data “to restore the normal operation, without having to lose any of the user data” (id.).
Gorobets in view of Yun, Ji, and Hsieh fails to teach that the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more. Intel teaches that the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more (“When both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit address cycles. The row addresses follow in one or more 8-bit address cycles.”, page 89, paragraph 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, Hsieh, and Intel such that the control logic is configured to receive the address information during N address cycles, wherein N is a natural number of two or more in order to address a large number of bytes while reducing the number of pins.
In regards to claim 3, Yun further teaches that the control logic determines address information received during preceding (N/2) address cycles among the N address cycles as the first program address, and determines address information received during subsequent (N/2) address cycles among the N address cycles as the second program address (“For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093).
In regards to claim 8, Gorobets teaches an operating method of a memory comprising:
receiving a program command requesting programming of target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
determining a first lower page location in which the target data is to be programmed, and a second upper page location in which the target data is to be programmed, the first location and the second location being included in a plurality of memory blocks, the first location being different from the second location (“FIG. 45 illustrates yet another embodiment of saving duplicate copies of critical data concurrently to two different metablocks. … Each sector is saved in duplicates. The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
receiving the target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
copying the target data to a buffer that is configured to cache data to be programmed into the plurality of memory blocks (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389);
programming the target data, stored in the buffer, to the first lower page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560); and
programming the target data to the second upper page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560).
Gorobets fails to teach that the location determining is based on address information received after receiving the program command,
a foggy-program address being an address indicating a first location in which the target data is to be foggy-programmed,
a fine-program address being an address indicating a second location in which the target data is to be fine-programmed;
foggy-programming the target data to the first location;
copy the foggy-programmed target data from the first location to the buffer; and
fine-programming the copied foggy-programmed target data to the second location,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted, and
wherein the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more; and
parsing the address information to determine the foggy-program address and the fine- program address.
Yun teaches that the location determining is based on address information received after receiving the program command (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; See figure 8B; “The opcode 42 may specify an operation corresponding to a command. For example, the operation may be a normal (e.g., single) read operation, a multi-read operation, a normal (e.g., single) write operation, a multi-write operation, etc.”, paragraph 0090),
an address indicating a first location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093),
an address indicating a second location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; “The duplicate/split flag 47 may be included to indicate, in the case of multi-access, whether the associated data is duplicate data or split data, or to indicate neither (e.g., if the command is a single-access command). As discussed further below, in some cases, data associated with a write command is to be duplicated and stored at two different physical locations.”, paragraph 0092);
wherein the determining the addresses comprises:
parsing the address information to determine the foggy-program address and the fine- program address (“The address list may include at least two, i.e., N physical addresses. For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093)
“so that an access operation can be performed on at least two different physical block addresses with a single command” (paragraph 0087).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun such that the location determining is based on address information received after receiving the program command,
an address indicating a first location in which the target data is to be programmed,
an address indicating a second location in which the target data is to be programmed;
wherein the determining a foggy-program address and a fine-program address comprises:
parsing the address information to determine the foggy-program address and the fine- program address
“so that an access operation can be performed on at least two different physical block addresses with a single command” (id.).
Gorobets in view of Yun fails to teach a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed;
foggy-programming the target data to the first location;
copy the foggy-programmed target data from the first location to the buffer; and
fine-programming the copied foggy-programmed target data to the second location,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted, and
wherein the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Ji teaches a first location in which the target data is to be foggy-programmed (“a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states”, abstract),
a second location in which the target data is to be fine-programmed (“a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states”, abstract);
foggy-programming the target data to the first location (“a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states”, abstract);
fine-programming the target data to the second location (“a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states”, abstract),
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states (“Each of the memory cells may have a threshold voltage that belongs to a threshold voltage distribution of any one of the erased state E and the first to seventh intermediate states I1 to I7 by the foggy program operation.”, paragraph 0111), and
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted (See figure 6; “FIG. 6 is a diagram illustrating threshold voltage distributions formed when the foggy program operation and the fine program operation are performed on memory cells of one page. In detail, dashed lines indicate threshold voltage distributions of the memory cells after the foggy program operation has been performed. Solid lines indicate threshold voltage distributions of the memory cells after the fine program operation has been performed.”, paragraph 0108)
“so that each memory cell has a threshold voltage corresponding to any one state” (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun and Ji to include a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed;
foggy-programming the target data to the first location; and
fine-programming the copied foggy-programmed target data to the second location,
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted, and
Gorobets in view of Yun and Ji fails to teach copy the programmed target data from the first location to the buffer; and
programming the copied programmed target data to the second location,
wherein the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Hsieh teaches copy the programmed target data from the first location to the buffer (“the user data stored in cache memory mirror 22 are copied and transferred to cache memory 20”, paragraph 0017); and
programming the copied programmed target data to the second location (“The user data are written into user data storage zone 24 from cache memory 20 via flash translation layer 16 in a write-back mode. … Then, data storage apparatus 12 repeats the above-mentioned process.”, paragraph 0017)
“to restore the normal operation, without having to lose any of the user data” (paragraph 0017).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, and Hsieh to include copy the programmed target data from the first location to the buffer; and
programming the copied programmed target data to the second location
“to restore the normal operation, without having to lose any of the user data” (id.).
Gorobets in view of Yun, Ji, and Hsieh fails to teach that the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Intel teaches that the determining a program addresses comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more (“When both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit address cycles. The row addresses follow in one or more 8-bit address cycles.”, page 89, paragraph 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, Hsieh, and Intel such that the determining a foggy-program address and a fine-program address comprises:
receiving, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more
in order to address a large number of bytes while reducing the number of pins.
In regards to claim 10, Yun further teaches that the determining a first program address and a second program address comprises:
determining address information received during preceding (N/2) address cycles among the N address cycles as the first program address (“For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093); and
determining address information received during subsequent (N/2) address cycles among the N address cycles as the second program address (“For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093).
In regards to claim 13, Gorobets teaches a storage device comprising:
a memory (memory system 20, figure 1) comprising:
a plurality of memory blocks (“Flash memory comprises blocks of memory cells which are erasable together as a unit.”, paragraph 0127);
a buffer configured to cache data that is to be programmed into the plurality of memory blocks (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389); and
a control logic (controller 100, figure 1),
wherein the control logic is configured to:
receive a program command requesting programming of target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
determine a first lower page location in which the target data is to be programmed, a second upper page location in which the target data is to be programmed, the first location being different from the second location (“FIG. 45 illustrates yet another embodiment of saving duplicate copies of critical data concurrently to two different metablocks. … Each sector is saved in duplicates. The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
receive the target data (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119);
copy the target data to the buffer (“A buffer 922 in the controller 920 helps to buffer the transfer of data via the data bus 930.”, paragraph 0389);
program the target data, stored in the buffer, to the first lower page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560);
program the target data to the second upper page location (“The two copies will be written concurrently to two differently blocks, Block 0 and Block 1. If one copy is written to a logical lower page, the other copy will be written to a logical upper page.”, paragraph 0560); and
a controller configured to transmit the program command and the target data to the memory (“In most cases during read or write operations, the host 10 essentially issues a command to the memory system 20 to read or write a segment containing a string of logical sectors of data with contiguous addresses.”, paragraph 0119).
Gorobets fails to teach that the location determination is based on address information received after receiving the program command,
a foggy-program address being an address indicating a first location in which the target data is to be foggy-programmed,
a fine-program address being an address indicating a second location in which the target data is to be fine-programmed,
foggy-program the target data to the first location indicated by the foggy-program address; and
copy the foggy-programmed target data from the first location to the buffer; and
fine-program the copied foggy-programmed target data to the second location indicated by the fine-program address;
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted, and
wherein the control logic is configured to receive, after receiving the program command, the address information during N address cycles, and parse the address information to determine the foggy-program address and the fine-program address, wherein N is a natural number of two or more.
Yun teaches that the location determination is based on address information received after receiving the program command (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; See figure 8B; “The opcode 42 may specify an operation corresponding to a command. For example, the operation may be a normal (e.g., single) read operation, a multi-read operation, a normal (e.g., single) write operation, a multi-write operation, etc.”, paragraph 0090),
a first program address being an address indicating a first location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093),
a second program address being an address indicating a second location in which the target data is to be programmed (“Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093; “The duplicate/split flag 47 may be included to indicate, in the case of multi-access, whether the associated data is duplicate data or split data, or to indicate neither (e.g., if the command is a single-access command). As discussed further below, in some cases, data associated with a write command is to be duplicated and stored at two different physical locations.”, paragraph 0092), and
wherein the control logic is configured to parse the address information to determine the first program address and the second program address (“The address list may include at least two, i.e., N physical addresses. For instance, the address list may include a first physical address 44 and a second physical address 45. Each of the physical addresses 44 and 45 may include a start address (Start_Address) 441 or 451 of physical blocks to which data will be written in the data storage device 300 and the number of the physical blocks 443 or 453.”, paragraph 0093)
“so that an access operation can be performed on at least two different physical block addresses with a single command” (paragraph 0087).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun such that the location determination is based on address information received after receiving the program command,
a first program address being an address indicating a first location in which the target data is to be programmed,
a second program address being an address indicating a second location in which the target data is to be programmed, and
wherein the control logic is configured to parse the address information to determine the foggy-program address and the fine-program address
“so that an access operation can be performed on at least two different physical block addresses with a single command” (id.).
Gorobets in view of Yun fails to teach a first location in which the target data is to be foggy-programmed,
a second location in which the target data is to be fine-programmed,
foggy-program the target data to the first location;
copy the foggy-programmed target data from the first location to the buffer; and
fine-program the copied foggy-programmed target data to the second location;
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states,
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted, and
wherein the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Ji teaches a first location in which the target data is to be foggy-programmed (“a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states”, abstract),
a second location in which the target data is to be fine-programmed (“a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states”, abstract),
foggy-program the target data to the first location (“a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states”, abstract); and
fine-program the target data to the second location (“a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states”, abstract);
wherein, when the target data is foggy-programmed, memory cells programmed with the target data are programmed into an erase state or one of a plurality of intermediate program states (“Each of the memory cells may have a threshold voltage that belongs to a threshold voltage distribution of any one of the erased state E and the first to seventh intermediate states I1 to I7 by the foggy program operation.”, paragraph 0111),
wherein, when the target data is fine-programmed, threshold voltage distributions of the memory cells programmed with the target data are adjusted (See figure 6; “FIG. 6 is a diagram illustrating threshold voltage distributions formed when the foggy program operation and the fine program operation are performed on memory cells of one page. In detail, dashed lines indicate threshold voltage distributions of the memory cells after the foggy program operation has been performed. Solid lines indicate threshold voltage distributions of the memory cells after the fine program operation has been performed.”, paragraph 0108)
“so that each memory cell has a threshold voltage corresponding to any one state” (abstract).
Gorobets in view of Yun and Hsieh fails to teach copy the programmed target data from the first location to the buffer; and
program the copied programmed target data to the second location;
wherein the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more.
Hsieh teaches copy the programmed target data from the first location to the buffer (“the user data stored in cache memory mirror 22 are copied and transferred to cache memory 20”, paragraph 0017); and
program the copied programmed target data to the second location (“The user data are written into user data storage zone 24 from cache memory 20 via flash translation layer 16 in a write-back mode. … Then, data storage apparatus 12 repeats the above-mentioned process.”, paragraph 0017)
“to restore the normal operation, without having to lose any of the user data” (paragraph 0017).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, and Hsieh to include copy the programmed target data from the first location to the buffer; and
program the copied programmed target data to the second location
“to restore the normal operation, without having to lose any of the user data” (id.).
Gorobets in view of Yun, Ji, and Hsieh fails to teach that the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more. Intel teaches that the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more (“When both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit address cycles. The row addresses follow in one or more 8-bit address cycles.”, page 89, paragraph 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, Hsieh, and Intel such that the control logic is configured to receive, after receiving the program command, the address information during N address cycles, wherein N is a natural number of two or more in order to address a large number of bytes while reducing the number of pins.
Claims 6, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gorobets et al. (US 2005/0141313) in view of Yun et al. (US 2017/0277432), Ji et al. (US 2021/0191636), Hsieh et al. (US 2019/0227708), Intel et al. (Open NAND Flash Interface Specification), and Kim (US 2020/0301586).
In regards to claim 6, Gorobets in view of Yun, Ji, Hsieh, and Intel teaches claim 1. Gorobets in view of Yun, Ji, Hsieh, and Intel fails to teach a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA,
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer.
Kim teaches a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059),
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059)
in order to avoid involving the CPU (paragraph 0059).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, Hsieh, Intel, and Kim to include a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA,
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer
in order to avoid involving the CPU (id.).
In regards to claim 16, Gorobets in view of Yun, Ji, Hsieh, and Intel teaches claim 8. Gorobets in view of Yun, Ji, Hsieh, and Intel fails to teach that the copying of the foggy- programmed target data includes copying the foggy-programmed target data from the first location to the buffer using a direct memory access (DMA) engine. Kim teaches that the copying of the foggy- programmed target data includes copying the foggy-programmed target data from the first location to the buffer using a direct memory access (DMA) engine (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059) in order to avoid involving the CPU (paragraph 0059). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, Hsieh, Intel, and Kim such that the copying of the foggy- programmed target data includes copying the foggy-programmed target data from the first location to the buffer using a direct memory access (DMA) engine in order to avoid involving the CPU (id.).
In regards to claim 17, Gorobets in view of Yun, Ji, Hsieh, and Intel teaches claim 13. Gorobets in view of Yun, Ji, Hsieh, and Intel fails to teach that the memory further comprises a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA,
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer.
Kim teaches that the memory further comprises a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059),
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer (“The second DMA engine 1157 may transfer and store write data stored in the buffer memory into the second write buffer 1153 during the write operation, and transfer and store read data stored in the second read buffer 1155 into the buffer memory during the read operation.”, paragraph 0059)
in order to avoid involving the CPU (paragraph 0059).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gorobets with Yun, Ji, Hsieh, Intel, and Kim to include a direct memory access (DMA) engine for copying data stored in the plurality of memory blocks to the buffer through DMA,
wherein the control logic requests the DMA engine to copy the foggy-programmed target data from the first location to the buffer
in order to avoid involving the CPU (id.).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/Nathan Sadler/Primary Examiner, Art Unit 2139 16 January 2026