DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by this Examiner.
Claim Objections
Claims 4 and 8 are objected to because of the following informalities:
Per claim 4, line 1, it would be more appropriate to replace “is” with “are” due to typographical and/or grammatic errors.
Per claim 8, line 1, it would be more appropriate to replace “is” with “are” due to typographical and/or grammatic errors.
All dependent claims are objected to as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Per claim 1, line 9, “the virtual memory space of the at least two processes” lacks sufficient antecedent basis. Line 7 of the instant claim only teaches “virtual memory spaces for the at least two compute blocks”. For prior art rejection purposes, the claim has been interpreted to mean that the virtual memory spaces are allocated to the at least two processes.
Per claim 2, line 1, “the process isolation” lacks sufficient antecedent basis. Claim 1 only teaches isolating the virtual memory spaces of the at least two processes.
Per claim 4, line 2, “the system network” lacks sufficient antecedent basis.
Per claim 9, line 7, “the virtual memory space of the at least two processes” lacks sufficient antecedent basis. Line 5 of the instant claim only teaches “virtual memory spaces for the at least two compute blocks”. For prior art rejection purposes, the claim has been interpreted to mean that the virtual memory spaces are allocated to the at least two processes.
Per claim 10, lines 1-2, “the virtual memories” lacks sufficient antecedent basis. It would be more appropriate to replace “memories” with “memory spaces”.
Per claim 17, line 6, “the virtual memory space of the at least two processes” lacks sufficient antecedent basis. Line 4 of the instant claim only teaches “virtual memory spaces for the at least two compute blocks”. For prior art rejection purposes, the claim has been interpreted to mean that the virtual memory spaces are allocated to the at least two processes.
Per claim 18, line 1, “the virtual memories” lacks sufficient antecedent basis. It would be more appropriate to replace “memories” with “memory spaces”.
All dependent claims are rejected as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Sell et al. [Pub.No.: US 20150095661 A1] (hereinafter “Sell”).
Independent Claims:
Per claim 1, Sell teaches:
A computing system (see Fig. 1, computing system 100) comprising:
at least one memory that stores computer-executable instructions (see paragraph [0064] and exemplary claims 15-20 for computer readable instructions stored in computer readable storage medium); and
at least one processor (see paragraph [0064] and exemplary claims 15-20 for a processor executing the computer readable instructions) configured to access the at least one memory and execute the computer-executable instructions to:
execute at least two processes (see paragraph [0038] and Fig. 2 for CPU Process 224, GPU Process 228 and APU Process 234) within a device (see Fig. 2, hardware layer 202, which comprises the processing units 101, 108 and 114 that executes the CPU Process 224, GPU Process 228 and APU Process 234) in a computing environment (see Fig. 2, the hardware layer 202, operating system 206 and application layer 220 can be collectively viewed as a computing environment), each process running on a respective compute block of at least two compute blocks (see paragraph [0038] and Fig. 2, CPU Process 224, GPU Process 228 and APU Process 234 are separately run on CPU 101, GPU 108 and APU 114);
manage allocations of virtual memory spaces for the least two compute blocks (see entire paragraphs [0037]-[0039] and Figs. 3-4 for MMU 111 managing the allocation of virtual memory spaces for CPU 101, GPU 108 and APU 114; note that in the depicted embodiment of Fig. 2 and paragraph [0038], one process is executing on each respective processing unit, as such the allocation of memory to each process amounts to the allocation of memory to each respective processing unit; also note that the instant claim appears to indicate that the virtual memory spaces allocated for the compute blocks are actually allocated to the processes) using an independent logical system separate from the at least two compute blocks (see Fog. 2, MMU 111); and
isolate the virtual memory spaces of the at least two processes by allowing each compute block to access only its own allocated virtual memory space (see entire paragraphs [0037]-[0039] and [0043], and Figs. 2-4, each process is isolated to its own key space and cannot access the key spaces of processes run on other processing units. For example, the APU process 234 running APU 114 and allocated to Key Space 2 cannot access Key Space 1, which is allocated to GPU Process 228 running on GPU 108).
Per claim 9, the claim is the non-transitory computer-readable medium storing computer-executable instructions for performing steps corresponding to those performed by claim 1’s computing system (see Sell, paragraph [0064] and exemplary claims 15-20 for computer readable instructions stored in computer readable storage medium). As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 17, the claim is the method performing steps corresponding to those performed by claim 1’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Dependent Claims:
Per claim 2, Sell further teaches the process isolation ensures that each job only has access to resources specifically allocated to each job (see entire paragraphs [0037]-[0039] and [0043], and Figs. 2-4, each process is isolated to its own key space and cannot access the key spaces of processes run on other processing units. Here the claimed “resources” are interpreted as allocated key space).
Per claim 3, Sell further teaches computer-executable instructions to generate metadata for each process, wherein the metadata is attached to a virtual address space and is not accessible to a compute block (see paragraph [0039] for different encryption keys for different processes, each encryption key used to isolate a process to a virtual address space/Key Space).
Per claim 4, Sell further teaches the computer-executable instructions is further configured to protect the system network from side channel attacks by ensuring that each compute block remains unaware of physical memory information (see paragraph [0043] and Figs. 3-4, each of the CPU Process 224, GPU Process 228 and APU Process address the virtual address space without directly addressing the physical memory space. Physical memory space is accessed through translation in MMU 111. Side channel attacks are prevented by isolating each process to a Key Space through encryption so that no compromised process can gain access to physical memory storing data associated with other processes).
Per claim 5, Sell further teaches the independent logical system manages a Global Address Space (GAS) comprised of a number of address bits, wherein a job in the computing environment is exposed to first address bits for all data belonging to the job (see paragraphs [0050]-[0054] and Figs. 6-7, the system address space of the virtual address system uses the first few address bits for addressing the Key Spaces allocated to each process, as such each process allocated to a Key Space is exposed to the first few address bits designating that Key Space).
Per claim 6, Sell further teaches other address bits of the GAS encode an extended address space comprising metadata fields, wherein the metadata fields include at least one of user identification, access control list properties, media type, access interleaving granularity (see Fig. 7 and paragraph [0055], bits 36:0 of an address designate an extended address space, and bits 9:8 is interleave select), security rules, and encryption requirements.
Per claim 7, Sell further teaches the independent logical system comprises components for performing virtual address translation, job isolation, metadata field management, data encryption and decryption, and access rule checks and security management (see paragraphs [0037]-[0039], [0043], [0050]-[0053] and [0055], and Figs. 5-7, MMU 111 and Memory Controller 113 are responsible for virtual address translation, process isolation to Key Spaces, generating/managing hash values, encryption and decryption using Key values corresponding to the Key Spaces, and providing access rule checks and security management by isolating processes to their allocated Key Spaces and preventing compromised process from gaining access to physical memory storing data associated with other processes).
Per claim 8, Sell further teaches the computer-executable instructions is further configured to enable flexible selection of metadata fields to help in reducing packet size and improve system performance (see paragraph [0053] for choosing to use ‘d’ number of address bits or ‘c’ number of address bits to design a page, resulting in different page sizes; here page sizes are interpreted as the claimed packet size, and the address bits are interpreted as metadata fields).
Per claim 10, the claim is the non-transitory computer-readable medium storing computer-executable instructions for performing steps corresponding to those performed by claim 2’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 11, the claim is the non-transitory computer-readable medium storing computer-executable instructions for performing steps corresponding to those performed by claim 3’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 12, the claim is the non-transitory computer-readable medium storing computer-executable instructions for performing steps corresponding to those performed by claim 4’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 13, the claim is the non-transitory computer-readable medium storing computer-executable instructions for performing steps corresponding to those performed by claim 5’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 14, the claim is the non-transitory computer-readable medium storing computer-executable instructions for performing steps corresponding to those performed by claim 6’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 15, the claim is the non-transitory computer-readable medium storing computer-executable instructions for performing steps corresponding to those performed by claim 7’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 16, the claim is the non-transitory computer-readable medium storing computer-executable instructions for performing steps corresponding to those performed by claim 8’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 18, the claim is the method performing steps corresponding to those performed by claim 2’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 19, the claim is the method performing steps corresponding to those performed by claim 3’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Per claim 20, the claim is the method performing steps corresponding to those performed by claim 4’s computing system. As such the claim is rejected on the same grounds mutatis mutandis.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN X GU whose telephone number is (571)272-0703. The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN X GU/
Primary Examiner
Art Unit 2138
3 February 2026