DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 06/13/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mori (JP 2006165100 A).
Regarding claim 1, Mori teaches a semiconductor chip (e.g. IC chip 22, figs.1-2) comprising:
a power transistor (i.e. N-channel power MOSFET 2, figs.1-2);
a plurality of pads (page 4, A plurality of pads 4 corresponding to the drain (main terminal) of the MOSFET 2 and a plurality of pads 5 corresponding to the source (main terminal));
a plurality of wirings each configured to provide electrical continuity between each of the plurality of pads and one end of the power transistor (page 4, Of the source pads 5 of the MOSFET 2, the three pads 5 formed at positions facing the shunt resistor 23 (on the left end side of the pad row) are connected to the terminals 8 via bonding wires 6) (page 4, shunt resistor 23 is the third-layer aluminum wiring); and
a current detection circuit (i.e. control circuit 3, figs.1-2) configured to detect (page 5, high current detection accuracy can be secured), as a sense voltage, at least one of voltage drops occurring in the plurality of wirings, respectively, according to a shunt current flowing through each of the plurality of wirings and a wiring resistance component of each of the plurality of wirings (page 4, the terminal 11 can be used as a voltage detection terminal) (page 5, current flows uniformly spreading in the width direction of the shunt resistor 23. Thereby, the increase in heat generation is suppressed and high current detection accuracy can be secured).
Regarding claim 2, Mori teaches the semiconductor chip according to claim 1, wherein a wiring which is among the plurality of wirings and from which the sense voltage is extracted is laid on an element forming region of the power transistor (e.g. shunt resistor wire 23 overlaps pad 5 of MOSFET 2, fig.1).
Regarding claim 3, Mori teaches the semiconductor chip according to claim 1, wherein a wiring which is among the plurality of wirings and from which the sense voltage is extracted has the wiring resistance component (page 4, the shunt resistor 23 having an accurate resistance value can be produced) larger than those of remaining wirings (it is necessarily true that shunt resistor 23 has a larger/ controllable resistance compared to bonding wire 6, figs.1-2).
Regarding claim 6, Mori teaches the semiconductor chip according to claim 1, wherein the current detection circuit is provided on at least one of an input side and an output side of the power transistor (e.g. control circuit 3 is connected to the source/ output side of power transistor 2, fig.2).
Regarding claim 7, Mori teaches the semiconductor chip according to claim 1, wherein the current detection circuit is an overcurrent protection circuit configured to detect the sense voltage and limit an output current flowing through the power transistor (page 2, a semiconductor device having an IC chip in which a resistor for current detection is formed).
Regarding claim 8, Mori teaches the semiconductor chip according to claim 7, wherein the current detection circuit includes a comparator (i.e. operational amplifier 31, fig.2) configured to compare the sense voltage or a voltage corresponding to the sense voltage with a predetermined threshold voltage to generate an overcurrent protection signal (page 2, It can be suppressed and high current detection accuracy can be secured).
Regarding claim 9, Mori teaches the semiconductor chip according to claim 1, further comprising: a driver configured to drive and control the power transistor (page 3, operates as a high side switch) such that an output voltage output from the power transistor or a feedback voltage corresponding to the output voltage agrees with a reference voltage (page 4, the terminal 11 can be used as a voltage detection terminal).
Regarding claim 10, Mori teaches a semiconductor device (page 3, The IC 21 (corresponding to a semiconductor device) fixes an IC chip 22 (corresponding to a semiconductor chip) to a lead frame) comprising: the semiconductor chip according to claim 1; a plurality of external electrodes (page 3, terminals 7, 8, 11, 12 of the lead frame); and a wire configured to provide bonding between the plurality of external electrodes and the plurality of pads (page 3, They are assembled by connecting with wires 6).
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, Mori (JP 2006165100 A) teaches the semiconductor chip according to claim 1.
Mori does not teach, wherein the power transistor is divided into a plurality of unit transistors whose control terminals are each connected in common to each other.
Prior art Bryant (WO 2017186609 A1), Kao (US 7852054 B2), Muto (US 20180182719 A1) and Nakajima (US 20080232017 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the power transistor is divided into a plurality of unit transistors whose control terminals are each connected in common to each other.”
Claim 5 is indicated as allowable, as it depends on allowable claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 05/13/2026
Prosecution Insights