DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA and is in response to the amendments filed on 12/12/2025. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 103 as being unpatentable over Padmanabha et al (Trace Based Phase Prediction For Tightly-Coupled Heterogeneous Cores; MICRO’46, Dec 7-11, 2013) in view of Dumitrescu et al (U.S. Pub. 2018/0107766).
Padmanabha and Dumitrescu references have been previously presented.
As per claim 1 Padmanabha teaches the invention substantially as claimed including an integrated circuit comprising: a plurality of functional blocks, each configured to process one or more work blocks (pg. 450 right col section 4, pg. 451 left col. Table 1, first paragraph; pg. 447 right col. section 3, pg. 448 section 3.2 1st paragraph, pg. 449 left col. 1st paragraph, Fig. 5 super-trace, which are code sequences or basic blocks, that are scheduled for execution on big.LITTLE ARM cores); and circuitry configured to:
assign the first work block to a first functional block of the plurality of functional blocks that provides higher performance than one or more other functional blocks of the plurality of functional blocks, in response to the first work block including a first type of workload (pg. 449 right col. last paragraph, pg. 450 left col. 1st paragraph: super-trace that is compute-intensive is scheduled to run on Big out-of-order backend, which has better performance than Little backend); and execute the first work block on the first functional block (pg. 453 1st paragraph and 2nd paragraph, Fig. 11 and 12).
Padmanabha does not explicitly teach each function block representing an instantiated copy of integrated circuitry configured to process one or more work blocks; and receive a first work block.
However, Dumitrescu teaches each function block representing an instantiated copy of integrated circuitry configured to process one or more work blocks ([0018], [0019] logical cores are instantiated on physical cores and they are used to execute function blocks of applications); and receive a first work block ([0019] application are hosted on a computing system for execution, that means that the application is obvious received by the computing system).
It would have been obvious to one with ordinary skill in the prior to the effective filling date of the invention to combine the teachings of Dumitrescu and Padmanabha because both are directed towards mapping of different parts of applications on different processor cores. One with ordinary skill in the art would be motivated to incorporate the teachings of Dumitrescu into that of Padmanabha because Dumitrescu further improves efficiency of mapping of different parts of applications on different processor cores ([0003]).
As per claim 2 Padmanabha teaches wherein the circuitry is further configured to assign a second work block different from the first work block to a second functional block of the plurality of functional blocks that provides lower performance than one or more other functional blocks of the plurality of functional blocks, in response to the second work block including a second type of workload different from the first type of workload (pg. 449 right col. last paragraph, pg. 450 left col. 1st paragraph: super-trace that is compute-intensive is scheduled to run on Big out-of-order backend, which has better performance than Little backend; and memory intensive super-trace is scheduled on Little backend, which has decreased performance).
As per claim 3 Padmanabha teaches wherein the first type of workload is a computation intensive workload (pg. 450 left col. 1st paragraph).
As per claim 4 Padmanabha teaches wherein the second type of workload is a memory access intensive workload (pg. 450 left col. 1st paragraph).
As per claim 5 Padmanabha teaches wherein the circuitry is further configured to identify a performance level of one or more of the plurality of functional blocks based on identifiers of the plurality of functional blocks (pg. 449 section 3.3).
As per claim 6 Padmanabha teaches wherein the circuitry is further configured to identify a performance level of one or more work blocks based on monitored behavior of the one or more work blocks during previous execution of the one or more work blocks using the plurality of functional blocks (pg. 449 sections 3.3 and 3.4).
As per claim 7 Padmanabha wherein the circuitry is further configured to maintain a plurality of mappings between identifiers of one or more work blocks and identifiers of corresponding functional blocks of the plurality of functional blocks (pg. 449 section 3.3).
As per claims 8-14, they are reworded method versions of claims 1-7. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claims 1-7, respectively. In particular Dumitrescu teaches a scheduler that performs receiving and assigning steps of claim 1 ([0021] core mapping logic which is part of the computing system that hosts/receives applications for execution is responsible for assigning functional blocks of applications to logical cores).
As per claims 15-20, they are reworded system versions of claims 1-4, 6 and 7. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claims 1-4, 6 and 7, respectively. In particular Dumitrescu teaches a scheduler that performs receiving and assigning steps of claim 1, and a plurality of chiplets that executes the work blocks ([0021] core mapping logic which is part of the computing system that hosts/receives applications for execution is responsible for assigning functional blocks of applications to logical cores; [0018], [0020] logical cores are a form of chiplets).
Response to Arguments
Applicant’s arguments Applicant's arguments filed on 12/12/2025 have been considered but they are not persuasive.
Response for arguments for 35 U.S.C. 103 issues:
With regard to applicant’s argument for claim 1 that:
" Claim 1 recites "a plurality of functional blocks, each representing an instantiated copy of integrated circuitry configured to process one or more work blocks." The specification explains that these functional blocks are replicated (or instances of) semiconductor dies, each a copy of the same integrated circuitry, whose performance characteristics may vary due to manufacturing variations. (See, e.g., para. 14).
Padmanabha does not teach this. Padmanabha describes a heterogeneous big.LITTLE architecture, in which "super-traces that are compute-intensive are scheduled to run on Big out-of- order backend," while others run on Little cores. See the OA's own citations to Padmanabha at pg. 449-450. This is intentional architectural heterogeneity, not replicated copies of the same circuitry. Big and LITTLE cores differ by design, not by manufacturing variation. Padmanabha therefore does not teach "instantiated copies" of the same integrated circuitry as recited.
Likewise, Dumitrescu does not teach this limitation. Dumitrescu describes logical cores and functional blocks of applications mapped to those logical cores. Logical cores are software- visible execution contexts; they are not hardware copies of circuitry. For example, Dumitrescu describes "[0018] logical cores are instantiated on physical cores." This disclosure says nothing about instantiated copies of integrated circuitry. No replicated hardware blocks appear in Dumitrescu's disclosure.
Accordingly, neither reference teaches nor suggests a plurality of hardware blocks that are instantiated copies of identical circuitry, as recited in claim 1 (emphasis added by examiner).
The examiner respectfully disagrees.
Firstly, the examiner did not rely on Padmanabha reference to teach that each functional blocks being an instantiated copy of integrated circuitry. Instead the examiner relied on Dumitrescu to teach that each functional blocks being an instantiated copy of the integrated circuitry. As such, applicant’s arguments with regard to the Padmanabha reference is moot.
Secondly, as the examiner has emphasized above, applicant’s argument relied on details that are presented only in the specification but not in the claim themselves. In particular, while the above mentioned paragraph 14 of the specification mentions that the “functional blocks… each a copy of the same integrated circuitry, whose performance characteristics may vary due to manufacturing variations”. Such detail is not in the claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As such, under Broadest Reasonable Interpretation (BRI) for someone with ordinary skill in the art, the claims are not limited to having the “functional blocks” being “a plurality of hardware blocks that are instantiated copies of identical circuitry”; or that the “functional blocks” may have different performance characteristics due to “manufacturing variations”; instead, the functional blocks can be entirely software in nature, such as a logical or virtual processor that may or may not have different features. Since such software entity could also be a representation of “an instantiated copy of integrated circuitry configured to process on or more work blocks” of claim 1.
Furthermore, under BRI, the above mentioned paragraph 14 of the specification does not preclude the “functional blocks” of the specification from being software in nature. For example, paragraph [0079] of the specification mentions that “Additionally, in various implementations, program instructions include behavioral-level descriptions or register-transfer level (RTL) descriptions of the hardware functionality in a high level programming language such as C, or a design language (HDL) such as Verilog, VHDL, or database format such as GDS II stream format (GDSII). In some cases the description is read by a synthesis tool, which synthesizes the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represent the functionality of the hardware including the system.” This means that under BRI, in some implementations the functional blocks of the specification can be software that describe the functional blocks.
Finally, in light of the above two responses of the examiner, one with ordinary skill in the art, under BRI, could see that the logical cores of Dumitrescu can indeed be the “plurality of functional blocks, each representing an instantiated copy of integrated circuitry configured to process one or more work blocks” of claim 1 (as the examiner has previously presented in examiner’s previous office action). This is because, as mentioned above by the examiner, the functional blocks can be software in nature, and that any differences between the functional blocks can be due to differences in software features.
With regard to applicant’s argument for claim 1 that:
" In addition to the above, claim 1 further recites the features "assign the first work block to a first functional block ... that provides higher performance than one or more other functional blocks ... in response to the first work block including a first type of workload." The specification explains that the performance differences between functional blocks arise from manufacturing variation, and that work blocks are scheduled according to performance bins. In contrast, Padmanabha's scheduling is based on architectural class, not manufacturing variation(s). The Office Action relies on Padmanabha's teachings regarding compute-intensive super-traces being assigned to Big cores and memory-intensive ones to Little cores. But these assignments are based on architectural differences (big vs. LITTLE), not by differences among replicated copies of the same circuitry. Padmanabha does not disclose replicated hardware blocks, manufacturing-induced performance variation, or scheduling decisions based on such variation.
Dumitrescu provides no teaching of hardware performance bins. Dumitrescu discusses determining throughput for software functional block assignments. (See, e.g., [0038]-[0041]). Again, these are software-level performance evaluations, not hardware-level scheduling across replicated silicon blocks.
Accordingly, the cited art does not teach or suggest the claimed scheduling mechanism whether taken singly or in combination.
For the reasons set forth above, the combination of Padmanabha and Dumitrescu does not teach or suggest the limitations of claim 1, and the proposed combination is based on unsupported hindsight (emphasis added by examiner).
The examiner respectfully disagrees.
As the examiner has explained in examiner’s response to applicant’s first argument (above), applicant’s argument (emphasized by the examiner) relied on details that are presented only in the specification but not in the claim themselves. In particular, while the specification explains that in some implementations “the performance differences between functional blocks arise from manufacturing variations, and that work blocks are scheduled according to performance bins”. Such detail is not in the claims. As such, under BRI, the performance differences of the claims are not limited to those that arise from manufacturing variations, instead the performance differences of the claims can be due to architectural class differences, which Padmanabha reference teaches.
The applicant’s argument is also based on the suggestion that the “functional blocks” are “replicated copies of the same circuitry”. However, the limitation (of claim 1) of “a plurality of functional blocks, each representing an instantiated copy of integrated circuitry configured to process one or more work blocks” does not limit the functional blocks to be replicated copies of the same circuitry. Instead under BRI, the functional block can be any versions (software or hardware) of any kinds of processors. Since processors of different kind can all be “integrated circuitry configured process one or more work blocks.” As such the functional blocks of the claims can be copies of different kinds of processors.
Even if one or to limit the interpretation of the “functional blocks” to be “replicated copies of the same circuitry”. Dumitrescu reference, which the examiner has previously used to teach “each function block representing an instantiated copy of integrated circuitry configured to process one or more work blocks”, under BRI, still teaches this limited interpretation in [0018]: in some embodiments, two or more physical cores 104-1, 104-2, … , 104-M may be duplicated… and shared by the logical cores associated with the physical core. This means that the logical cores can have the same underlying hardware, thus making them “replicated copies of the same circuitry”.
Therefore, Padmanabha as modified by Dumitrescu teaches the features of “assign the first work block to a first functional block ... that provides higher performance than one or more other functional blocks ... in response to the first work block including a first type of workload (please see details in U.S.C. 103 section above).”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BING ZHAO/Primary Examiner, Art Unit 2151