DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA and is in response to the amendments filed on 04/13/2026. Claims 1-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/13/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
The following claim languages are not clear and indefinite:
As per claim 1, 8 and 15 it is not clear if the “circuitry” or the “scheduler” is part of a “processing circuit” or it is outside of all of the “processing circuits”.
The dependent claims do not cure the 112(b) issues of their respective parent claims. Therefore, they are rejected for the same reasons as those presented for their respective parent claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5-9, 12-16, 19 and 20 are rejected under 102(a)(1)(2) as being unpatentable over Therien et al (U.S. Pat. 11409577).
As per claim 1 Therien teaches the invention as claimed including an integrated circuit comprising: a plurality of functional blocks processing circuits, each representing being an instantiated copy of a same integrated circuitry, wherein a first processing circuit of the plurality of processing circuits provides a higher performance level than a second processing circuit of the plurality of processing circuits (col 5 lines 7-15, col 8 lines 16-25 identical cores are differentiated at manufacturing time based on their differences in physical characteristics); and
circuitry configured to: receive a first work block associated with a first workload type (col 5 lines 7-31, col 7 lines 53-58, col 9 lines 47-51, 60- col 10 line 5; col 11 lines 49-55 module is configured to evaluate each thread, which have different types of demands, determined based on things like whether or not the thread is from a user selected application or foreground application); and
cause the first work block to be executed by one of the plurality of processing circuits based on the first workload type and relative performance levels of the plurality of processing circuits (col 9 line 59 – col 10 line 6, col 12 lines 3-11 thread with highest type of demand will be ranked first in a sorted tracker list, and it is affinitized to the core with highest performance).
As per claim 2 Therien teaches wherein the circuitry is further configured to: receive a second work block associated with a second workload type different from the first workload type; and cause the second work block to be executed by a processing circuit of the plurality of processing circuits having a lower performance level than another processing circuit of the plurality of processing circuits based on the second workload type and the relative performance levels of the plurality of processing circuit (col 9 line 59 – col 10 line 6, col 12 lines 3-11 thread with 2nd highest type of demand will be ranked second in a sorted tracker list, and it is affinitized to the core with second highest performance).
As per claim 5 Therien teaches wherein the circuitry is further configured to identify a performance level of one or more of the plurality of functional blocks processing circuits based on stored characterization data associated with respective identifiers of the plurality of processing circuits, the stored characterization data indicating performance differences among the plurality of processing circuits arising from manufacturing variation identifiers of the plurality of functional blocks (col 8 lines 17-25, col 12 lines 18-25).
As per claim 6 Therien teaches wherein the circuitry is further configured to identify a workload type of one or more work blocks based on monitored behavior of the one or more work blocks during previous execution of the one or more work blocks by the plurality of processing circuits a performance level of one or more work blocks based on monitoring behavior of the one or more work blocks during previous execution of the one or more work blocks using the plurality of functional blocks (col 7 lines 33-44; col 9 lines 5-32 demand calculation are performed periodically).
As per claim 7 Therien teaches wherein the circuitry is further configured to maintain, in memory of the integrated circuit, a plurality of mappings between identifiers of one or more work blocks and corresponding workload types or corresponding ones of the plurality of processing circuits (col 9 lines 7-32, 35-52, col 8 lines 27-64 threads and their associated demands are tracked in a tracker list).
As per claims 8, 9 and 12-14, they are reworded method versions of claims 1, 2 and 5-7. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claims 1, 2 and 5-7, respectively. In particular Therien teaches a scheduler that performs receiving and assigning steps of claim 1 (col 5 lines 7-23).
As per claims 15,16, 19 and 20, they are reworded system versions of claims 1, 2, 4, 6 and 7. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claims 1, 2, 4, 6 and 7, respectively. In particular Therien teaches a scheduler that performs receiving and assigning steps of claim 1 (col 5 lines 7-23), and a plurality of chiplets that executes the work blocks (col 8 lines 17-25, col 3 lines 51-59 processing cores are part of a processor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 10, 11, 17 and 18 are rejected under 103 as being unpatentable over Therien et al (U.S. Pat. 11409577) in view of Lu (U.S. Pub. 2016/0266929).
As per claim 3 Therien does not explicitly teach wherein the first workload type is a computation intensive workload type.
However, Lu teaches that the first workload type is a computation intensive workload type ([0070]).
It would have been obvious to one with ordinary skill in the prior to the effective filling date of the invention to combine the teachings of Lu and Therien because both are directed towards scheduling of multi-core processors. One with ordinary skill in the art would be motivated to incorporate the teachings of Lu into that of Therien because Lu further improves efficiency of scheduling of multi-core processors ([0004], [0005]).
As per claim 4 Lu teaches wherein the second type of workload type is a memory access intensive workload type ([0070] I/O-intensive application is a type of memory access intensive workload).
As per claims 10 and 11, they are reworded method versions of claims 3 and 4. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claims 3 and 4, respectively.
As per claims 17 and 18, they are reworded system versions of claims 3 and 4. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claims 3 and 4, respectively.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BING ZHAO whose telephone number is (571)270-1745. The examiner can normally be reached 9:30am - 6pm.
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/BING ZHAO/Primary Examiner, Art Unit 2151
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