Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-26 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the usage of “when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue exists in the write queue logic circuit” is unclear in this context. The arithmetic queue and arithmetic write queue are previously claimed to be comprised/stored within the PIM controller, therefore they already exist within the scope of the claim. This phrasing raises the question of what is encompassed, or what is intended to be encompassed by the claim. Appropriate correction is required.
Claim 2, and similarly claim 13, 18-19, recites the limitation "the flag". There is insufficient antecedent basis for this limitation in the claim.
Claim 16, and similarly claim 17, recites the limitation "the flags". There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 2, the usage of “wherein the scheduling logic circuit is configured to determine whether the arithmetic queue is exist in the read/arithmetic queue logic circuit” is unclear in this context. The arithmetic queue is previously claimed to be comprised/stored within the PIM controller, therefore it already exists within the claim. Further, the phrase “is exist” is grammatically incorrect.
Regarding claim 3, and similarly for claims 4, 13-15, 24-25, the usage of “when the arithmetic queue exists” (or is “absent”) is unclear in this context. The arithmetic queue is previously claimed to be comprised/stored within the PIM controller, therefore it already exists within the scope of the claim.
Regarding claim 11, and similarly for claims 13, 22, the usage of “when the read queue or arithmetic queue is stored” is unclear in this context. The arithmetic queue is previously claimed to be comprised/stored within the PIM controller, therefore it is already stored within the scope of the claim.
Claims 5-12, 20-21, 23, 26 are rejected for being dependent upon a rejected parent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Walker et al., US Patent Application Publication 2011/0093665 (hereinafter Walker) in view of Terry et al., US Patent Application Publication 2019/0188133 (hereinafter Terry).
Regarding claim 1, Walker teaches:
A processing-in-memory (PIM) controller configured to control a PIM device having a memory function and an arithmetic function (see e.g. fig. 2, 3, para. [0026-31], sequencer/fetch/memory control logic to control the PIM device), the PIM controller comprising: a read/arithmetic queue logic circuit configured to store a read queue and an arithmetic queue (see e.g. fig. 2, 3, para. [0026-31], a buffer(s) for read requests and arithmetic instructions), the read queue being a request for reading data out of the PIM device (see e.g. fig. 2, 3, para. [0029], requests to read data from memory), and the arithmetic queue being a request for arithmetic operation of the PIM device (see e.g. fig. 2, 3, para. [0026-31], arithmetic instructions to be executed); a write queue logic circuit configured to store a write queue for requesting to write data in the PIM device, the write queue including a memory write queue for storing data in the PIM device, and an arithmetic write queue for storing data necessary for the arithmetic operation performed in the PIM device (see e.g. fig. 2, 3, para. [0026-41], buffer circuitry for storing write requests and data for arithmetic instructions); and a scheduling logic circuit configured to perform a scheduling operation by adjusting an output sequence of the read queue, the arithmetic queue, and the write queue (see e.g. fig. 2, 3, para. [0026-41], sequencer/fetch/memory control logic schedules the instructions/data to be output based on control signals at certain levels that are transmitted to the buffer(s)), wherein the scheduling logic circuit is configured to perform the scheduling operation when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue exists in the write queue logic circuit (see e.g. fig. 2, 3, para. [0026-41], sequencer/fetch/memory control logic schedules instructions and their data when those instructions and data exist).
Walker fails to explicitly teach performing the scheduling operation such that the write queue logic circuit outputs the arithmetic write queue before the read/arithmetic queue logic circuit outputs the arithmetic queue.
Terry teaches sending data for an instruction before sending the instruction (see e.g. para. [0006]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Walker and Terry to perform the scheduling operation such that the write queue logic circuit outputs the arithmetic write queue before the read/arithmetic queue logic circuit outputs the arithmetic queue. This would have allowed for sending some instruction data into the pipeline early to preemptively process control information or conditional processing required to execute the instruction and reduce execution delays.
Regarding claim 24, Walker in view of Terry teaches or suggests:
The PIM controller of claim 1, wherein the scheduling logic circuit performs the scheduling operation such that the arithmetic write queue, the arithmetic queue, and the read queue are sequentially outputted when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue exists in the write queue logic circuit; wherein the scheduling logic circuit performs the scheduling operation such that the arithmetic queue, the read queue, and the write queue are sequentially outputted when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue is absent from the write queue logic circuit; and wherein the scheduling logic circuit performs the scheduling operation such that the read queue and the write queue are sequentially outputted when the arithmetic queue is absent from the read/arithmetic queue logic circuit (see e.g. Walker fig. 2, 3, para. [0026-42], Terry para. [0006], data from buffers can be output sequentially on clock cycles, and is done based on the data being present).
Claims 2-7, 9-18, 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Walker in view of Terry, further in view of Lakshmanamurthy et al., US Patent Application Publication 2006/0069869 (hereinafter Lakshmanamurthy).
Regarding claim 2, Walker in view of Terry teaches or suggests:
The PIM controller of claim 1, wherein the read/arithmetic queue logic circuit includes a read/arithmetic queue storage region having a plurality of read/arithmetic queue entries, each of which stores the read queue or the arithmetic queue (see e.g. Walker fig. 2, 3, para. [0026-41], the buffer(s) has a multiple entries);
Walker in view of Terry fails to explicitly teach wherein the flag of a read/arithmetic queue entry in which the read queue is stored among the plurality of read/arithmetic queue entries is set to have a first binary number; wherein the flag of the read/arithmetic queue entry in which the arithmetic queue is stored among the plurality of read/arithmetic queue entries is set to have a second binary number; and wherein the scheduling logic circuit is configured to determine whether the arithmetic queue is exist in the read/arithmetic queue logic circuit based on a value of the flag of each of the plurality of read/arithmetic queue entries.
Lakshmanamurthy teaches using flags and other descriptors for queued data entries to indicate a mode, validity, count, etc. (see e.g. fig. 2, para. [0016-27]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Walker, Terry, and Lakshmanamurthy such that the flag of a read/arithmetic queue entry in which the read queue is stored among the plurality of read/arithmetic queue entries is set to have a first binary number; wherein the flag of the read/arithmetic queue entry in which the arithmetic queue is stored among the plurality of read/arithmetic queue entries is set to have a second binary number; and wherein the scheduling logic circuit is configured to determine whether the arithmetic queue is exist in the read/arithmetic queue logic circuit based on a value of the flag of each of the plurality of read/arithmetic queue entries. This would have provided a way of being able to quickly determine the type of information in a queue to ensure it was routed to the proper destination. This would have also allowed for prioritizing modes based on the number of entries of each type.
Regarding claim 3, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 2, wherein the read/arithmetic queue logic circuit is configured to generate and transmit an arithmetic mode signal having a first level to the scheduling logic circuit when the arithmetic queue exists in the read/arithmetic queue logic circuit (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]); wherein the scheduling logic circuit is configured to generate and transmit an arithmetic mode enablement signal having the first level to the read/arithmetic queue logic circuit in response to receiving the arithmetic mode signal having the first level; and wherein the read/arithmetic queue logic circuit is configured to output the arithmetic queue in response to receiving the arithmetic mode enablement signal having the first level (see e.g. Walker fig. 2, 3, para. [0026-41], Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 4, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 3, wherein the read/arithmetic queue logic circuit is configured to generate and transmit the arithmetic mode signal having a second level to the scheduling logic circuit when the arithmetic queue is absent from the read/arithmetic queue logic circuit; wherein the scheduling logic circuit is configured to generate and transmit the arithmetic mode enablement signal having the second level to the read/arithmetic queue logic circuit in response to receiving the arithmetic mode signal having the second level; and wherein the read/arithmetic queue logic circuit is configured to output the read queue having an output priority in response to receiving the arithmetic mode enablement signal having the second level (see e.g. Walker fig. 2, 3, para. [0026-41], Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 5, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 3, wherein each of the plurality of read/arithmetic queue entries further includes an index having information on validity and an output sequence of the read queue or the arithmetic queue stored therein (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]), wherein the read/arithmetic queue logic circuit includes: a first arithmetic mode detector configured to receive the flag in each of the plurality of read/arithmetic queue entries to output the arithmetic mode signal (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]); a next read/arithmetic queue filter configured to receive the flag, the index, and the arithmetic mode enablement signal to generate and output a first arithmetic index signal; a next read/arithmetic queue selector configured to receive an output signal of the next read/arithmetic queue filter and the index in each of the plurality of read/arithmetic queue entries to generate a read/arithmetic queue selection control signal; and a read/arithmetic queue selection/output circuit configured to receive the read queues and the arithmetic queues from the read/arithmetic queue storage region to output one of the read queues and the arithmetic queues, which is selected by the read/arithmetic queue selection control signal (see e.g. Walker fig. 2, 3, para. [0026-41]).
Regarding claim 6, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 5, wherein the first binary number and the second binary number are “0” corresponding to a logic “low(0)” level and “1” corresponding to a logic “high(1)” level, respectively; and wherein the first arithmetic mode detector includes an OR gate for performing a logical OR operation of the flags of the read/arithmetic queue entries to output the result of the logical OR operation as the arithmetic mode signal (see e.g. Lakshmanamurthy fig. 2, para. [0016-27], Walker fig. 2, 3, para. [0026-41], the values must be either ‘1’ or ‘0’ in a binary computer system).
Regarding claim 7, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 5, wherein the next read/arithmetic queue filter is configured to: output the index of the read/arithmetic queue entry storing the arithmetic queue as the first arithmetic index signal when the flag and the arithmetic mode enablement signal have a logic “high(1)” level; and output the first arithmetic index signal having a logic “low(0)” level when at least one of the flag and the arithmetic mode enablement signal has a logic “low(0)” level (Lakshmanamurthy fig. 2, para. [0016-27], the mode determines what is output by the queue).
Regarding claim 9, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 5, wherein the next read/arithmetic queue selector is configured to: generate the read/arithmetic queue selection control signal for selectively outputting the arithmetic queue stored in the read/arithmetic queue entry having the index designated by the first arithmetic index signal when the first arithmetic index signal is outputted from the next read/arithmetic queue filter; and generate the read/arithmetic queue selection control signal for selectively outputting the read queue having an output priority according to the index when the first arithmetic index signal having a logic “low(0)” level is outputted from the next read/arithmetic queue filter (Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 10, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 5, wherein the read/arithmetic queue logic circuit further includes a first counter to count the total number of the read queues and the arithmetic queues stored in the read/arithmetic queue storage region to generate a first queue counted value (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 11, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 10, wherein the first counter is suitable for: performing a first operation that increases the first queue counted value by one to transmit the increased value of the first queue counted value to the scheduling logic circuit when the read queue or the arithmetic queue is stored in the read/arithmetic queue logic circuit; and performing a second operation that decreases the first queue counted value by one to transmit the decreased value of the first queue counted value to the scheduling logic circuit when the read queue or the arithmetic queue is outputted from the read/arithmetic queue logic circuit (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 12, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 11, wherein the first operation is performed in response to a first queue input control signal outputted from the scheduling logic circuit; and wherein the second operation is performed in response to a first queue output control signal outputted from the scheduling logic circuit (see e.g. Walker fig. 2, 3, para. [0026-41]).
Regarding claim 13, Walker in view of Terry teaches or suggests:
The PIM controller of claim 1, wherein the write queue logic circuit includes a write queue storage region having a plurality of write queue entries, each of which stores the memory write queue or the arithmetic write queue (see e.g. Walker fig. 2, 3, para. [0026-41]).
Walker in view of Terry fails to explicitly teach wherein the flag of a certain write queue entry of the plurality of write queue entries is set to have a first binary number when the memory write queue is stored in the certain write queue entry; wherein the flag of the certain write queue entry of the plurality of write queue entries is set to have a second binary number when the arithmetic write queue is stored in the certain write queue entry; and wherein the scheduling logic circuit is configured to determine whether the arithmetic write queue is exist in the write queue logic circuit based on a value of the flag of each of the plurality of write queue entries.
Lakshmanamurthy teaches using flags and other descriptors for queued data entries to indicate a mode, validity, count, etc. (see e.g. fig. 2, para. [0016-27]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Walker, Terry, and Lakshmanamurthy such that the flag of a certain write queue entry of the plurality of write queue entries is set to have a first binary number when the memory write queue is stored in the certain write queue entry; wherein the flag of the certain write queue entry of the plurality of write queue entries is set to have a second binary number when the arithmetic write queue is stored in the certain write queue entry; and wherein the scheduling logic circuit is configured to determine whether the arithmetic write queue is exist in the write queue logic circuit based on a value of the flag of each of the plurality of write queue entries. This would have provided a way of being able to quickly determine the type of information in a queue to ensure it was routed to the proper destination. This would have also allowed for prioritizing modes based on the number of entries of each type.
Regarding claim 14, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 13, wherein the write queue logic circuit is configured to generate and transmit an arithmetic write mode signal having a first level to the scheduling logic circuit when the arithmetic write queue exists in the plurality of write queue entries (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]); wherein the scheduling logic circuit is configured to generate and transmit an arithmetic write mode enablement signal having the first level to the write queue logic circuit in response to receiving the arithmetic write mode signal having the first level; and wherein the write queue logic circuit is configured to output the arithmetic write queue in response to receiving the arithmetic write mode enablement signal having the first level (see e.g. Walker fig. 2, 3, para. [0026-41], Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 15, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 14, wherein the write queue logic circuit is configured to generate and transmit the arithmetic write signal having a second level to the scheduling logic circuit when the arithmetic write queue is absent from the write queue logic circuit; wherein the scheduling logic circuit is configured to generate and transmit the arithmetic write enablement signal having the second level to the write queue logic circuit in response to receiving the arithmetic write signal having the second level; and wherein the write queue logic circuit is configured to output the memory write queue having an output priority in response to receiving the arithmetic write enablement signal having the second level (see e.g. Walker fig. 2, 3, para. [0026-41], Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 16, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 14, wherein each of the plurality of write queue entries further includes an index having information on validity and an output sequence of the memory write queue or the arithmetic write queue stored therein (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]); and wherein the write queue logic circuit includes: a second arithmetic mode detector configured to receive the flags of the plurality of write queue entries to output the arithmetic write signal (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]); a next write queue filter configured to receive the flag, the index, and the arithmetic mode enablement signal to generate and output a second arithmetic index signal; a next write queue selector configured to receive an output signal of the next write queue filter and the indexes of the plurality of write queue entries to generate a write queue selection control signal; and a write queue selection/output circuit configured to receive the memory write queues and the arithmetic write queues from the write queue storage region to output one of the memory write queues and the arithmetic write queues, which is selected by the write queue selection control signal (see e.g. Walker fig. 2, 3, para. [0026-41]).
Regarding claim 17, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 16, wherein the first binary number and the second binary number are “0” corresponding to a logic “low(0)” level and “1” corresponding to a logic “high(1)” level, respectively; and wherein the second arithmetic mode detector includes an OR gate for performing a logical OR operation of the flags of the write queue entries to output the result of the logical OR operation as the arithmetic write signal (see e.g. Lakshmanamurthy fig. 2, para. [0016-27], Walker fig. 2, 3, para. [0026-41], the values must be either ‘1’ or ‘0’ in a binary computer system).
Regarding claim 18, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 16, wherein the next write queue filter is configured to: output the index of the write queue entry storing the arithmetic write queue as the second arithmetic index signal when the flag and the arithmetic write enablement signal have a logic “high(1)” level; and output the second arithmetic index signal having a logic “low(0)” level when at least one of the flag and the arithmetic write enablement signal has a logic “low(0)” level (see e.g. Lakshmanamurthy fig. 2, para. [0016-27], the mode determines what is output by the queue).
Regarding claim 20, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 16, wherein the next write queue selector is configured to: generate the write queue selection control signal for selectively outputting the arithmetic write queue stored in the write queue entry having the index designated by the second arithmetic index signal when the second arithmetic index signal is outputted from the next write queue filter; and generate the write queue selection control signal for selectively outputting the memory write queue having an output priority according to the index when the second arithmetic index signal having a logic “low(0)” level is outputted from the next write queue filter (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 21, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 16, wherein the write queue logic circuit further includes a second counter to count the total number of the memory write queues and the arithmetic write queues stored in the write queue storage region to generate a second queue counted value (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 22, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 21, wherein the second counter is suitable for: performing a third operation that increases the second queue counted value by one to transmit the increased value of the first queue counted value to the scheduling logic circuit when the memory write queue or the arithmetic write queue is stored in the write queue logic circuit; and performing a fourth operation that decreases the second queue counted value by one to transmit the decreased value of the second queue counted value to the scheduling logic circuit when the memory write queue or the arithmetic write queue is outputted from the write queue logic circuit (see e.g. Lakshmanamurthy fig. 2, para. [0016-27]).
Regarding claim 23, Walker in view of Terry and Lakshmanamurthy teaches or suggests:
The PIM controller of claim 22, wherein the third operation is performed in response to a second queue input control signal outputted from the scheduling logic circuit; and wherein the fourth operation is performed in response to a second queue output control signal outputted from the scheduling logic circuit (see e.g. Walker fig. 2, 3, para. [0026-41]).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Walker in view of Terry, further in view of VanStee et al., US Patent Application Publication 2008/0183903 (hereinafter VanStee).
Regarding claim 25, Walker in view of Terry teaches or suggests:
The PIM controller of claim 1, wherein the scheduling logic circuit performs the scheduling operation such that the read queue and the write queue are sequentially outputted when the arithmetic queue is absent from the read/arithmetic queue logic circuit (see e.g. Walker fig. 2, 3, para. [0026-42], Terry para. [0006], data from buffers can be output sequentially on clock cycles, and is done based on the data being present).
Walker in view of Terry fails to explicitly teach wherein the scheduling logic circuit performs the scheduling operation such that the write queue has an output priority over the read queue until the number of the write queues stored in the write queue logic circuit becomes less than a maximum threshold value when the number of the write queues stored in the write queue logic circuit is equal to or greater than the maximum threshold value.
VanStee teaches conditionally performing read commands from a prefetch buffer depending on whether a predefined number is below a threshold (see e.g. para. [0041-3]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Walker, Terry, and VanStee such that the scheduling logic circuit performs the scheduling operation such that the write queue has an output priority over the read queue until the number of the write queues stored in the write queue logic circuit becomes less than a maximum threshold value when the number of the write queues stored in the write queue logic circuit is equal to or greater than the maximum threshold value. This would have provided a way of dynamically determining whether to execute certain commands to prioritize more critical commands or to conserve power such as discussed by VanStee (see para. [0029]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Walker in view of Terry, further in view of Acocella, US Patent 7,400,326 (hereinafter Acocella).
Regarding claim 26, Walker in view of Terry teaches or suggests:
The PIM controller of claim 1.
Walker in view of Terry fails to explicitly teach wherein when an address of the read queue transmitted to the read/arithmetic queue logic circuit is the same as an address of the write queue stored in the write queue logic circuit, data of the write queue stored in the write queue logic circuit are transmitted to a host and the read queue transmitted to the read/arithmetic queue logic circuit is not stored in the read/arithmetic queue logic circuit.
Acocella teaches that if duplicate addresses/transfers are detected, data can be forwarded/transmitted to a desired location rather than accessing additional storage (see e.g. col. 9 lines 20-60).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Walker, Terry, and Acocella such that when an address of the read queue transmitted to the read/arithmetic queue logic circuit is the same as an address of the write queue stored in the write queue logic circuit, data of the write queue stored in the write queue logic circuit are transmitted to a host and the read queue transmitted to the read/arithmetic queue logic circuit is not stored in the read/arithmetic queue logic circuit. This would have provided an advantage such as discussed by Acocella “to largely separate the data stream from the command stream, thereby reducing stalling of the data path while providing an efficient path for transferring a stream of state commands that includes wide commands (e.g., programs).” (see Acocella col. 15 lines 49-67).
Allowable Subject Matter
Claims 8 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if amended to overcome 112 rejections, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
McCormick, JR., US Patent Application Publication 2014/0195772, teaches dispatching a prefetch of data prior to sending an instruction which uses the data.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-30 of U.S. Patent No. 11,720,354 in view of Terry. Terry teaches sending data for an instruction before sending the instruction (see e.g. para. [0006]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Patent ‘354 and Terry to perform the scheduling operation such that the write queue logic circuit outputs the arithmetic write queue before the read/arithmetic queue logic circuit outputs the arithmetic queue. This would have allowed for sending some instruction data into the pipeline early to preemptively process control information or conditional processing required to execute the instruction and reduce execution delays.
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183