Prosecution Insights
Last updated: August 18, 2026
Application No. 18/334,828

PHASE MODULATED PULSE RADAR WITH ANALOG CORRELATOR

Final Rejection §103
Filed
Jun 14, 2023
Priority
Jun 16, 2022 — provisional 63/366,485
Examiner
MAKHDOOM, SAMARINA
Art Unit
3648
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Regents of the University of Minnesota
OA Round
4 (Final)
72%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
89 granted / 124 resolved
+19.8% vs TC avg
Strong +30% interview lift
Without
With
+30.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
60 currently pending
Career history
192
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
72.6%
+32.6% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 124 resolved cases

Office Action

§103
DETAILED ACTION Response to Amendment Applicant's submission filed on June 11, 2026 has been entered. Claims 1, 10 and 17 are amended. Claim 20 is cancelled. Claims 1-19 are pending this application. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-8, 10-15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo (WO 2012/166315 A2) in view of Iizuka (US 2005/0089122 A1). Regarding Claim 1, Matsuo teaches a radar system comprising [0035 for using pulse compression radar with binary phase shift keying]: receive circuitry configured to process an analog radar pulse that is digital phase modulated [0035 for using digitally modulate PCR with phase shift keying for encoded messages]; and correlator circuitry configured to: [0066-0067 for using multiplier to receive PCR pulse in the analog domain]; receive the analog radar pulse as mixed with the signal from the oscillator [0035, and 00118-0119 for demodulation filter 979 applies the FM carrier signal 972 in removing the carrier frequency from the reflected PCR signals] receive a bitstream to integrate the received radar pulse [0032-0033 and 0041 for received samples (pulse) for object detection with 0043 for using Barker Codes]; prior to digital conversion, perform a correlation function on the received radar pulse based on the bitstream [0041, 0043 and 0068 for using a integration to generate correlation signal] and output the correlated analog signal to digital conversion circuitry [0072 for using ADC]. Matsuo fails to explicitly teach a mixing circuitry configured to mix the received analog radar pulse with a signal from an oscillator. Iizuka has a correlator which can be adapted to a receiver for impulse radio includes a multiplier for multiplying a received impulse train by a received template train (abstract) and teaches a mixing circuitry configured to mix the received analog radar pulse with a signal from an oscillator [0039-0041 for using a correlator, quantizer and integrator with a template train and template generator]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the applicant’s invention for modifying the radar circuit techniques, as disclosed by Matsuo, further including the signal processing calculations as taught by Iizuka for the purpose to ensure further decrease of the quantization error (Iizuka, 0049). Regarding Claim 10, Matsuo teaches device implemented in circuitry comprising [0035 for using pulse compression radar with binary phase shift keying]: receive circuitry configured to process an analog radar pulse that is digital phase modulated [0035 for using digitally modulate PCR with phase shift keying for encoded messages]; correlator circuitry configured to: [0066-0067 for using multiplier to receive PCR pulse in the analog domain]; receive the analog radar pulse as mixed with the signal from the oscillator [0035, and 00118-0119 for demodulation filter 979 applies the FM carrier signal 972 in removing the carrier frequency from the reflected PCR signals] receive a bitstream to integrate the received radar pulse [0032-0033 and 0041 for received samples (pulse) for object detection with 0043 for using Barker Codes]; prior to digital conversion, perform a correlation function on the received radar pulse based on the bitstream [0041, 0043 and 0068 for using a integration to generate correlation signal] and output the correlated analog signal to digital conversion circuitry [0072 for using ADC]. Matsuo fails to explicitly teach a mixing circuitry configured to mix the received analog radar pulse with a signal from an oscillator. Iizuka has a correlator which can be adapted to a receiver for impulse radio includes a multiplier for multiplying a received impulse train by a received template train (abstract) and teaches a mixing circuitry configured to mix the received analog radar pulse with a signal from an oscillator [0039-0041 for using a correlator, quantizer and integrator with a template train and template generator]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the applicant’s invention for modifying the radar circuit techniques, as disclosed by Matsuo, further including the signal processing calculations as taught by Iizuka for the purpose to ensure further decrease of the quantization error (Iizuka, 0049). Regarding Claim 17, Matsuo teaches a method comprising [0035 for using pulse compression radar with binary phase shift keying]: receiving, by correlator circuitry, the analog pulse as mixed with the signal from the oscillator [0035, and 00118-0119 for demodulation filter 979 applies the FM carrier signal 972 in removing the carrier frequency from the reflected PCR signals]; receiving, by the correlator circuitry a bitstream to decode the received radar pulse [0032-0033 and 0041 for received samples (pulse) for object detection with 0043 for using Barker Codes]; prior to digital conversion, performing by the correlator circuitry, a correlation function on the received radar pulse based on the bitstream to generate a correlated analog signal [0041, 0043 and 0068 for using an integration to generate correlation signal] and outputting the correlated analog signal to digital conversion circuitry [0072 for using ADC]. Matsuo fails to explicitly teach a mixing circuitry configured to mix the received analog radar pulse with a signal from an oscillator. Iizuka has a correlator which can be adapted to a receiver for impulse radio includes a multiplier for multiplying a received impulse train by a received template train (abstract) and teaches a mixing circuitry configured to mix the received analog radar pulse with a signal from an oscillator [0039-0041 for using a correlator, quantizer and integrator with a template train and template generator]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the applicant’s invention for modifying the radar circuit techniques, as disclosed by Matsuo, further including the signal processing calculations as taught by Iizuka for the purpose to ensure further decrease of the quantization error (Iizuka, 0049). Regarding Claim 2 and 12, Matsuo teaches the correlator circuitry comprises: a multiplier [0066-0068 for multipliers using multiplied signals]; and an integrator, wherein the combination of the multiplier and the integrator is configured to realize a transfer function of a linear matched filter [0039-0042 for using multiplier and integrator as well as 0068-0069]. Regarding Claim 3 and 13, Matsuo fails to explicitly teach the correlator circuitry further comprises: a quantizer, configured to receive the output from the integrator; a counter, configured to receive the output from the quantizer, wherein the quantizer and counter extend a linear dynamic range of the integrator. Iizuka has a correlator which can be adapted to a receiver for impulse radio (abstract) and teaches the correlator circuitry further comprises [0039 for integrator and quantizer for impulse train]: a quantizer, configured to receive the output from the integrator [0039, with 0042]; a counter, configured to receive the output from the quantizer, wherein the quantizer and counter extend a linear dynamic range of the integrator [0017 for using SNR for signal and 0021 to decrease quantizer error (dynamic range)]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the applicant’s invention for modifying the radar circuit techniques, as disclosed by Matsuo, further including the signal processing calculations as taught by Iizuka for the purpose to decrease quantization error outputted (Iizuka, 0017). Regarding Claim 4 and 14, Matsuo teaches the correlator is arranged to compress digital data based on the received analog radar pulse by sampling the received analog radar pulse [0072 also 0078 for fine tuning detection process]. Regarding Claim 5, Matsuo teaches the received analog radar pulse is a radar echo signal reflected from a target [0036-0037 for reflect PCR signal 164 travels the distance R back to the antenna]. Regarding Claim 6, Matsuo teaches the received analog radar pulse is received directly from a radar transmitter that transmits signals that are digital phase modulated [0045-0046 for initial PCR signal 133 can be prepared for transmission and be replicated at or around the same time]. Regarding Claim 7, Matsuo teaches the radar system comprises both the receive circuitry and the radar transmitter [0042 for radar with both transmitting and receiving antennas]. Regarding Claim 8 and 15, Matsuo teaches the bitstream received by the correlator circuitry is based on a transmitted radar pulse from a radar transmitter, and wherein the transmitted radar pulse is time delayed before the correlator circuitry receives the transmitted radar pulse [0061-0064 for using adjustable time delays]. Regarding Claim 11, Matsuo teaches the circuitry is implemented on an integrated circuit [0113 for circuit architectures]. Regarding Claim 18, Matsuo teaches the radar pulse is reflected from a target [0036-0037]. Regarding Claim 19, Matsuo teaches the bitstream is based on a transmitted radar pulse from transmit circuitry operatively coupled to the correlator circuitry, wherein the transmit circuitry is: configured to transmit the analog radar pulse via a transmit antenna, and the transmitted radar pulse is the digitally phase modulated radar pulse [0046-0047]. Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo et al (WO 2012/166315 A2) in view of Iizuka (US 2005/0089122 A1) and further in view of Kim (US 20130038401 A1) and Dandu et al (US 2020/0076380 A1). Regarding Claim 9 and 16, Matsuo fails to explicitly teach wherein the correlator circuitry receives the analog radar pulse via a power splitter. Kim has a balun includes a first port connected with a port connection part (abstract) and teaches wherein the correlator circuitry receives the analog radar pulse via a power splitter [0031]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the applicant’s invention for modifying the radar circuit techniques, as disclosed by Matsuo, further including the pulse calculations as taught by Kim for the purpose to synthesizing the signals having the phase difference (Kim, 0023). Matsuo fails to explicitly teach and a differential amplifier that drives two differential paths connected to the correlator circuitry, and wherein the differential amplifier provides reverse isolation to isolate the two differential paths. Dandu has differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node (abstract) and teaches and a differential amplifier that drives two differential paths connected to the correlator circuitry [0023-0024 for having a differential pair circuit deliver a differential output signal VO], and wherein the differential amplifier provides reverse isolation to isolate the two differential paths [0035 for using neutralization operation for isolation]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the applicant’s invention for modifying the radar circuit techniques, as disclosed by Matsuo, further including the pulse calculations as taught by Dandu for the purpose to reduces the differential amplifier gain across the illustrated frequency range (Dandu, 0035). Response to Arguments Applicant’s arguments with respect to claims 1-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In Applicant’s Arguments, page 7, fourth paragraph, applicant argues that Rao does not teach the correlator for the analog radar pulse. The Examiner appreciates the amendments to the independent claims, the current rejection is Matsuo in view of Iizuka. In Applicant’s Arguments, page 8, first paragraph, applicant argues that Rao does not teach performing functions prior to digital conversion. The Examiner respectfully disagrees: the combination of Matsuo with Iizuka teaches prior to digital conversion, perform a correlation function on the received radar pulse based on the bitstream [Matsuo, 0041, 0043 and 0068 for using a integration to generate correlation signal]. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMARINA MAKHDOOM whose telephone number is (703)756-1044. The examiner can normally be reached Monday – Thursdays from 8:30 to 5:30 pm eastern time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Resha Desai can be reached on 571-270-7792 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMARINA MAKHDOOM/ Examiner, Art Unit 3648 /RESHA DESAI/Supervisory Patent Examiner, Art Unit 3648
Read full office action

Prosecution Timeline

Show 7 earlier events
Jan 13, 2026
Response after Non-Final Action
Feb 11, 2026
Request for Continued Examination
Mar 02, 2026
Response after Non-Final Action
Mar 11, 2026
Non-Final Rejection mailed — §103
May 20, 2026
Applicant Interview (Telephonic)
May 20, 2026
Examiner Interview Summary
Jun 11, 2026
Response Filed
Jun 29, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+30.4%)
3y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 124 resolved cases by this examiner. Grant probability derived from career allowance rate.

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