DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/07/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Response to Amendment
This Office Action is in response to Applicant’s amendment filed on May 18, 2026. Claims 1, 3-4 and 6 have been amended. New claims 20-27 have been added. Claims 16-17 and 19 have been canceled. Currently claims 1-15,18 and 20-27 are pending.
Response to Arguments
Applicant's arguments with respect to claims 1 filed on 05/18/2026 have been fully considered but they are not persuasive. The reason is set forth below,
Regarding Amended claims 1, the applicant stated “In Cook et al., Fig. 2A illustrates "wiring layer (218)" and "first heat dissipation layer (230)" (reference numeral are those referred to in Cook et al.). Cook et al., however, fails to describe "protection circuit". Thus, Cook et al. in which there does not exist a "protection circuit" naturally cannot describe "a contact that is electrically connected to the protection circuit.”
However, primary prior art (US 20150255451 A1) “YASUSAKA et al.” already discloses a protection circuit and a layer (“The wiring pattern 114 of the wiring layer L2 corresponds to the above-described heat conductive member L2X (see FIG. 4C). In this manner, in the semiconductor device including three (or more) wiring layers, since a vertical distance between the uppermost wiring layer and the heat detection element is large, a middle or lower wiring layer may be used to stack the heat conductive members in the vertical direction.” ¶ [0062]) and the secondary prior art (US 20180151471 A1) “Cook et al” is brought into to show that the layer is a heat dissipation layer with a motivation to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance. Moreover, the protection circuit of YASUSAKA et al. includes a bipolar transistor 31 (¶ [0047]), and the heat removal circuit of Cook et el. also can include bipolar junction transistors (¶ [0024]).
Furthermore, upon further search, newly found prior art (US 7751164 B1) “Jin et al.” discloses the added limitations “wherein the protection circuit is configured to protect the semiconductor element against noise.” for amended claim 1.
For the stated reasons above a final rejection has been made using YASUSAKA, Makoto (US 20150255451 A1) “YASUSAKA et al.” in view of Cook, Benjamin Stassen (US 20180151471 A1) “Cook et al” further in view of Jin, Xiaodong (US 7751164 B1) “Jin et al.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION. - The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 15 recited “where the first heat dissipation with at least a part of the protection circuit” which should be “where the first heat dissipation layer overlaps with at least a part of the protection circuit”. For examination purposes, this will be interpreted as “where the first heat dissipation layer overlaps with at least a part of the protection circuit”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1-4, 7-8, 15 and 18, 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over YASUSAKA, Makoto (US 20150255451 A1) “YASUSAKA et al.” in view of Cook, Benjamin Stassen (US 20180151471 A1) “Cook et al” further in view of Jin, Xiaodong (US 7751164 B1) “Jin et al.”.
Regarding Independent Claim 1, YASUSAKA et al. Figs. 1-5 discloses a semiconductor apparatus (“a semiconductor device” ¶ [0032]), comprising:
a semiconductor layer (“a semiconductor substrate” ¶ [0034]) having a first surface (Top Surface of the substrate aligned with the top surface of transistor 10 in Fig. 5) and a second surface (Bottom surface of substrate in Fig. 5) and including, between the first surface and the second surface,
a semiconductor element (“a P channel type MOS (Metal Oxide Semiconductor) field effect transistor 10” ¶ [0033]) and
a protection circuit (“an overheat protection circuit 30” ¶ [0033]);
a wiring layer disposed at a first-surface side of the semiconductor layer (“a wiring pattern 112” ¶ [0061]) and electrically connected to the protection circuit (“a wiring pattern 112 electrically connected to a transistor 31 (heat detection element)” ¶ [0061]) or a plurality of wiring layers (“The first (lower) wiring layer L1 includes a wiring pattern 111 electrically connected to a transistor 10 (heat source) and a wiring pattern 112 electrically connected to a transistor 31 (heat detection element). The second (middle) wring layer L2 includes a wiring pattern 113 formed on the wiring pattern 111, and a wiring pattern 114 formed on the wiring pattern 112. The third (upper) wiring layer L3 includes a wiring pattern 115 formed across both of the transistor 10 (heat source) and the transistor 31 (heat detection element). The wiring pattern 111 and the wiring patterns 113, the wiring pattern 113 and the wiring patterns 115, and the wiring pattern 114 and the wiring patterns 115 are respectively electrically interconnected through vias 116 to 118, respectively.” ¶ [0061]) disposed at a first-surface side of the semiconductor layer and electrically connected to the protection circuit, the first-surface side being a side where the first surface is located; and
a first heat dissipation layer (“The wiring pattern 114 of the wiring layer L2 corresponds to the above-described heat conductive member L2X” ¶ [0062]) disposed between a wiring layer that is closest to the semiconductor layer (“The wiring pattern 114 of the wiring layer L2 corresponds to the above-described heat conductive member L2X (see FIG. 4C). In this manner, in the semiconductor device including three (or more) wiring layers, since a vertical distance between the uppermost wiring layer and the heat detection element is large, a middle or lower wiring layer may be used to stack the heat conductive members in the vertical direction.” ¶ [0062]), among the plurality of wiring layers, and the semiconductor layer, and not electrically connected to the protection circuit (“The wiring pattern 112 and the wiring pattern 114 are not electrically interconnected.” ¶ [0061]),
wherein in a plan view taken at the first-surface side, the first heat dissipation layer is disposed at a position where the first heat dissipation layer overlaps with at least a part of the protection circuit (Figs. 4A-4D and 5 shows heat dissipation layer 114 overlaps with at least a part of the protection circuit 30 (31 of 30)).
However, YASUSAKA et al. does not explicitly disclose a first heat dissipation layer disposed between the wiring layer and the semiconductor layer, and wherein the protection circuit is configured to protect the semiconductor element against noise.
In the similar field of endeavor of semiconductor devices Cook et al. Fig. 2A discloses, a first heat dissipation layer (“thermal via 230 may provide a more closely matched thermal environment for the first component 208 and the second component 234” ¶ [0025]) disposed between the wiring layer (“interconnects 218” ¶ [0024]) and the semiconductor layer (“a substrate 202 comprising a semiconductor material 204” ¶ [0024]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the heat dissipation layer of YASUSAKA et al. with the heat dissipation layer of Cook et al. in order to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance (Cook et al. ¶ [0025]).
However, Cook et al. does not teach wherein the protection circuit is configured to protect the semiconductor element against noise.
In the similar field of endeavor protection circuit Jin et al. discloses, wherein the protection circuit is configured to protect the semiconductor element against noise (“The ESD protection circuit 200 according to the present invention reduces the parasitic capacitance C.sub.ESD of the ESD protection circuit during operation. Other benefits include reducing the noise contribution from substrate resistance during normal operation due to the reduction of parasitic capacitance C.sub.ESD.” Column 5, lines 18-23).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit of YASUSAKA et al. as modified by Cook et al. with the protection circuit of Jin et al. in order to reduce the noise contribution from substrate resistance during normal operation due to the reduction of parasitic capacitance C.sub.ESD (Jin et al. Column 5, lines 18-23).
Regarding Claim 2, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein in a plan view taken at the first-surface side, a contact layer connecting the protection circuit and the wiring layer electrically is disposed inside a region surrounded by the first heat dissipation layer.
In the similar field of endeavor of semiconductor devices, Cook et al., Fig. 2A discloses, wherein in a plan view taken at the first-surface side, a contact layer (“contacts 216” ¶ [0024]) connecting the protection circuit (“components 208 and 234 are depicted in FIG. 2A as MOS transistors, however other manifestations, such as bipolar junction transistors, JFETs, resistors, and SCRs are within the scope of the instant example” ¶ [0024]) and the wiring layer (“interconnects 218” ¶ [0024]) electrically is disposed inside a region surrounded by the first heat dissipation layer 230 (“contacts 216 extend through the PMD layer 236. A first IMD layer 238 may be disposed over the thermal via 230” ¶ [0025]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the heat dissipation layer of YASUSAKA et al. with the heat dissipation layer of Cook et al. in order to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance (Cook et al. ¶ [0025]).
Regarding Claim 3, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein in a plan view taken at the first-surface side, a plurality of contact layers connecting the protection circuit and the wiring layer electrically is disposed, and the first heat dissipation layer is disposed between contact layers included in the plurality of contact layers.
In the similar field of endeavor of semiconductor devices Cook et al., Fig. 2A discloses, wherein in a plan view taken at the first-surface side, a plurality of contact layers (“contacts 216” ¶ [0024]) connecting the protection circuit 234 and the wiring layer 218 electrically is disposed, and the first heat dissipation layer 230 is disposed between contact layers included in the plurality of contact layers 216 (Fig. 2A shows the first heat dissipation layer 230 is disposed between the plurality of contact layers 216).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit and heat dissipation layer of YASUSAKA et al. with the protection circuit and the heat dissipation layer of Cook et al. in order to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance (Cook et al. ¶ [0025]).
Regarding Claim 4, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein in a plan view taken at the first-surface side, a contact layer connecting the protection circuit and the wiring layer electrically is disposed between first heat dissipation layers included in a plurality of first heat dissipation layers, each of which is the first heat dissipation layer.
In the similar field of endeavor of semiconductor devices Cook et al., Fig. 2A discloses, wherein in a plan view taken at the first-surface side, a contact layer (“contacts 216” ¶ [0024]) connecting the protection circuit 234 and the wiring layer 218 electrically is disposed between first heat dissipation layers 230 included in a plurality of heat dissipation layers 230, each of which is the first heat dissipation layer 230 (Fig. 2A shows a plurality of heat dissipation layer 230, each of which is the first heat dissipation layer 230).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit and heat dissipation layer of YASUSAKA et al. with the protection circuit and the heat dissipation layer of Cook et al. in order to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance (Cook et al. ¶ [0025]).
Regarding Claim 7, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. YASUSAKA et al. further discloses,
wherein the first heat dissipation layer contains, at least, a single element alone of metal selected from the group consisting of tungsten, copper (“wiring layers L2 and L3 are made of copper” ¶ [0063]), aluminum (“The wiring patterns 50 and 60 are formed by patterning metal having high conductivity (such as aluminum, copper, silver, gold or the like).” ¶ [0038]), titanium, cobalt, and nickel, or an alloy including the metal (“at least one of the wiring layers L1 and L2 stacked on the semiconductor substrate may be used to form the heat conductive member 60X” ¶ [0056]).
Regarding Claim 8, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. YASUSAKA et al. further discloses, wherein the wiring layer and the first heat dissipation layer contain metal, and a main element of the wiring layer and a main element of the first heat dissipation layer are different from each other (“if the wiring layer L1 is made of aluminum and the wiring layers L2 and L3 are made of copper, the wiring layers L2 and L3 having higher thermal conductivity may be used to form the heat conductive members L2X and L3X.” [0063]).
Regarding Claim 15, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. YASUSAKA et al. further discloses, wherein the first heat dissipation layer is electrically connected to a pad that is not electrically connected to the protection circuit (“The wiring pattern 60 is a conductive member (output line) electrically connecting the drain of the transistor 10 and the pad 80” ¶ [0038]).
Regarding Claim 18, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. YASUSAKA et al. further discloses, equipment comprising: the semiconductor apparatus according to claim 1; and at least one selected from the group comprising an optical apparatus co-operable with the semiconductor apparatus; a control apparatus configured to control the semiconductor apparatus; a processing apparatus configured to process a signal outputted from the semiconductor apparatus; a display apparatus configured to display information obtained by the semiconductor apparatus (“FIG. 8 shows an external appearance of a personal computer X, and FIG. 9 shows an external appearance of a television Y. The use of the above-described semiconductor devices 1 and 2 as power supply ICs of these electronic apparatuses can result in increased safety and reliability of the electronic apparatuses.” ¶ [0079]); a storage apparatus configured to store information obtained by the semiconductor apparatus; and a mechanical apparatus configured to operate based on information obtained by the semiconductor apparatus.
Regarding Claim 20, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein the first heat dissipation layer is not electrically connected to the semiconductor element.
In the similar field of endeavor of semiconductor devices Cook et al., Fig. 2A discloses, wherein the first heat dissipation layer 230 is not electrically connected to the semiconductor element (“the thermal via 230 laterally surrounds the components 208 and 234 in the PMD layer 236” ¶ [0025]; “The components 208 and 234 may be laterally separated by field oxide 214” ¶ [0024]; as layer 230 is in 236 and on 214 and both layer are insulating layers therefore, 230 is not connected to element 208 and 234).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the heat dissipation layer of YASUSAKA et al. with the heat dissipation layer of Cook et al. in order to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance (Cook et al. ¶ [0025]).
Regarding Claim 21, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein the semiconductor apparatus further comprises a contact that is electrically connected to the protection circuit and the wiring layer, and
in a plan view taken at the first-surface side, the contact is provided inside regions surrounded by the first heat dissipation layer.
In the similar field of endeavor of semiconductor devices Cook et al., Fig. 2A discloses, wherein the semiconductor apparatus further comprises a contact (“interconnect region 206 may include contacts 216,” ¶ [0024]) that is electrically connected to the protection circuit 234 and the wiring layer (“The interconnect region 206 may include contacts 216, interconnects 218” ¶ [0024]), and
in a plan view taken at the first-surface side, the contact 216 is provided inside regions surrounded (“the thermal via 230 laterally surrounds the components 208 and 234 in the PMD layer 236” ¶ [0025]) by the first heat dissipation layer 230.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the heat dissipation layer of YASUSAKA et al. with the heat dissipation layer of Cook et al. in order to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance (Cook et al. ¶ [0025]).
Regarding Claim 22, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein the noise is static electricity or a surge voltage.
In the similar field of endeavor protection circuit Jin et al. discloses, wherein the noise is static electricity or a surge voltage (“The ESD protection circuits begin conducting or undergo breakdown to provide an electrical path to ground (or to a power-supply rail) when excess voltage occurs.” Column 1, lines 55-58).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit of YASUSAKA et al. as modified by Cook et al. with the protection circuit of Jin et al. in order to provide a minimum CESD for a particular voltage rating, the ESD circuit has additional advantages. For example, when spacing is provided by a disconnected resistor between two connected resistors, the ESD protection circuit has improved heat dissipation characteristics (Jin et al. Column 7, lines 59-63).
Claims 23–25 are rejected under 35 U.S.C. 103 as being unpatentable over YASUSAKA, Makoto (US 20150255451 A1) “YASUSAKA et al.” in view of Cook, Benjamin Stassen (US 20180151471 A1) “Cook et al” further in view of Jin, Xiaodong (US 7751164 B1) “Jin et al.” further in view of Yanai; Tetsuro (US 5942931 A) “Yanai et al.”.
Regarding Claim 23, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. YASUSAKA et al. further discloses, the semiconductor apparatus further comprises a pad (“pads 70 and 80.” ¶ [0033]).
However, YASUSAKA et al. does not disclose, noise is static electricity that is inputted from the pad or a surge voltage that is inputted from the pad.
In the similar field of endeavor of Yanai et al. discloses, noise is static electricity that is inputted from the pad or a surge voltage that is inputted from the pad (“a protection circuit for providing protection against noise such as static electricity or the like applied to an input terminal or an output terminal of an integrated circuit device.” Column 1, Lines 6-10).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit of YASUSAKA et al. as modified by Cook et al. with the protection circuit of Jin et al. in order to provide protection against the input of noise such as static electricity or the like (Yanai et al. Column 1, lines 12-13).
Regarding Claim 24, YASUSAKA et al. as modified by Cook et al., Jin et al and Yanai et al. discloses the semiconductor apparatus according to claim 23. YASUSAKA et al. Figs. 1A, 6A and 7A further discloses, wherein in a plan view taken at the first-surface side, the first heat dissipation layer 114 is disposed at a position where the first heat dissipation layer overlaps (Figs. 1A, 6A and 7A shows wiring pattern 60, conductive member 90 and wiring patterns 240-250 overlap the pad 80/280/290 and the heat dissipation layer is part of the wiring patterns, therefore also overlaps with the pads; “a heat conductive member 260X is formed to overlap with the heat detection element 231 by leading a portion of the wiring pattern 260” ¶ [0076]) with at least the pad 80.
Regarding Claim 25, YASUSAKA et al. as modified by Cook et al., Jin et al and Yanai et al. discloses the semiconductor apparatus according to claim 23. YASUSAKA et al. Figs. 1A, 6A and 7A further discloses, in a plan view taken at the first-surface side, the protection circuit is disposed at a position where the protection circuit overlaps with at least the pad (7A shows protection circuit 230 overlap the pad 290, therefore also overlaps with the pads; “a heat conductive member 260X is formed to overlap with the heat detection element 231 by leading a portion of the wiring pattern 260” ¶ [0076]).
Claims 5-6 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over YASUSAKA, Makoto (US 20150255451 A1) “YASUSAKA et al.” in view of Cook, Benjamin Stassen (US 20180151471 A1) “Cook et al” further in view of Jin, Xiaodong (US 7751164 B1) “Jin et al.” further in view of Kobayashi; Masahiro (US 20130107075 A1) “Kobayashi et al.”
Regarding Claim 5, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein in a plan view taken at the first-surface side, the first heat dissipation layer is disposed at a position of overlapping with at least a part of a well region included in the protection circuit.
In the similar field of endeavor of semiconductor device with protection circuit, Kobayashi et al. Figs. 1-10 discloses, wherein in a plan view taken at the first-surface side, the first heat dissipation layer 150/130 is disposed at a position of overlapping with at least a part of a well region 902 (“The wiring 150 is connected to a p-type semiconductor region 902” ¶ [0048]) included in the protection circuit 315 (“Fig. 10B shows 150 is overlapping with 902).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit of YASUSAKA et al. with the protection circuit of Kobayashi et al. in order to be connected to the wiring VSS supplying the predetermined voltage (VSS) via a plurality of contacts (Kobayashi et al. ¶ [0048]).
Regarding Claim 6, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein in a plan view taken at the first-surface side, the first heat dissipation layer is disposed at a position where the first heat dissipation layer overlaps with at least a part of an active region included in the protection circuit.
In the similar field of endeavor of semiconductor device with protection circuit, Kobayashi et al. Figs. 1-10 discloses, wherein in a plan view taken at the first-surface side, the first heat dissipation layer is disposed at a position where the first heat dissipation layer overlaps (“Fig. 10B shows 150/130 is overlapping with 902 and 903) with at least a part of an active region included in the protection circuit (“The wiring 150 is connected to a p-type semiconductor region 902 forming the anode of the first diode 145 via the contact, and is connected to an n-type semiconductor region 903 forming the cathode of the second diode 146 via the contact.” ¶ [0048]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit of YASUSAKA et al. with the protection circuit of Kobayashi et al. in order to be connected to the wiring VSS supplying the predetermined voltage (VSS) via a plurality of contacts (Kobayashi et al. ¶ [0048]).
Regarding Claim 11, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein the semiconductor element includes a peripheral circuit configured to process a signal detected by a photoelectric conversion portion.
In the similar field of endeavor of semiconductor device with protection circuit, Kobayashi et al. Figs. 1-10 discloses, wherein the semiconductor element includes a peripheral circuit configured to process a signal detected by a photoelectric conversion portion (“a peripheral circuit part 302 where there is arranged a peripheral circuit that may include a reading circuit configured to read a signal from the pixel part 301” ¶ [0036]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device with protection circuit of YASUSAKA et al. with the semiconductor device with protection circuit including a peripheral circuit of Kobayashi et al. in order to generating a signal based on the charge of the photoelectric conversion element and is arranged in a main face thereof (Kobayashi et al., ¶ [0033]).
Regarding Claim 12, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein the semiconductor element includes a photoelectric conversion portion.
In the similar field of endeavor of semiconductor device with protection circuit, Kobayashi et al. Figs. 1-10 discloses, wherein the semiconductor element includes a photoelectric conversion portion (“a photoelectric conversion element 303” ¶ [0037]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device with protection circuit of YASUSAKA et al. with the semiconductor device with protection circuit including a photoelectric conversion element of Kobayashi et al. in order to generating a signal based on the charge of the photoelectric conversion element and is arranged in a main face thereof (Kobayashi et al., ¶ [0033]).
Regarding Claim 13, YASUSAKA et al. as modified by Cook et al., Jin et al. and Kobayashi et al. discloses the semiconductor apparatus according to claim 12. However, YASUSAKA et al. does not disclose, wherein light enters the photoelectric conversion portion through the second surface.
In the similar field of endeavor of semiconductor device with protection circuit, Kobayashi et al. Figs. 1-10 discloses, wherein light enters the photoelectric conversion portion through the second surface (“light enters from the micro lens layer 118 side and is received by the photoelectric conversion element.” ¶ [0054]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device with protection circuit of YASUSAKA et al. with the semiconductor device with protection circuit including a photoelectric conversion element of Kobayashi et al. in order to generating a signal based on the charge of the photoelectric conversion element and is arranged in a main face thereof (Kobayashi et al., ¶ [0033]).
Regarding Claim 14, YASUSAKA et al. as modified by Cook et al., Jin et al. and Kobayashi et al. discloses the semiconductor apparatus according to claim 13. However, YASUSAKA et al. does not disclose, wherein a circuit substrate including a peripheral circuit configured to process a signal detected by the photoelectric conversion portion is stacked on the semiconductor layer.
In the similar field of endeavor of semiconductor device with protection circuit, Kobayashi et al. Figs. 1-10 discloses, wherein a circuit substrate including a peripheral circuit configured to process a signal detected by the photoelectric conversion portion is stacked on the semiconductor layer (“In the pixel part 301 of the first member 308, there are arranged on the first substrate 101 an n-type semiconductor region 112 constituting a photoelectric conversion element” ¶ [0053]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device with protection circuit of YASUSAKA et al. with the semiconductor device with protection circuit including a photoelectric conversion element of Kobayashi et al. in order to generating a signal based on the charge of the photoelectric conversion element and is arranged in a main face thereof (Kobayashi et al., ¶ [0033]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over YASUSAKA, Makoto (US 20150255451 A1) “YASUSAKA et al.” in view of Cook, Benjamin Stassen (US 20180151471 A1) “Cook et al” further in view of Jin, Xiaodong (US 7751164 B1) “Jin et al.” further in view of Kaneko, Kishou (US 20130334529 A1) “Kaneko et al.”.
Regarding Claim 9, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 1. However, YASUSAKA et al. does not disclose, wherein an element isolation region and a second heat dissipation layer including metal are disposed between the first surface and the second surface, the protection circuit includes the element isolation region, the second heat dissipation layer is in contact with the element isolation region, the protection circuit is disposed at a first depth from the first surface, and the second heat dissipation layer is disposed at the first depth from the first surface.
In the similar field of endeavor of semiconductor device with protection circuit, Kaneko et al. Fig. 6 discloses, wherein an element isolation region (“an interlayer insulating film 4-1” ¶ [0042]) and a second heat dissipation layer (“wiring lines 21 and 22” ¶ [0060]) including metal (“a metal wiring line having a high thermal conductivity (e.g. Cu wiring line and Al wiring line)” ¶ [0060]) are disposed between the first surface (upper surface of 21 and 22) and the second surface (lower surface of 21 and 22), the protection circuit (“protection device 11” ¶ [0060]) includes the element isolation region 4-1, the second heat dissipation layer 21 and 22 is in contact with the element isolation region 4-1, the protection circuit is disposed at a first depth from the first surface, and the second heat dissipation layer is disposed at the first depth from the first surface (Fig. 6 shows the protection circuit 11 is disposed at a first depth from the first surface, and the second heat dissipation 21 and 22 layer is disposed at the first depth from the first surface).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit layer of YASUSAKA et al. with the protection circuit layer including a heat dissipation and isolation layer in order to adopt the structure which eases the heat generated locally in the ESD protection device 11 and the wiring layer 3 by the wiring lines 21 to 23, the heat tolerance and the reliability of the ESD protection device 11 can be improved (Kaneko et al. ¶ [0060]).
Regarding Claim 10, YASUSAKA et al. as modified by Cook et al. and Jin et al. discloses the semiconductor apparatus according to claim 9. However, YASUSAKA et al. does not disclose, wherein the second heat dissipation layer contains, at least, a single element alone of metal selected from the group consisting of tungsten, copper, aluminum, titanium, cobalt, and nickel, or an alloy including the metal, or a metal-and-polysilicon compound.
In the similar field of endeavor of semiconductor device with protection circuit, Kaneko et al. Fig. 6 discloses, wherein the second heat dissipation layer contains, at least, a single element alone of metal selected from the group consisting of tungsten, copper, aluminum, titanium, cobalt, and nickel, or an alloy including the metal, or a metal-and-polysilicon compound (“a metal wiring line having a high thermal conductivity (e.g. Cu wiring line and Al wiring line) may be formed in the neighborhood of the ESD protection device 11” ¶ [0060]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the protection circuit layer of YASUSAKA et al. with the protection circuit layer including a heat dissipation and isolation layer in order to adopt the structure which eases the heat generated locally in the ESD protection device 11 and the wiring layer 3 by the wiring lines 21 to 23, the heat tolerance and the reliability of the ESD protection device 11 can be improved (Kaneko et al. ¶ [0060]).
Claims 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over YASUSAKA, Makoto (US 20150255451 A1) “YASUSAKA et al.” in view of Cook, Benjamin Stassen (US 20180151471 A1) “Cook et al”.
Regarding Independent Claim 26, YASUSAKA et al. Figs. 1-5 discloses a semiconductor apparatus (“a semiconductor device” ¶ [0032]), comprising:
a semiconductor layer (“a semiconductor substrate” ¶ [0034]) having a first surface (Top Surface of the substrate aligned with the top surface of transistor 10 in Fig. 5) and a second surface (Bottom surface of substrate in Fig. 5) and including, between the first surface and the second surface,
a semiconductor element (“a P channel type MOS (Metal Oxide Semiconductor) field effect transistor 10” ¶ [0033]) and
a protection circuit (“an overheat protection circuit 30” ¶ [0033]);
a wiring layer disposed at a first-surface side of the semiconductor layer (“a wiring pattern 112” ¶ [0061]) and electrically connected to the protection circuit (“a wiring pattern 112 electrically connected to a transistor 31 (heat detection element)” ¶ [0061]) or a plurality of wiring layers (“The first (lower) wiring layer L1 includes a wiring pattern 111 electrically connected to a transistor 10 (heat source) and a wiring pattern 112 electrically connected to a transistor 31 (heat detection element). The second (middle) wring layer L2 includes a wiring pattern 113 formed on the wiring pattern 111, and a wiring pattern 114 formed on the wiring pattern 112. The third (upper) wiring layer L3 includes a wiring pattern 115 formed across both of the transistor 10 (heat source) and the transistor 31 (heat detection element). The wiring pattern 111 and the wiring patterns 113, the wiring pattern 113 and the wiring patterns 115, and the wiring pattern 114 and the wiring patterns 115 are respectively electrically interconnected through vias 116 to 118, respectively.” ¶ [0061]) disposed at a first-surface side of the semiconductor layer and electrically connected to the protection circuit, the first-surface side being a side where the first surface is located; and
a first heat dissipation layer (“The wiring pattern 114 of the wiring layer L2 corresponds to the above-described heat conductive member L2X” ¶ [0062]) disposed between a wiring layer that is closest to the semiconductor layer (“The wiring pattern 114 of the wiring layer L2 corresponds to the above-described heat conductive member L2X (see FIG. 4C). In this manner, in the semiconductor device including three (or more) wiring layers, since a vertical distance between the uppermost wiring layer and the heat detection element is large, a middle or lower wiring layer may be used to stack the heat conductive members in the vertical direction.” ¶ [0062]), among the plurality of wiring layers, and the semiconductor layer, and not electrically connected to the protection circuit (“The wiring pattern 112 and the wiring pattern 114 are not electrically interconnected.” ¶ [0061]),
wherein in a plan view taken at the first-surface side, the first heat dissipation layer is disposed at a position where the first heat dissipation layer overlaps with at least a part of the protection circuit (Figs. 4A-4D and 5 shows heat dissipation layer 114 overlaps with at least a part of the protection circuit 30 (31 of 30)).
However, YASUSAKA et al. does not explicitly disclose a first heat dissipation layer disposed between the wiring layer and the semiconductor layer, and wherein the first heat dissipation layer is not electrically connected to the semiconductor element.
In the similar field of endeavor of semiconductor devices Cook et al. Fig. 2A discloses, a first heat dissipation layer (“thermal via 230 may provide a more closely matched thermal environment for the first component 208 and the second component 234” ¶ [0025]) disposed between the wiring layer (“interconnects 218” ¶ [0024]) and the semiconductor layer (“a substrate 202 comprising a semiconductor material 204” ¶ [0024]) and
wherein the first heat dissipation layer 230 is not electrically connected to the semiconductor element (“the thermal via 230 laterally surrounds the components 208 and 234 in the PMD layer 236” ¶ [0025]; “The components 208 and 234 may be laterally separated by field oxide 214” ¶ [0024]; as layer 230 is in 236 and on 214 and both layer are insulating layers therefore, 230 is not connected to element 208 and 234).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the heat dissipation layer of YASUSAKA et al. with the heat dissipation layer of Cook et al. in order to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance (Cook et al. ¶ [0025]).
Regarding Independent Claim 27, YASUSAKA et al. Figs. 1-5 discloses a semiconductor apparatus (“a semiconductor device” ¶ [0032]), comprising:
a semiconductor layer (“a semiconductor substrate” ¶ [0034]) having a first surface (Top Surface of the substrate aligned with the top surface of transistor 10 in Fig. 5) and a second surface (Bottom surface of substrate in Fig. 5) and including, between the first surface and the second surface,
a semiconductor element (“a P channel type MOS (Metal Oxide Semiconductor) field effect transistor 10” ¶ [0033]) and
a protection circuit (“an overheat protection circuit 30” ¶ [0033]);
a wiring layer disposed at a first-surface side of the semiconductor layer (“a wiring pattern 112” ¶ [0061]) and electrically connected to the protection circuit (“a wiring pattern 112 electrically connected to a transistor 31 (heat detection element)” ¶ [0061]) or a plurality of wiring layers (“The first (lower) wiring layer L1 includes a wiring pattern 111 electrically connected to a transistor 10 (heat source) and a wiring pattern 112 electrically connected to a transistor 31 (heat detection element). The second (middle) wring layer L2 includes a wiring pattern 113 formed on the wiring pattern 111, and a wiring pattern 114 formed on the wiring pattern 112. The third (upper) wiring layer L3 includes a wiring pattern 115 formed across both of the transistor 10 (heat source) and the transistor 31 (heat detection element). The wiring pattern 111 and the wiring patterns 113, the wiring pattern 113 and the wiring patterns 115, and the wiring pattern 114 and the wiring patterns 115 are respectively electrically interconnected through vias 116 to 118, respectively.” ¶ [0061]) disposed at a first-surface side of the semiconductor layer and electrically connected to the protection circuit, the first-surface side being a side where the first surface is located; and
a first heat dissipation layer (“The wiring pattern 114 of the wiring layer L2 corresponds to the above-described heat conductive member L2X” ¶ [0062]) disposed between a wiring layer that is closest to the semiconductor layer (“The wiring pattern 114 of the wiring layer L2 corresponds to the above-described heat conductive member L2X (see FIG. 4C). In this manner, in the semiconductor device including three (or more) wiring layers, since a vertical distance between the uppermost wiring layer and the heat detection element is large, a middle or lower wiring layer may be used to stack the heat conductive members in the vertical direction.” ¶ [0062]), among the plurality of wiring layers, and the semiconductor layer, and not electrically connected to the protection circuit (“The wiring pattern 112 and the wiring pattern 114 are not electrically interconnected.” ¶ [0061]),
wherein in a plan view taken at the first-surface side, the first heat dissipation layer is disposed at a position where the first heat dissipation layer overlaps with at least a part of the protection circuit (Figs. 4A-4D and 5 shows heat dissipation layer 114 overlaps with at least a part of the protection circuit 30 (31 of 30)).
However, YASUSAKA et al. does not explicitly disclose a first heat dissipation layer disposed between the wiring layer and the semiconductor layer, a contact that is electrically connected to the protection circuit and the wiring layer, wherein in a plan view taken at the first-surface side, the contact is provided inside regions surrounded by the first heat dissipation layer.
In the similar field of endeavor of semiconductor devices, Cook et al., Fig. 2A discloses, a first heat dissipation layer (“thermal via 230 may provide a more closely matched thermal environment for the first component 208 and the second component 234” ¶ [0025]) disposed between the wiring layer (“interconnects 218” ¶ [0024]) and the semiconductor layer (“a substrate 202 comprising a semiconductor material 204” ¶ [0024]).
wherein in a plan view taken at the first-surface side, a contact (“contacts 216” ¶ [0024]) that is electrically connected to the protection circuit (“components 208 and 234 are depicted in FIG. 2A as MOS transistors, however other manifestations, such as bipolar junction transistors, JFETs, resistors, and SCRs are within the scope of the instant example” ¶ [0024]) and the wiring layer (“interconnects 218” ¶ [0024]), wherein in a plan view taken at the first-surface side, the contact 216 is provided inside regions surrounded (“the thermal via 230 laterally surrounds the components 208 and 234 in the PMD layer 236” ¶ [0025]) by the first heat dissipation layer 230.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the heat dissipation layer of YASUSAKA et al. with the heat dissipation layer of Cook et al. in order to provide a more closely matched thermal environment for the first component and the second component and thereby improve their performance (Cook et al. ¶ [0025]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
