DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 11/28/25, for application number 18/335,009 has been received and entered into record. Claims 1, 5, 8, and 15 have been amended, and Claim 6 has been cancelled. Therefore, Claims 1-5 and 7-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 1-5 and 7-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, lines 15-17 recite, “wherein the buffer circuit comprises a level shifter positioned between the multiplexer and the corresponding coupled peripheral to perform real-time voltage-level shifting of the clock signal provided to the corresponding coupled peripheral.” (emphasis added) There does not appear to be sufficient support for the real-time voltage-level shifting in the Specification as filed.
Paragraphs 15, 20, and 21, as well as Fig. 1 and 4 as cited by Applicant make reference to adjusting the voltage level to power domain voltage, but there does not appear to be language regarding a real-time voltage adjustment (i.e. level shifting). For the purposes of examination, the “real-time voltage-level shifting” is interpreted to simply be “voltage-level shifting.”
Claims 13 and 20 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding Claims 13 and 20, independent claims 8 and 15, on which Claims 13 and 20 depend have incorporated, in part, features presented in Claim 6, and thus, Claims 13 and 20 as currently presented appear to simply repeat the limitations already present in the newly-amended Claims 8 and 15. Applicant may cancel the claims, amend the claims to place the claims in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that the dependent claims complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-13, and 14-20, are rejected under 35 U.S.C. 103 as being unpatentable over Hanson et al., US 2019/0079574 A1, in view of Sheafor, US 9,703,313 B2, and further in view of Schmitz et al., US 2011/0010567 A1.
Regarding Claim 1, Hanson discloses a method performed by an electronic circuit within a microcontroller unit (MCU) [Fig. 1A and par 30-31, core 111 within microcontroller 102], the method comprising:
fanning out a source clock signal within the MCU to produce a plurality of clock signals [Fig. 1J(i) and par 106, clock generator 120 receives source clock signals (e.g., from HRFC, LFRC, or XTAL oscillators) and distributes the multiple derived clocks throughout the microcontroller system; i.e. a clock CLKOUT, generated from any of the oscillators, may be configured and driven onto an external pin. CLKOUT also drives the Real Time Clock (RTC) Module and other internal clock nodes.);
inputting each one of the plurality of clock signals to a respective one of a plurality of input/output (I/O) groups within the MCU [Fig. 1A and par 106, the clock generator supplies (i.e., inputs) these clocks to various functional blocks of the MCU, including I/O groups within I/O peripherals 128. Par 107, I/O groups receive clocks according to module needs (i.e., respectively) as the clock generator controls oscillator enablement based on module requests (I2C/SPI Master 128D is one of the modules within I/O peripherals 128, see par 34. See also par 235 and 251)], wherein each one of the plurality of I/O groups corresponds to a different one of a plurality of power domains of the MCU [Par 251-252, peripherals (including I/O groups) may be grouped by power domain and their clocking isolated primarily to that domain, see also par. 253-254]; and
providing the plurality of clock signals to a plurality of peripherals coupled to the plurality of I/O groups [Fig. 1A and par 106, a plurality of clocks are supplied by the clock generator to multiple blocks within MCU, including I/O groups and coupled peripherals within I/O peripherals 128 (128A-E)], wherein each one of the plurality of I/O groups adjusts, according to its corresponding power domain, its clock signal prior to providing the clock signal to its corresponding coupled peripheral [Par 244-246 and Fig. 4, a block (i.e., I/O groups) can be clock gated with their respective clock gater 420 when its corresponding power domain is shut down].
Hanson also discloses the use of clock gate circuits to control clock signals based on the corresponding power domain, specifically by disabling or gating off the clock when the associated power domain is shut down [Par 246 and Fig. 4]. However, Hanson does not explicitly disclose fanning out, by a multiplexer, a clock signal; adjusting a voltage level of the clock signal; wherein the adjustment is performed by a buffer circuit disposed within each I/O group, the buffer circuit being powered by the corresponding power domain and configured to shift the voltage level of the clock signal to match the voltage requirements of the peripheral; wherein the buffer circuit comprises a level shifter positioned between the multiplexer and the corresponding coupled peripheral to perform real-time voltage-level shifting of the clock signal provided to the corresponding coupled peripheral.
In the analogous art of peripheral clock management, Sheafor teaches fanning out, by a multiplexer, a clock signal [Fig. 2 and Fig. 4, MUX1 to MUXm, within the MCU fan out clock generator 30 to produce a plurality of clock signals].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hanson and Sheafor, before him before the effective filing date of the claimed invention, to incorporate a multiplexer to fan out the source clock signal to produce a plurality of clock signals as taught by Sheafor, into the system as disclosed by Hanson, to achieve autonomy from the CPU, resulting in improved power efficiency [Sheafor, col 4, Il. 26-29].
However, the combination of references does not explicitly teach adjusting a voltage level of the clock signal; wherein the adjustment is performed by a buffer circuit disposed within each I/O group, the buffer circuit being powered by the corresponding power domain and configured to shift the voltage level of the clock signal to match the voltage requirements of the peripheral; wherein the buffer circuit comprises a level shifter positioned between the multiplexer and the corresponding coupled peripheral to perform real-time voltage-level shifting of the clock signal provided to the corresponding coupled peripheral.
In the analogous art of power management, Schmitz teaches adjusting a voltage level of the clock signal; and wherein the adjustment is performed by a buffer circuit disposed within each I/O group, the buffer circuit being powered by the corresponding power domain and configured to shift the voltage level of the clock signal to match the voltage requirements of the peripheral; and wherein the buffer circuit comprises a level shifter positioned between the clock signal and the corresponding coupled peripheral to perform real-time voltage-level shifting of the clock signal provided to the corresponding coupled peripheral [if a particular bus transaction requires that the peripheral device 104 be in a different operating state, the power management device 106 can transition between one operating state and another, for example, by adjusting the operating voltage and/or clock frequency required for the new operating state; the power controller 211 adjusts the operating voltage and/or clock frequency of the peripheral device 104 to minimize energy consumption, depending on the operating state of operation of the peripheral device 104 (the buffer circuit necessarily being positioned between the clock signal source and the peripheral, as the buffer circuit receives the clock signal and adjusts the signal prior to sending the adjusted voltage/frequency to the peripheral), par 20, 29].
It would have been obvious to one or ordinary skill in the art having the teachings of Hanson, Sheafor, and Schmitz before the effective filing date of the claimed invention, to incorporate adjusting a voltage level of a clock signal as taught by Schmitz, into the system as disclosed by Hanson and Sheafor, to minimize energy consumption [Schmitz, par 29].
Regarding claim 2, Hanson, Sheafor, and Schmitz disclose the method of claim 1. Hanson further discloses wherein the source clock signal is a first source clock signal corresponding to a first clock domain and the plurality of clock signals are a plurality of first clock signals [Par 106-107, the clock generator can distribute clocks from high frequency 48 MHz oscillator (HFRC), i.e., a first source clock signal corresponding to a first clock domain, and may distribute a plurality of clocks derived from HFRC upon received requests from modules], and wherein the first source clock signal and the second source clock signal operate at different clock frequencies [Par 106, first source clock signal HFRC operates at 48 MHz, second source clock signal LFRC operates at 1 kHz]. The remainder of claim 2 repeats substantially the same limitations as recited in claim 1, and is rejected accordingly.
Regarding claim 3, Hanson, Sheafor, and Schmitz disclose the method of claim 1. Hanson further discloses wherein the source clock signal is a low power clock and each one of the plurality of clock signals operates as a low power clock to one or more of the plurality of peripherals while operating a low power state [Par 68, the enabled source clock signal may be low frequency clock LFRC when the microcontroller is in a low power state (deep sleep mode 3). This mode can be used by the ADC (peripheral) for very low power sampling].
Regarding claim 4, Hanson, Sheafor, and Schmitz disclose the method of claim 1. Hanson further discloses wherein each one of the plurality of power domains is based on one of a plurality of device specifications corresponding to the plurality of peripherals [Par 252, the peripherals are organized into power domains based on factors like cell type, voltage, or corner behavior (i.e., examples of device specifications)].
Regarding claim 5, Hanson, Sheafor, and Schmitz disclose the method of claim 1. Hanson further discloses: turning off power to a first peripheral of the plurality of peripherals [Par 244, a block can be power gated (i.e., turn off power) when not in use (see also par 252 and Fig. 8, individual peripherals may have their own blocks/power domains, e.g., BLOCK3 (414) in Fig. 4)]; and turning off one of the plurality of clock signals corresponding to the first peripheral in response to turning off the power to the first peripheral [Par 246, clocks going to the blocks may also be gated (i.e., turned off) if corresponding power domain is shut down (i.e., clock gating in response to power being gated)].
Regarding claim 7, Hanson, Sheafor, and Schmitz disclose the method of claim 1. Hanson further discloses wherein the source clock signal is generated external to the MCU [Par 30 and par 50, one of the three clock sources may be a 32.768 kHz crystal (XTAL) oscillator].
Regarding claim 8, Hanson discloses a system comprising a microcontroller unit (MCU) [Fig. 1A and par 36, MCU 102], and peripherals coupled to the plurality of I/O groups and external to the MCU [Par 36]. The remainder of claim 8 repeats the same limitations as recited in claim 1, and is rejected accordingly.
Regarding claims 9, 11, 12 and 14, Hanson, Sheafor, and Schmitz disclose the system of claim 8. The remainder of claims 9, 11, 12, and 14, repeat the same limitations as recited in claims 2, 4, 5, and 7, respectively, and are rejected accordingly.
Regarding Claim 13, Hanson, Sheafor, and Schmitz disclose the system of Claim 8. Claim 13 recites limitations similar to those presented in Claim 8, and is rejected accordingly.
Regarding claim 10, Hanson, Sheafor, and Schmitz disclose the system of claim 8. Hanson further discloses adjusting clock signals prior to being sent to one or more of the plurality of peripherals [Par 244-246 and Fig. 4, a block (i.e., I/O groups) can be clock gated with their respective clock gater 420 when its corresponding power domain is shut down]. Schmitz further teaches one or more clock signal boosters that adjust the voltage level of one or more of the plurality of clock signals [adjustable voltage regulator 212 can set an output voltage (VOUT) provided to the peripheral voltage 104 at a specific voltage level, par 30].
Regarding claim 15, Hanson discloses a microcontroller unit (MCU) [Fig. 1A, MCU 102]. The remainder of claim 15 repeats the same limitations as recited in claims 1 and 8, and is rejected accordingly.
Regarding claims 16-19, Hanson, Sheafor, and Schmitz disclose the MCU of Claim 15. The remainder of claims 16-19 repeat the same limitations as recited in claims 2-5, respectively, and are rejected accordingly.
Regarding Claim 20, Hanson, Sheafor, and Schmitz disclose the MCU of Claim 15. Claim 20 recites limitations similar to those presented in Claim 15, and is rejected accordingly.
Response to Arguments
Applicant's arguments filed 11/26/25 have been fully considered but they are not persuasive.
Applicant argues Schmitz does not teach a buffer circuit comprising a level shifter on a clock signal path positioned between a multiplexer and a peripheral to perform real-time voltage-level shifting of the clock signal provided to the peripheral.
Examiner notes the rejection relies upon Sheafor to teach the multiplexer fanning a plurality to clock signals, and while Schmitz does not explicitly teach the buffer circuit on the signal path between the multiplexer and the peripheral, the circuitry of Schmitz receives a clock signal from a clock source and outputs an adjusted voltage to a peripheral, and thus would necessarily be on the signal path between a multiplexer which fanned out clock signals and the corresponding peripherals.
Examiner also notes, while the amendments appear to overcome the rejection of record, as indicated in the interview dated 11/25/25, upon further search and consideration, and as noted in the rejection above, there does not appear to be support for the “real-time voltage-level shifting” in the Specification as filed. As such, no weight is given to the “real-time voltage-level shifting” beyond the voltage adjustment previously presented. Additional clarification and support regarding the real-time voltage level shifting (adjustment) and any features of the multiplexer as relates to the positioning of the buffer circuit may better distinguish the claims from the rejection of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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/Paul Yen/Primary Examiner, Art Unit 2175