DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 07/30/26, for application number 18/335,009 has been received and entered into record. Claims 1, 8, and 15 have been amended, Claims 2, 6, 9, 13, 15, and 20 were previously cancelled. Therefore, Claims 1, 3-5, 7, 8, 10-12, 14, 15, and 17-19 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 8, and 15 are objected to because of the following informalities:
Claim 1, lines 4-6 recite, “wherein control circuitry identifies respective operating states of the plurality of peripherals and controls the first multiplexer to selectively feed corresponding ones of the plurality of clock signals to respective buffer circuits of the plurality of I/O groups” (emphasis added) and should instead read, “wherein control circuitry identifies respective operating states of a plurality of peripherals and controls the first multiplexer to selectively feed corresponding ones of the plurality of clock signals to respective buffer circuits of a plurality of I/O groups” (emphasis added) to clarify the introduction of the plurality of peripherals and plurality of I/O groups in the claim. References to “plurality of peripherals” and “plurality of I/O groups” in the subsequent limitations may need amendment in light of the corrections made to lines 4-6.
Claims 8 and 15 repeat the same limitations as recited in Claim 1, and are objected to accordingly. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 7, 8, 10-12, 14, 15, and 17-19, are rejected under 35 U.S.C. 103 as being unpatentable over Hanson et al., US 2019/0079574 A1, in view of Yi et al., US 2019/0187774 A1, and further in view of Schmitz et al., US 2011/0010567 A1.
Regarding Claim 1, Hanson discloses a method performed by an electronic circuit within a microcontroller unit (MCU) [Fig. 1A and par 30-31, core 111 within microcontroller 102], the method comprising:
fanning out a source clock signal within the MCU to produce a plurality of clock signals [Fig. 1J(i) and par 106, clock generator 120 receives source clock signals (e.g., from HRFC, LFRC, or XTAL oscillators) and distributes the multiple derived clocks throughout the microcontroller system; i.e. a clock CLKOUT, generated from any of the oscillators, may be configured and driven onto an external pin. CLKOUT also drives the Real Time Clock (RTC) Module and other internal clock nodes.);
feed corresponding ones of the plurality of clock signals to respective buffer circuits of the plurality of I/O groups [Fig. 1A and par 106, a plurality of clocks are supplied by the clock generator to multiple blocks within MCU, including I/O groups and coupled peripherals within I/O peripherals 128 (128A-E)], wherein each one of the plurality of I/O groups adjusts, according to its corresponding power domain, its clock signal prior to providing the clock signal to its corresponding coupled peripheral [Par 244-246 and Fig. 4, a block (i.e., I/O groups) can be clock gated with their respective clock gater 420 when its corresponding power domain is shut down];
inputting each one of the plurality of clock signals to a respective one of a plurality of input/output (I/O) groups within the MCU [Fig. 1A and par 106, the clock generator supplies (i.e., inputs) these clocks to various functional blocks of the MCU, including I/O groups within I/O peripherals 128. Par 107, I/O groups receive clocks according to module needs (i.e., respectively) as the clock generator controls oscillator enablement based on module requests (I2C/SPI Master 128D is one of the modules within I/O peripherals 128, see par 34. See also par 235 and 251)], wherein each one of the plurality of I/O groups corresponds to a different one of a plurality of power domains of the MCU [Par 251-252, peripherals (including I/O groups) may be grouped by power domain and their clocking isolated primarily to that domain, see also par. 253-254];
providing the plurality of clock signals to a plurality of peripherals coupled to the plurality of I/O groups [Fig. 1A and par 106, a plurality of clocks are supplied by the clock generator to multiple blocks within MCU, including I/O groups and coupled peripherals within I/O peripherals 128 (128A-E)], wherein each one of the plurality of I/O groups adjusts, according to its corresponding power domain, its clock signal prior to providing the clock signal to its corresponding coupled peripheral [Par 244-246 and Fig. 4, a block (i.e., I/O groups) can be clock gated with their respective clock gater 420 when its corresponding power domain is shut down];
wherein the source clock signal is a first source clock signal corresponding to a first clock domain and the plurality of clock signals are a plurality of first clock signals [Par 106-107, the clock generator can distribute clocks from high frequency 48 MHz oscillator (HFRC), i.e., a first source clock signal corresponding to a first clock domain, and may distribute a plurality of clocks derived from HFRC upon received requests from modules];
distributing the plurality of second clock signals to the plurality of I/O groups [Fig. 1A and par 106, the clock generator supplies (i.e., inputs) these clocks to various functional blocks of the MCU, including I/O groups within I/O peripherals 128. Par 107, I/O groups receive clocks according to module needs (i.e., respectively) as the clock generator controls oscillator enablement based on module requests (I2C/SPI Master 128D is one of the modules within I/O peripherals 128, see par 34. See also par 235 and 251)]; and
wherein the first source clock signal and the second source clock signal operate at different clock frequencies [Par 106, first source clock signal HFRC operates at 48 MHz, second source clock signal LFRC operates at 1 kHz].
Hanson also discloses the use of clock gate circuits to control clock signals based on the corresponding power domain, specifically by disabling or gating off the clock when the associated power domain is shut down [Par 246 and Fig. 4]. However, Hanson does not explicitly teach wherein control circuitry identifies respective operating states of the plurality of components and controls the first multiplexer to selectively feed corresponding ones of the plurality of clock signals to the plurality of components; fanning out, by a multiplexer, a clock signal; adjusting a voltage level of the clock signal; wherein the adjustment is performed by a buffer circuit disposed within each I/O group, the buffer circuit being powered by the corresponding power domain and configured to shift the voltage level of the clock signal to match the voltage requirements of the peripheral; wherein the buffer circuit comprises a level shifter positioned between the multiplexer and the corresponding coupled peripheral to perform real-time voltage-level shifting of the clock signal provided to the corresponding coupled peripheral.
Yi teaches wherein control circuitry identifies respective operating states of the plurality of components and controls the first multiplexer to selectively feed corresponding ones of the plurality of clock signals to the plurality of components [selectively controlling a clock to be provided to each intellectual property block based on operation states of the intellectual property block (i.e. the operation states of the function blocks are determined by the clock managing unit 120 in order to provide or not provide a clock based on the operation state), par 5, 37]; fanning out, by a first multiplexer, a clock signal; and fanning out, by a second multiplexer, a clock signal [clock managing unit 120 providing clocks to each of the multiple function blocks depending on the operation state of each block, par 37].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hanson and Yi, before him before the effective filing date of the claimed invention, to incorporate selectively feeding clocks to components based on their operation state, as taught by Yi, into the system as disclosed by Hanson, to reduce power consumption relating to the clock [Yi, par 4].
However, the combination of references does not explicitly teach adjusting a voltage level of the clock signal; wherein the adjustment is performed by a buffer circuit disposed within each I/O group, the buffer circuit being powered by the corresponding power domain and configured to shift the voltage level of the clock signal to match the voltage requirements of the peripheral; wherein the buffer circuit comprises a level shifter positioned between the multiplexer and the corresponding coupled peripheral to perform real-time voltage-level shifting of the clock signal provided to the corresponding coupled peripheral.
In the analogous art of power management, Schmitz teaches adjusting a voltage level of the clock signal; and wherein the adjustment is performed by a buffer circuit disposed within each I/O group, the buffer circuit being powered by the corresponding power domain and configured to shift the voltage level of the clock signal to match the voltage requirements of the peripheral; and wherein the buffer circuit comprises a level shifter positioned between the clock signal and the corresponding coupled peripheral to perform real-time voltage-level shifting of the clock signal provided to the corresponding coupled peripheral [if a particular bus transaction requires that the peripheral device 104 be in a different operating state, the power management device 106 can transition between one operating state and another, for example, by adjusting the operating voltage and/or clock frequency required for the new operating state; the power controller 211 adjusts the operating voltage and/or clock frequency of the peripheral device 104 to minimize energy consumption, depending on the operating state of operation of the peripheral device 104 (the buffer circuit necessarily being positioned between the clock signal source and the peripheral, as the buffer circuit receives the clock signal and adjusts the signal prior to sending the adjusted voltage/frequency to the peripheral), par 20, 29].
It would have been obvious to one or ordinary skill in the art having the teachings of Hanson, Yi, and Schmitz before the effective filing date of the claimed invention, to incorporate adjusting a voltage level of a clock signal as taught by Schmitz, into the system as disclosed by Hanson and Yi, to minimize energy consumption [Schmitz, par 29].
Regarding Claim 3, Hanson, Yi, and Schmitz disclose the method of claim 1. Hanson further discloses wherein the source clock signal is a low power clock and each one of the plurality of clock signals operates as a low power clock to one or more of the plurality of peripherals while operating a low power state [Par 68, the enabled source clock signal may be low frequency clock LFRC when the microcontroller is in a low power state (deep sleep mode 3). This mode can be used by the ADC (peripheral) for very low power sampling].
Regarding Claim 4, Hanson, Yi, and Schmitz disclose the method of claim 1. Hanson further discloses wherein each one of the plurality of power domains is based on one of a plurality of device specifications corresponding to the plurality of peripherals [Par 252, the peripherals are organized into power domains based on factors like cell type, voltage, or corner behavior (i.e., examples of device specifications)].
Regarding Claim 5, Hanson, Yi, and Schmitz disclose the method of claim 1. Hanson further discloses: turning off power to a first peripheral of the plurality of peripherals [Par 244, a block can be power gated (i.e., turn off power) when not in use (see also par 252 and Fig. 8, individual peripherals may have their own blocks/power domains, e.g., BLOCK3 (414) in Fig. 4)]; and turning off one of the plurality of clock signals corresponding to the first peripheral in response to turning off power to the first peripheral [Par 246, clocks going to the blocks may also be gated (i.e., turned off) if corresponding power domain is shut down (i.e., clock gating in response to power being gated)].
Regarding Claim 7, Hanson, Yi, and Schmitz disclose the method of claim 1. Hanson further discloses wherein the source clock signal is generated external to the MCU [Par 30 and par 50, one of the three clock sources may be a 32.768 kHz crystal (XTAL) oscillator].
Regarding Claim 8, Hanson discloses a system comprising a microcontroller unit (MCU) [Fig. 1A and par 36, MCU 102], and peripherals coupled to the plurality of I/O groups and external to the MCU [Par 36]. The remainder of claim 8 repeats the same limitations as recited in claim 1, and is rejected accordingly.
Regarding Claim 10, Hanson, Yi, and Schmitz disclose the system of claim 8. Hanson further discloses adjusting clock signals prior to being sent to one or more of the plurality of peripherals [Par 244-246 and Fig. 4, a block (i.e., I/O groups) can be clock gated with their respective clock gater 420 when its corresponding power domain is shut down]. Schmitz further teaches one or more clock signal boosters that adjust the voltage level of one or more of the plurality of clock signals [adjustable voltage regulator 212 can set an output voltage (VOUT) provided to the peripheral voltage 104 at a specific voltage level, par 30].
Regarding Claims 11, 12 and 14, Hanson, Yi, and Schmitz disclose the system of claim 8. The remainder of claims 11, 12, and 14, repeat the same limitations as recited in claims 4, 5, and 7, respectively, and are rejected accordingly.
Regarding Claim 15, Hanson discloses a microcontroller unit (MCU) [Fig. 1A, MCU 102]. The remainder of claim 15 repeats the same limitations as recited in claims 1 and 8, and is rejected accordingly.
Regarding claims 17-19, Hanson, Yi, and Schmitz disclose the MCU of Claim 15. The remainder of claims 17-19 repeat the same limitations as recited in claims 3-5, respectively, and are rejected accordingly.
Response to Arguments
Applicant’s arguments filed 07/30/26 have been considered but are moot due to the new rejection based on the references cited above, as well as the newly cited portions of the references previously presented.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175
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