DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Reopening of Prosecution After Appeal Brief
In view of the appeal brief filed on 05/09/2026, PROSECUTION IS HEREBY REOPENED. New grounds of rejection are set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
Joint Inventors
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 9-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Loh (US 20130114924 A1).
With regards to claims 1 and 9, Loh discloses a package assembly and method for attaching an optical fiber to a photonic integrated circuit chip, comprising:
having a photonic integrated circuit chip that includes an optical fiber attachment area (Figs15a-b/PIC chip 1502 and fiber attachment area [region defined by elements 1514]);
disposing at least one optical fiber within the optical fiber attachment area (Figs15a-b/At least one optical fiber 1512);
disposing a lid structure over the at least one optical fiber (Figs15a-b/Lid structure 1518); and
forming soldered connections between the lid structure and the photonic integrated circuit chip such that upon cooling of the soldered connections the lid structure is drawn toward the photonic integrated circuit chip causing the lid structure to press against the at least one optical fiber to mechanically hold the at least one optical fiber against the optical fiber attachment area (Figs15a-b/Soldered connections 1516; Paragraph 256).
With regards to claims 2 and 10, Loh discloses the package assembly and method as recited in claims 1 and 9 respectively, wherein the lid structure is formed of silicon (Paragraph 295/ “…Si V-grooved substrate piece (e.g. a capping substrate)…”).
With regards to claim 3 and 11, Loh discloses the package assembly and method as recited in claims 1 and 9 respectively, wherein the soldered connections are formed at locations around and outside of the optical fiber attachment area (Figs15a-b).
With regards to claim 4 and 12, Loh discloses the package assembly and method as recited in claims 1 and 9 respectively, wherein the plurality of soldered connections are formed to shrink upon cooling after completion of a reflow process that forms the plurality of soldered connections (Paragraph 256; Paragraph 295).
With regards to claim 5 and 13, Loh discloses the package assembly and method as recited in claims 1 and 9 respectively, wherein forming the soldered connections includes disposing solder balls on the photonic integrated circuit chip and respectively aligning conductive pad structures within the lid structure to the solder balls (Figs15b/Conductive pad structures [Rectangular structures above elements 1516]).
With regards to claims 6 and 14, Loh discloses the package assembly and method as recited in claims 1 and 9 respectively, wherein the optical fiber attachment area includes an array of a plurality of V-grooves, and wherein disposing the at least one optical fiber within the optical fiber attachment area includes respectively disposing a plurality of optical fibers within the plurality of V-grooves (Figs15a-b/Array of a plurality of v-grooves [all of elements 1514 together]).
With regards to claims 7 and 15, Loh discloses the package assembly and method as recited in claims 6 and 14 respectively, wherein the photonic integrated circuit chip includes a plurality of spot size converters, each of the plurality of spot size converters exposed at an interior end of a respective one of the plurality of V-grooves, wherein the method includes optically aligning a core of each of the plurality of optical fibers with a respective one of the plurality of spot size converters before forming the soldered connections between the lid structure and the photonic integrated circuit chip (Figs11&15a-b/Spot size converters 1510; Paragraph 51).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 20130114924 A1) in view of Li [1] (US 20220196935 A1).
With regards to claims 8 and 16, Loh discloses the package assembly and method as recited in claims 1 and 9 respectively, further comprising: a package component (Fig13/Package component 1304), the photonic integrated circuit chip attached to the package component after the plurality of soldered connections are formed to secure the lid structure to the photonic integrated circuit chip, but is silent regarding flip-chip attachment. However, the practice of using flip-chip attachment to bind a photonic chip to a package via flip-chip attachment exists in the art as exemplified by Li [1].
Loh and Li [1] are considered to be analogous in the field of optical package formation. Loh and Lee each disclose a PIC chip attached to a package component (Loh/Fig13; Lee/Fig1a). Lee further teaches attaching PIC chip to the package component via flip-chip attachment (Li [1]/Paragraph 19/Lines 1-5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select flip chip bonding as the method by which to attach the PIC chip and package component of Loh as suggested by Li [1] since doing so would facilitate greater electrical and thermal performance in the completed device.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 20130114924 A1) in view of Li [2] (US 20220196943 A1).
With regards to claim 17, Loh discloses a method for manufacturing a package assembly, comprising:
having a photonic integrated circuit chip that includes an optical fiber attachment area (Figs15a-b/PIC chip 1502 and fiber attachment area [region defined by elements 1514]);
disposing at least one optical fiber within the optical fiber attachment area (Figs15a-b/At least one optical fiber 1512);
disposing a lid structure over the at least one optical fiber (FigsFigs15a-b/Lid structure 1518);
performing a first solder reflow process to form a first set of soldered connections between the lid structure and the photonic integrated circuit chip such that upon cooling of the first set of soldered connections the lid structure presses against the at least one optical fiber to mechanically hold the at least one optical fiber against the optical fiber attachment area (Figs15a-b/Soldered connections 1516; Paragraph 256); and
forming a package component (Fig13/Package component 1304).
Loh is silent regarding performing a second solder reflow process to form a second set of soldered connections between the photonic integrated circuit chip after forming the first set of soldered connections and the package component. However, the practice of using a second set of solders to bond a formed PIC chip to a package component exists in the art as exemplified by Li [2].
Loh and Li [2] are considered to be analagous in the field of optical package formation. Loh and Lee each disclose a PIC chip attached to a package component (Loh/Fig13; Lee/Fig1a). Lee further teaches formation of a second set of soldered connections between a PIC chip and package component (Li [2]/Soldered connections 103). Lee does not explicitly state that the solders are formed by a reflow process, but examiner notes that reflow is a well-known and expected standard for solder formation. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the PIC chip of Loh to the package component of Loh as suggested by Li [2] since doing so would facilitate conductivity between the PIC and package component of Li [2] while also increasing resistance to mechanical strain.
With regards to claim 18, Loh and Li [2] together disclose the method as recited in claim 17, wherein the second solder reflow process is performed to avoid disturbance of the first set of soldered connections so as to maintain mechanical hold of the at least one optical fiber against the optical fiber attachment area by the lid structure (Loh/Fig13; Li [2]/Fig1a).
With regards to claim 19, Loh and Li [2] together disclose the method as recited in claim 17, further comprising:
attaching a carrier component to a surface of the photonic integrated circuit chip opposite of the optical fiber attachment area (Li [2]/Fig1a/Carrier 120); and
attaching the carrier component to a fiber array unit that includes the at least one optical fiber (Li [2]/Fig1a/Fiber array unit 130).
With regards to claim 20, Loh and Li [2] together disclose the method as recited in claim 17, wherein the optical fiber attachment area includes an array of a plurality of V-grooves, wherein the photonic integrated circuit chip includes a plurality of spot size converters, each of the plurality of spot size converters exposed at an interior end of a respective one of the plurality of V-grooves, and wherein disposing the at least one optical fiber within the optical fiber attachment area includes respectively disposing a plurality of optical fibers within the plurality of V-grooves, wherein the method further includes optically aligning a core of each of the plurality of optical fibers with a respective one of the plurality of spot size converters before performing the first solder reflow process to form the first set of soldered connections (Loh/Figs15a-b).
Conclusion
This prior art, made of record, but not relied upon, is considered pertinent to applicant’s disclosure since the following references have similar structure and/or use similar structure and/or similar optical elements to what is disclosed and/or claimed in the instant application:
Yoo (US 20190310433 A1) [Figs 3d-3e]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marc E Manheim whose telephone number is (703)756-1873. The examiner can normally be reached 6:30am - 5pm E.T., Monday - Tuesday and Thursday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARC E MANHEIM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
Prosecution Insights