Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action responds to the Amendment filed on 7/22/2026 and IDS filed on 6/29/2026. Applicant's arguments filed with respect to the claims have been fully considered but they are not persuasive. The rejection of the claims is maintained under prior art previously cited. Applicant’s remarks are addressed in the Response to Applicant’s Remarks section cited below.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-9, 14-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (U.S. Pub. No. 2017/0250195 A1).
As per claim 1, Kim discloses:
A method of correcting a design layout of a semiconductor device, performed by a computing device, the method comprising:
separating a first target layer comprising a plurality of target patterns from an original design layout (See Figure 9, i.e. s210 – check location of first pattern in layout & Para [0085], i.e. stacked memory device may include a memory cell array area and a peripheral circuit area…the first pattern may include a contact pattern arranged in a peripheral circuit area, See Figures 10 & 11, See Para [0094]-[0099], i.e. The peripheral circuit area 230 may be adjacent to the memory cell array areas 210a and 210b and the row decoder areas 220a to 220c in the Y direction –[prior art separate circuit into different region, wherein target layer with patterns is in the peripheral circuit area is considered as the separating as cited above])
generating a second target layer by shifting the plurality of target patterns in the first target layer based on misalignment values at respective positions of the plurality of target patterns (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D –[prior art perform OPC by shifting pattern, considered as the generating as cited above]); and
combining the second target layer with the original design layout from which the first target layer is separated to generate a corrected design layout (See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [00138]-[0041], i.e. receive layout data and OPC data and may verify the OPC… mask may be used to form a contact in a peripheral circuit area of the stacked memory device, See Para [0100]-[0117], i.e. a contact may be formed by manufacturing a mask according to the second pattern PT2a –[prior art make correction to device pattern in a peripheral circuit area, wherein a mask is used to generate the device, therefore, the mask include the peripheral circuit area is used to generate the device, therefore include the combining of the correction in the peripheral circuit area into the mask that generate the device, considered as the combining as cited above]).
As per claim 2, Kim discloses all of the features of claim 1 discloses above wherein Kim also discloses wherein the separating the first target layer comprises generating a first semiconductor cell with the first target layer, and wherein the generating the second target layer comprises generating a second semiconductor cell by shifting the plurality of target patterns in the first semiconductor cell based on the misalignment values (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0068]-[0076], Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D).
As per claim 3, Kim discloses all of the features of claim 2 discloses above wherein Kim also discloses wherein the generating of the corrected design layout comprises disposing the second semiconductor cell in a top cell of the original design layout from which the first target layer is separated (See Para [0068]-[0076], Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D –[Figure 12, PT1 – 332 , is corrected considered as the top cell inside of ACT]).
As per claim 4, Kim discloses all of the features of claim 1 discloses above wherein Kim also discloses wherein the generating of the second target layer comprises generating the second target layer by shifting the plurality of target patterns in a direction that offsets misalignment by correction values, the correction values being determined based on the misalignment values at the respective positions of the plurality of target patterns (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D).
As per claim 5, Kim discloses all of the features of claim 4 discloses above wherein Kim also discloses generating data in which the respective positions of the plurality of target patterns are mapped with the misalignment values at the respective positions, wherein the generating of the second target layer comprises shifting the plurality of target patterns based on the data (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D).
As per claim 6, Kim discloses all of the features of claim 4 discloses above wherein Kim also discloses generating data in which the respective positions of the plurality of target patterns are mapped with the correction values at the respective positions, and wherein the generating of the second target layer comprises shifting the plurality of target patterns based on the data (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D).
As per claim 7, Kim discloses all of the features of claim 1 discloses above wherein Kim also discloses obtaining misalignment values in a plurality of regions on a wafer; and determining the misalignment values at the respective positions of the plurality of target patterns based on the misalignment values in the plurality of regions (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D).
As per claim 8, Kim discloses all of the features of claim 7 discloses above wherein Kim also discloses wherein the wafer is a wafer that is taped out with a mask to which the original design layout is applied (See Para [0041], i.e. receive layout data and OPC data and may verify the OPC…memory device is formed by performing various semiconductor processes on a semiconductor substrate such as a wafer by using the mask).
As per claim 9, Kim discloses all of the features of claim 7 discloses above wherein Kim also discloses wherein the wafer is a wafer for a same generation product as the original design layout (See Para [0038]-[0041], i.e. memory device is formed by performing various semiconductor processes on a semiconductor substrate such as a wafer by using the mask).
As per claim 14, Kim discloses all of the features of claim 1 discloses above wherein Kim also discloses wherein the semiconductor device comprises a memory device, and wherein the plurality of target patterns comprises gate patterns of sub-wordline drivers of the memory device (See Para [0039], i.e. misalignment of a contact formed along the second pattern may be prevented, and thus a potential failure of a semiconductor chip in which the stacked memory device, See Para [0052]-[0054], i.e. multiple word lines WL1 to WL8, multiple bit lines BL1 to BL3).
As per claim 15, Kim discloses all of the features of claim 1 discloses above wherein Kim also discloses validating the corrected design layout by comparing a number of the plurality of target patterns in the corrected design layout with a number of the plurality of target patterns in the original design layout (See Para [0038]-[0040], i.e. OPC verifying tool may receive layout data and OPC data and may verify the OPC, See Para [0083]-[0093], See Para [0100]-[0117] – [prior art verify layout meet specification is considered as the validating as cited above]).
As per claim 16, Kim discloses all of the features of claim 1 discloses above wherein Kim also discloses validating the corrected design layout based on a shift value between each of the plurality of target patterns in the corrected design layout and each of the plurality of target patterns in the original design layout (See Para [0038]-[0040], i.e. OPC verifying tool may receive layout data and OPC data and may verify the OPC, See Para [0083]-[0093], See Para [0100]-[0117] – [prior art verify layout meet specification is considered as the validating as cited above]).
As per claim 17, Kim discloses:
A computing device comprising: a memory configured to store one or more instructions; and one or more processors configured to execute the one or more the instructions, wherein the one or more processors are configured, by executing the one or more instructions (See Para [0038], i.e. tool may be a software module that includes multiple instructions executable on a processor, and may be stored in a non-transitory computer-readable storage medium),
to separate a target layer comprising a plurality of target patterns from a design layout of a semiconductor device (See Figure 9, i.e. s210 – check location of first pattern in layout & Para [0085], i.e. stacked memory device may include a memory cell array area and a peripheral circuit area…the first pattern may include a contact pattern arranged in a peripheral circuit area, See Figures 10 & 11, See Para [0094]-[0099], i.e. The peripheral circuit area 230 may be adjacent to the memory cell array areas 210a and 210b and the row decoder areas 220a to 220c in the Y direction –[prior art separate circuit into different region, wherein target layer with patterns is in the peripheral circuit area is considered as the separating as cited above]);
shift the plurality of target patterns in the target layer based on misalignment values at the plurality of target patterns (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D –[prior art perform OPC by shifting pattern, considered as the shift as cited above]); and
combine the target layer in which the plurality of target patterns are shifted with the design layout from which the target layer is separated to generate a corrected design layout (See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [00138]-[0041], i.e. receive layout data and OPC data and may verify the OPC… mask may be used to form a contact in a peripheral circuit area of the stacked memory device, See Para [0100]-[0117], i.e. a contact may be formed by manufacturing a mask according to the second pattern PT2a –[prior art make correction to device pattern in a peripheral circuit area, wherein a mask is used to generate the device, therefore, the mask include the peripheral circuit area is used to generate the device, therefore include the combining of the correction in the peripheral circuit area into the mask that generate the device, considered as the combining as cited above]).
As per claim 18, Kim discloses all of the features of claim 17 discloses above wherein Kim also discloses wherein the one or more processors are further configured to: generate a semiconductor cell comprising the target layer, shift the plurality of target patterns in the target layer by shifting the plurality of target patterns in the semiconductor cell based on the misalignment values at the plurality of target patterns (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D); and combine the semiconductor cell in which the plurality of target patterns are shifted with the design layout from which the target layer is separated to combine the target layer in which the plurality of target patterns are shifted with the design layout from which the target layer is separated ((See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [00138]-[0041], i.e. receive layout data and OPC data and may verify the OPC… mask may be used to form a contact in a peripheral circuit area of the stacked memory device, See Para [0100]-[0117], i.e. a contact may be formed by manufacturing a mask according to the second pattern PT2a).
As per claim 20, Kim discloses:
A method of fabricating a semiconductor device, comprising:
loading an original design layout (See Figure 9, i.e. s210 – check location of first pattern in layout);
separating a target layer comprising a plurality of target patterns from the original design layout (See Figure 9, i.e. s210 – check location of first pattern in layout & Para [0085], i.e. stacked memory device may include a memory cell array area and a peripheral circuit area…the first pattern may include a contact pattern arranged in a peripheral circuit area, See Figures 10 & 11, See Para [0094]-[0099], i.e. The peripheral circuit area 230 may be adjacent to the memory cell array areas 210a and 210b and the row decoder areas 220a to 220c in the Y direction –[prior art separate circuit into different region, wherein target layer with patterns is in the peripheral circuit area is considered as the separating as cited above]);
shifting the plurality of target patterns in the target layer based on misalignment values (See Figure 9, i.e. s230 & s250 – shift of first pattern…obtain difference value…through OPC, See Para [0087]-[0092], i.e. a difference value between a second location of a second pattern, which is formed through OPC with respect to the first pattern, and the first location of the first pattern is obtained, See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [0108]-[0117], i.e. the second pattern PT2a may be a pattern formed by performing an OPC with respect to the first pattern PT1, See Figures 12-14D –[prior art perform OPC by shifting pattern, considered as the shifting as cited above]);
combining the target layer in which the plurality of target patterns are shifted with the original design layout from which the target layer is separated to generate a corrected design layout (See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [00138]-[0041], i.e. receive layout data and OPC data and may verify the OPC… mask may be used to form a contact in a peripheral circuit area of the stacked memory device, See Para [0100]-[0117], i.e. a contact may be formed by manufacturing a mask according to the second pattern PT2a –[prior art make correction to device pattern in a peripheral circuit area, wherein a mask is used to generate the device, therefore, the mask include the peripheral circuit area is used to generate the device, therefore include the combining of the correction in the peripheral circuit area into the mask that generate the device, considered as the combining as cited above]);
manufacturing a mask based on the corrected design layout; and fabricating the semiconductor device based on the mask (See Para [0093], i.e. determined that a misalignment of a contact corresponding to the first pattern is accurately corrected, See Para [00138]-[0041], i.e. receive layout data and OPC data and may verify the OPC… mask may be used to form a contact in a peripheral circuit area of the stacked memory device, See Para [0100]-[0117], i.e. a contact may be formed by manufacturing a mask according to the second pattern PT2a)
Allowable Subject Matter
5. Claims 10-13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claim 10 and/or 19 – wherein
claims 11-13 depend on dependent claim 10.
Response to Applicant’s Remarks
7. With respect to Applicant’s remarks, the following are addressed:
Applicant's arguments filed with respect to the claims have been fully considered but they are not persuasive.
Applicant’s remarks (Pages 9 & 10), argues that the prior art does not teach “separating a first layer comprising plurality of target patterns from an original layout” and “shifting the plurality of target patterns in the first target layer based on misalignment values at respective positions of the plurality of target patterns”.
With respect to Applicant’s remarks, prior art Kim correction by shifting patterns in peripheral circuit area of a layout by shifting the patterns by shifting values calculated by different equations (See Para [0074], cited below:)
[0074] In the graph of FIG. 7, the peripheral circuit area PA is divided into three regions, but the peripheral circuit area PA is not limited thereto. In an embodiment, the peripheral circuit area PA may be divided into a higher number of regions along the Y direction. Then, the shift values of the patterns may be calculated by using different calculation equations for different regions. In an embodiment, the peripheral circuit area PA may be divided into two regions with respect to a reference line in the Y direction. For example, the shift direction of the patterns arranged on the reference line of the peripheral circuit area PA may be determined to be a positive direction. The shift direction of the patterns arranged under the reference line may be determined to be a negative direction.
The shift of the values of the patterns is isolated to the peripheral circuit area of a layout, which is isolate from memory area of a chip (See Para [0081], cited below: )
[0081] According to embodiments, a calculation equation for calculating the shift values of the patterns on the peripheral circuit area may be established based on the graph of FIG. 8. In detail, a calculation equation for calculating the shift values of the patterns may be established based on the distances between the patterns and the memory cell array area of the corresponding semiconductor chip and the distance between the memory cell array areas of the adjacent semiconductor chips, and also based on the locations of the patterns in the X direction.
Because prior art shift of patterns by values is within the peripheral circuit area, the prior art therefore teaches the separating a first layer comprising plurality of target patterns from an original layout as cited above.
In an example of shifting patterns in the peripheral circuit area, prior art shift gate contact pattern, source contact pattern, and drain contact pattern in the peripheral circuit area by shift value SV1, SV2, and SV3 (See Para [0103]-[0105] & Figure 12 & 13 )
[0103] The initial layout 300 may not properly reflect the shift of the silicon substrate corresponding to the peripheral circuit area 230 due to the stress during the cell array forming process. Accordingly, according to the present embodiment, in operation S210 of FIG. 9, the locations of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 in the initial layout 300 may be checked. In an embodiment, the Y coordinates of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 may be checked. Hereinafter, the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 may be referred to as first patterns PT1.
[0104] FIG. 13 illustrates first correction patterns PT1′ for the first patterns PT1 of FIG. 12, according to a pattern shift value calculating operation of an embodiment.
[0105] Referring to FIG. 13, the shift values SV1, SV2, and SV3 may be calculated according to the locations of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 corresponding to the first patterns PT1. As compared with the layout 300 of FIG. 12, the layout 300′ of FIG. 13 further includes a corrected gate contact pattern 331′, a corrected source contact pattern 332′, and a corrected drain contact pattern 333′. The corrected gate contact pattern 331′, the corrected source contact pattern 332′, and the corrected drain contact pattern 333′ may be formed based on shift values SV1, SV2, and SV3 respectively calculated for the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333. Hereinafter, the corrected gate contact pattern 331′, the corrected source contact pattern 332′, and the corrected drain contact pattern 333′ may be referred to as first corrected patterns PT1′.
Because prior art Kim shift multiple patterns by different shift values, therefore the prior Kim teach the limitations “shifting the plurality of target patterns in the first target layer based on misalignment values at respective positions of the plurality of target patterns”, as cited above.
Because the prior art have been shown to teach the limitations of the claims as cited above, the rejection of the claims is maintained under prior art Kim as cited above. This office action is Final.
Conclusion
8. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/ Primary Examiner, Art Unit 2851
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