Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/15/2023 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 6 and 8 – 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 20220209728 A1).
Regarding Independent Claim 1, Kim teaches,
A power amplifier (Fig. 1, 1000), comprising:
a power transistor (Fig. 1, 200) configured to amplify an input Radio Frequency (RF) signal (Fig. 1, RFin), and output the amplified signal (Fig. 1, RFout);
an overvoltage protection circuit (Fig. 1, 500) configured to detect a magnitude of the input RF signal (Fig. 1, magnitude of RFin), and detect a magnitude of an output RF signal of the power transistor (Fig. 1, magnitude of RFout), and generate an overvoltage output signal (Fig. 1, signal from 500) corresponding to the magnitude of the input RF signal and the magnitude of the output RF signal; and
a bias circuit (Fig. 1, 400) configured to generate bias current to bias the power transistor (Fig. 1, 200), and adjust the bias current based on the overvoltage output signal.
Regarding claim 2,
The power amplifier of claim 1, wherein:
the overvoltage protection circuit (Fig. 1, 500) is configured to generate the overvoltage output signal indicating an overvoltage state, when the magnitude of the input RF signal is greater than a first reference voltage and the magnitude of the output RF signal is greater than a second reference voltage (Fig. 1, 500 generates a signal when RFin and RFout are greater than the reference voltage. See paragraph [0053], “Depending on an external condition (e.g., battery conditions), the power supply voltage Vcc may enter an overvoltage state that is greater than an operating voltage state (a state exceeding a predetermined threshold value). When the power supply voltage Vcc is in the overvoltage state, the power transistor 200 may be damaged or destroyed. To prevent this situation, the overvoltage protection circuit 500 according to the example performs a function of protecting the power transistor 200 by detecting an overvoltage state of the power supply voltage Vcc.”).
Regarding claim 3,
The power amplifier of claim 2, wherein:
the bias circuit does not generate the bias current or reduce a magnitude of the bias current, when the overvoltage output signal indicates the overvoltage state (Fig. 400 reduces the bias current in order to function. See paragraph [0056], “The bias circuit 400 may supply a bias current Ibias biasing the power transistor 200. The power transistor 200 may set a bias level (i.e., a bias point) through the bias current Ibias provided from the bias circuit 400. In the example, the bias current Ibias is reduced in the overvoltage state due to operation of the overvoltage protection circuit 500”).
Regarding claim 4,
The power amplifier of claim 1, wherein:
the overvoltage protection circuit (Figs. 1 and 2, 500. See paragraph [0058], “FIG. 2 illustrates an example overvoltage protection circuit, in accordance with one or more embodiments.”) comprises:
an input detector (Fig. 2, Q1, Q2, C1, and Vcc) configured to detect the magnitude of the input RF signal (Fig. 1, RFin), an output detector (Fig. 1, Q3, Q4, C2, and Vref) configured to detect the magnitude of the output RF signal (Fig. 1, RFout), and an overvoltage discriminating unit configured to generate the overvoltage output signal corresponding to an output signal of the input detector and an output signal of the output detector.
Regarding claim 5,
The power amplifier of claim 4, wherein:
the input detector (Fig. 2, Q1, Q2, C1, and Vcc) comprises:
an amplifier transistor (Fig. 2, Q1) configured to amplify the input RF signal and output the amplified input RF signal, a diode (Fig. 2, Q2. See paragraph [0018], “The protection circuit may further include at least one additional transistor connected between the power supply voltage and the first terminal of the second transistor, and the at least one additional transistor may be configured to have a diode connection structure”) comprising an anode connected to an output terminal of the amplifier transistor (Fig. 2, Q1), and a first capacitor (Fig. 2, C1) that is connected between a cathode of the diode and a ground, and a voltage (Fig. 2, Vcc) to which the first capacitor (Fig. 2, C1) is charged corresponds to the magnitude of the input RF signal.
Regarding claim 6,
The power amplifier of claim 5, wherein:
the output detector (Fig. 1, Q3, Q4, C2, and Vref) comprises:
a plurality of diodes (Fig. 1, Q3 and Q4. See paragraph [0018], “The protection circuit may further include at least one additional transistor connected between the power supply voltage and the first terminal of the second transistor, and the at least one additional transistor may be configured to have a diode connection structure”) connected between an output terminal of the power transistor and the ground, and a second capacitor (Fig. 1, C2) connected between a node located between two of the plurality of diodes and the ground, and a voltage (Fig. 1, Vref) to which the second capacitor is charged is the magnitude of the output RF signal.
Regarding claim 8,
The power amplifier of claim 1, wherein:
the power transistor (Fig. 1, 200) comprises a first power transistor (Fig. 1, first transistor of 200) (See paragraph [0054]. “The power transistor 200 may be implemented as various transistors such as, but not limited to, a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and the like”) configured to amplify the input RF signal, and a second power transistor (Fig. 1, second transistor of 200) configured to amplify an output RF signal of the first power transistor, the bias circuit (Fig. 1, 400. See paragraph [0091], “The bias circuit 400 may be implemented with various structures.”) comprises a first bias circuit (Fig. 1, part of 400) configured to generate a first bias current to bias the first power transistor, and a second bias circuit (Fig. 1, part of 400 configured to generate a second bias current to bias the second power transistor, the magnitude of the output RF signal is a magnitude of an output RF signal of the second power transistor, and at least one of the first bias circuit and the second bias circuit (Fig. 1, 400) is configured to adjust its own bias current of the first bias current and the second bias current, corresponding to the overvoltage output signal.
Regarding Independent claim 9,
An operating method of a power amplifier (Fig. 1, 1000) that generates an output radio frequency (RF) signal (Fig. 1, RFout) by amplifying an input RF signal (Fig. 1, RFin), comprising:
detecting a magnitude of the input RF signal (Fig. 1, magnitude of RFin);
detecting a magnitude of the output RF signal (Fig. 1, magnitude of RFout);
determining an overvoltage state (Fig. 1, 500) when the magnitude of the input RF signal (Fig. 1, RFin) is greater than a first reference voltage and the magnitude of the output RF signal is greater than a second reference voltage (Fig. 1, 500 generates a signal when RFin and RFout are greater than the reference voltage. See paragraph [0053], “Depending on an external condition (e.g., battery conditions), the power supply voltage Vcc may enter an overvoltage state that is greater than an operating voltage state (a state exceeding a predetermined threshold value). When the power supply voltage Vcc is in the overvoltage state, the power transistor 200 may be damaged or destroyed. To prevent this situation, the overvoltage protection circuit 500 according to the example performs a function of protecting the power transistor 200 by detecting an overvoltage state of the power supply voltage Vcc.”); and
adjusting a bias level (Fig. 1, 400) to bias the power amplifier (Fig. 1, 1000), in the overvoltage state.
Regarding claim 10,
The method of claim 9, wherein:
the adjusting of the bias level comprises adjusting a bias current to be supplied to a power transistor included in the power amplifier (Fig. 400 adjusts the bias current in order to function. See paragraph [0056], “The bias circuit 400 may supply a bias current Ibias biasing the power transistor 200. The power transistor 200 may set a bias level (i.e., a bias point) through the bias current Ibias provided from the bias circuit 400. In the example, the bias current Ibias is reduced in the overvoltage state due to operation of the overvoltage protection circuit 500”).
Regarding claim 11,
The method of claim 10, wherein:
the adjusting the bias current comprises not generating the bias current or reducing a magnitude of the bias current (Fig. 400 reduces the bias current in order to function. See paragraph [0056], “The bias circuit 400 may supply a bias current Ibias biasing the power transistor 200. The power transistor 200 may set a bias level (i.e., a bias point) through the bias current Ibias provided from the bias circuit 400. In the example, the bias current Ibias is reduced in the overvoltage state due to operation of the overvoltage protection circuit 500”).
Regarding claim 12,
The method of claim 9, wherein:
the magnitude of the input RF signal corresponds to an envelope of the input RF signal (See paragraph [0048], “The examples may be applied to envelope elimination and restoration (EER) a power amplifier, a digital predistortion power amplifier, a Doherty power amplifier, a switch mode power amplifier, a GaN power amplifier and a CMOS power amplifier.”).
Regarding claim 13,
The method of claim 9, wherein:
the power transistor (Fig. 1, 200) comprises a first power transistor (Fig. 1, first transistor of 200) (See paragraph [0054]. “The power transistor 200 may be implemented as various transistors such as, but not limited to, a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and the like”) configured to amplify the input RF signal, and a second power transistor (Fig. 1, second transistor of 200) configured to amplify an output RF signal of the first power transistor, and the magnitude of the output signal is a magnitude of an output RF signal of the second power transistor.
Regarding claim 14,
The method of claim 9, wherein:
the detecting the magnitude of the input RF signal comprises:
amplifying the input RF signal, and detecting an envelope of the amplified input RF signal (See paragraph [0048], “The examples may be applied to envelope elimination and restoration (EER) a power amplifier, a digital predistortion power amplifier, a Doherty power amplifier, a switch mode power amplifier, a GaN power amplifier and a CMOS power amplifier.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 15 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen et al. (US 20140077867 A1), hereinafter Chen.
Regarding claim 7, Kim is silent regarding:
the overvoltage discriminating unit comprises:
a first comparator configured to compare the output signal of the input detector with a first reference voltage, a second comparator configured to compare the output signal of the output detector with a second reference voltage, and an AND gate configured to receive an output signal of the first comparator and an output signal of the second comparator, and output the overvoltage output signal.
Chen discloses:
the overvoltage discriminating unit (Fig. 4, 4041) comprises:
a first comparator (Fig. 4, I2) configured to compare the output signal of the input detector with a first reference voltage, a second comparator (Fig. 4, I3) configured to compare the output signal of the output detector with a second reference voltage, and an AND gate (Fig. 4, I4) configured to receive an output signal of the first comparator and an output signal of the second comparator, and output the overvoltage output signal.
Kim and Chen are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include comparators and an AND gate in Kim‘s design in order to compare the input and output signals and output the overvoltage signal in accordance with Chen‘s design.
Regarding Independent claim 15,
A power amplifier (Fig. 1, 1000), comprising:
a first transistor and a second transistor (Fig. 1, 200) (See paragraph [0054]. “The power transistor 200 may be implemented as various transistors such as, but not limited to, a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and the like”) configured to amplify an input radio frequency (RF) signal;
one or more bias circuits (Fig. 1, 400) configured to generate bias currents, and supply the generated bias currents to the first transistor and the second transistor (Fig. 1, 200);
an overvoltage protection circuit (Fig. 1, 500), comprising a first comparator configured to receive an input RF signal, compare a magnitude of the input RF signal to a first reference voltage, and output a first signal;
a second comparator configured to receive an output RF signal, compare a magnitude of the output RF signal to a second reference voltage, and output a second signal; and
an AND gate configured to receive the first signal and the second signal, and output a third signal.
Kim is silent regarding:
an overvoltage protection circuit (Fig. 1, 500), comprising a first comparator configured to receive an input RF signal, compare a magnitude of the input RF signal to a first reference voltage, and output a first signal;
a second comparator configured to receive an output RF signal, compare a magnitude of the output RF signal to a second reference voltage, and output a second signal; and
an AND gate configured to receive the first signal and the second signal, and output a third signal.
Chen teaches:
an overvoltage protection circuit (Fig. 1, 500), comprising a first comparator (Fig. 4, I2) configured to receive an input RF signal, compare a magnitude of the input RF signal to a first reference voltage, and output a first signal;
a second comparator (Fig. 4, I3) configured to receive an output RF signal, compare a magnitude of the output RF signal to a second reference voltage, and output a second signal; and
an AND gate (Fig. 4, I4) configured to receive the first signal and the second signal, and output a third signal.
Kim and Chen are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include comparators and an AND gate in Kim‘s design in order to compare the input and output signals and output the overvoltage signal in accordance with Chen‘s design.
Regarding claim 16,
The power amplifier of claim 15, wherein the third signal is an overvoltage output signal (Fig. 1, 500 outputs the third signal).
Regarding claim 17,
The power amplifier of claim 16, wherein the one or more bias circuits (Fig. 1, 400) are configured to receive the overvoltage output signal, and adjust a bias current based on the overvoltage output signal (Fig. 400 adjusts the bias current in order to function. See paragraph [0056], “The bias circuit 400 may supply a bias current Ibias biasing the power transistor 200. The power transistor 200 may set a bias level (i.e., a bias point) through the bias current Ibias provided from the bias circuit 400. In the example, the bias current Ibias is reduced in the overvoltage state due to operation of the overvoltage protection circuit 500”).
Regarding claim 18,
The power amplifier of claim 15, wherein the output RF signal is output from at least one of the first transistor and the second transistor (Fig. 1, RFour is from 200).
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843