Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/15/2023 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 15-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the “computer-readable storage medium” encompasses both transitory/signal media and non-transitory media. Therefore, it could be interpreted as a signal and is not limited to the statutory non-transitory media. It is suggested that claim 15 be amended to recite only a “non-transitory” computer-storage readable medium to overcome this rejection.
Claims 16-20 do not resolve this issue and are similarly rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, 11, 12, 15, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nunes Coelho, Jr. (US 20240220867 A1, hereafter referred to as Nunes).
Regarding claim 1, Nunes discloses “implementing a quantization scheme allowing at most one (1), non-zero-valued bit in the mantissa of a floating point number” (See [0046]; Nunes discloses a quantization scheme that uses a 1-bit mantissa)
Regarding claim 8, this claim is similar in scope to claim 1.
Regarding claim 11, Nunes discloses “wherein the computer hardware adapted to performing the mathematical calculation and implementing the quantization scheme represents a simplified version of the computer hardware in lieu of a previously adapted portion of the computer hardware performing the mathematical calculation but not implementing the quantization scheme.” (See [0021]; Nunes discloses a hardware setup that can perform the mathematical operation and quantization scheme in an Artificial Intelligence core using low-cost programmable hardware that is suitable for running a modified neural network)
Regarding claim 12, Nunes discloses “the computer hardware adapted to perform the mathematical operation and implement the quantization scheme is realized in an Artificial Intelligence (AI) core of the computer hardware” (See [0021]; Nunes discloses a hardware setup that can perform the mathematical operation and quantization scheme in an Artificial Intelligence core using low-cost programmable hardware that is suitable for running a modified neural network)
Regarding claim 15, Nunes discloses “one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instruction comprising:” (See [0124]; Nunes discloses computer readable storage media that stores program instructions)
“implementing a quantization scheme allowing at most one (1), non-zero-valued bit in the mantissa of a floating point number” (See [0046]; Nunes discloses a quantization scheme that uses a 1-bit mantissa)
Regarding claim 20, Nunes discloses “further including program instructions for leveraging simplifications of a hardware design of the computing environment made possible by implementation of the quantization scheme.” (See [0054], [0124]; Nunes discloses that the quantization scheme that quantizes inputs and outputs allows for the use of simpler hardware designs, and that the quantization scheme can be implemented as one or more computer programs)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nunes Coelho, Jr. (US 20240220867 A1, hereafter referred to as Nunes) in view of Li (US 20230153586 A1) and Cowley (US 20240259701 A1).
Regarding claim 2, Nunes fails to explicitly disclose, “the mathematical calculation is a multiplication operation, and implementing a quantization scheme further includes truncating digits remaining after the occurrence of the first non-zero-valued bit of the floating point number, such that the remaining bits in the floating point number are designated as zero bits”.
Li teaches “the mathematical calculation is a multiplication operation, and implementing a quantization scheme further includes truncating digits remaining after the occurrence of the first non-zero-valued bit of the floating point number” (See [0026]; Li discloses truncating digits from a number by keeping only the most significant bits of a number during a multiplication operation, which can be interpreted as truncating all digits after the first non-zero-valued bit).
Li fails to explicitly disclose, “such that the remaining bits in the floating point number are designated as zero bits”.
Cowley teaches “such that the remaining bits in the floating point number are designated as zero bits” (See [0020]; Cowley discloses that truncating a number should set the truncated digits to zero instead of removing them from the number).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention having Nunes, Li, and Cowley before them to modify Nunes to truncate digits after the first non-zero-valued bit for a multiplication operation as well as setting the remaining bits to zero. One would be motivated to truncate after the first non-zero-valued bit to compress the data of the floating point number, see e.g., [0024], where Li teaches that truncation can partially compress the data of a floating point number. One would be motivated to set the remaining bits after the first non-zero-valued bit to zero instead of removing them in order to maintain the original number of bits in the floating point number while compressing the floating point number’s data.
Regarding claims 9 and 16, these claims are similar in scope to claim 2.
Claim Rejections - 35 USC § 103
Claims 3, 10, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Nunes Coelho, Jr. (US 20240220867 A1, hereafter referred to as Nunes), in view of Tripathi (US 20120229497 A1).
Regarding claim 3, Nunes fails to explicitly disclose, “the mathematical calculation is a multiplication operation, and implementing a quantization scheme further includes rounding digits remaining after the occurrence of the first non-zero-valued bit of the floating point number, such that the remaining bits in the floating point number round up or down depending on which value is closer”.
Tripathi teaches “the mathematical calculation is a multiplication operation, and” (See [0031], [0044]; Tripathi discloses that dithering component 72 is part of image processing component 20, which uses any suitable dithering algorithm, including Floyd-Steinberg dithering, which is an algorithm that uses multiplication operations)
“implementing a quantization scheme further includes rounding digits remaining after the occurrence of the first non-zero-valued bit of the floating point number, such that the remaining bits in the floating point number round up or down depending on which value is closer” (See [0044]; Tripathi discloses performing dithering for an image by rounding a number's most significant bits (first non-zero-valued bit) up or down based on the least significant bits (remaining bits in the number after the first non-zero-valued bit)).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention having Nunes and Tripathi before them to modify Nunes to use a quantization scheme that rounds digits after the first non-zero-valued bit for use in a multiplication operation. One would be motivated to round digits after the first non-zero-valued bit to reduce the size of a floating point number, see e.g., [0044], where Tripathi uses rounding to produce lower-bit-depth images that use smaller floating point numbers.
Regarding claims 10 and 17, these claims are similar in scope to claim 3.
Claim Rejections - 35 USC § 103
Claims 4, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Nunes Coelho, Jr. (US 20240220867 A1, hereafter referred to as Nunes), in view of Nair (US 20220107782 A1).
Regarding claim 4, Nunes fails to explicitly disclose, “implementing the quantization scheme on a first one of two floating point numbers to undergo a matrix multiplication operation”.
Nair teaches “implementing the quantization scheme on a first one of two floating point numbers to undergo a matrix multiplication operation” (See [0014]; Nair discloses using matrix multiplication on a first floating point number with a second floating point number).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention having Nunes and Nair before them to modify Nunes to use a matrix multiplication operation on a first of two floating point numbers. One would be motivated to use matrix multiplication on two floating point numbers to perform many multiplication calculations at the same time, see e.g., [0015], where Nair teaches that multiple processing elements can be used in matrix multiplications, and that the number of computed elements can be scaled up depending on the computation and data requirements.
Regarding claim 5, Nunes discloses “enabling the computer hardware required to perform the mathematical operation and implement the quantization scheme in an Artificial Intelligence (AI) core of the computer hardware” (See [0021]; Nunes discloses a hardware setup that can perform the mathematical operation and quantization scheme in an Artificial Intelligence core using low-cost programmable hardware that is suitable for running a modified neural network)
Claim Rejections - 35 USC § 103
Claims 6, 13, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nunes Coelho, Jr. (US 20240220867 A1, hereafter referred to as Nunes), in view of Schmookler (Leading zero anticipation and detection - a comparison of methods).
Regarding claim 6, Nunes fails to explicitly disclose, “examining the floating point number to locate the occurrence of the first non-zero-valued bit of the floating point number”.
Schmookler teaches “examining the floating point number to locate the occurrence of the first non-zero-valued bit of the floating point number” (See [Page 10, Section 3.1, Paragraph 1, 2]; Schmookler discloses a method of examining a floating point number to locate the occurrence of the first non-zero bit).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention having Nunes and Schmookler before them to modify Nunes to find the first non-zero-valued bit in the floating point number. One would be motivated to search for the first non-zero-valued bit to perform an operation on the floating point number, see e.g., [Page 7, Section 1, Paragraph 1], where Schmookler teaches that locating the position of the first non-zero-valued bit (most significant bit) is done to normalize the floating point number during floating point addition.
Regarding claims 13 and 18, these claims are similar in scope to claim 6.
Claim Rejections - 35 USC § 103
Claims 7, 14, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nunes Coelho, Jr. (US 20240220867 A1, hereafter referred to as Nunes), in view of Nealis (US 10410098 B2).
Regarding claim 7, Nunes fails to explicitly disclose, “implementing the quantization scheme using a modified floating point unit (FPU), and in part, a barrel shifter realized as hardware in the FPU”.
Nealis teaches “implementing the quantization scheme using a modified floating point unit (FPU), and in part, a barrel shifter realized as hardware in the FPU” (See [Page 52, Col 11, Lines 5-8], [Page 63, Col 33, Lines 40-58]; Nealis discloses implementing a FPU and barrel shifter for quantization on a GPGPU core. The FPU can be a modified FPU, as Nealis describes using FPUs with differing precisions as a potential architecture configuration with a FPU).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention having Nunes and Nealis before them to modify Nunes to use a modified FPU and a barrel shifter for the quantization scheme. One would be motivated to use this hardware to perform quantization operations that benefit from dedicated hardware, see e.g., [Page 52, Col 11, Lines 5-8] where Nealis uses GPGPU cores that can use various different configurations, which include using single precision and double precision FPUs that can be used for floating point arithmetic with various precision configurations, and [Page 63, Col 33, Lines 40-58], where Nealis uses a barrel shifter for quantizing weights to accelerate processing operations.
Regarding claims 14 and 19, these claims are similar in scope to claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID KIM whose telephone number is (571)272-4331. The examiner can normally be reached 7:30 AM - 4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Ell can be reached at (571) 270-3264. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.K./Examiner, Art Unit 2141
/MATTHEW ELL/Supervisory Patent Examiner, Art Unit 2141
Prosecution Insights