DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/12/2026 has been entered.
Claim Objections
3. Claim 18 is objected to because of the following informalities: On line 6, “or” should be placed after “;” similar to claim 7. Appropriate correction is required.
Response to Arguments
4. On pg. 11, par. 2 of Applicant’s Response, applicant argues that Kang does not disclose that the inhibiting circuit is configured to inhibit a module by setting a data input/output of said module to a high impedance state, by applying a signal corresponding to an active state to an initialization signal input of the module to be inhibited as recited in claim 1.
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Examiner respectfully disagrees with applicant’s argument.
When U3 (~second SIM) is inserted, U1 (~processor) sends to U3 (~second SIM) a reset signal on RST pin to initialize the newly inserted U3 (~second SIM) and synchronize communication between the U1 (~processor) and U3 (~second SIM). This forces U3 (~second SIM) to restart, allowing it to switch to a powered-on ready to be read state.
Since RST pin of U1 (~processor), U2 (~first SIM), and U3 (~second SIM) are all connected, the reset signal from U1 (~processor) also goes to RST pin of U2 (~first SIM), putting I/O data pin of U2 (~first SIM) into a high impedance state (inhibiting U2 (~first SIM) and to allow the U1 (~processor) to pull it high or low to initiate communication).
5. On pg. 12, pars. 2-3 of Applicant’s Response, applicant argues that applicant respectfully submits that while Kang shows an RST bus (highlighted in blue) connecting the RST output of U1 and the RST inputs of U2 and U3, Kang does not disclose that, when U3 is inserted, an RST signal applied by U1 to the RST input pin of U2 and puts the I/O data pin of U2 into a high impedance state. The effects of applying an RST signal to RST pins of U2 and U3 over the RST bus are not described by Kang. Applicant respectfully submits that the Advisory Action’s statement is pure speculation of how the device of Kang work, but in absence of any factual basis to support this statement.
Examiner respectfully disagrees with applicant’s argument. During a reset, when applying a reset signal to a reset pin, the data I/O pin is released to a high-impedance state, allowing the master (modem) to control the line before a communication begins. The purpose of this is to prevent electrical contention, allowing the terminal to drive the data I/O pin to pull it high, signaling the beginning of the Answer to Reset (ATR) sequence. It's not just a speculation, it's a requirement for the electrical interface to ensure the SIM card can communicate with different voltage levels as schematically illustrated in Fig. 1 of Kang.
6. On pg. 13, pars. 1-2 of Applicant’s Response, applicant argues that “When the equipment is in an abnormal working state and needs to use the SIM card, the SIM card is inserted, the micro switch of the SIM card module U3 enables the 5 pin SW to be disconnected, Q3 is conducted, Q2 is conducted, Q1 is disconnected, and U1 reads the registration information of U3. After insertion of U3, U1 no longer reads the registration information of U2, DATA (PIN 4) of U2 and DATA (PIN 4) of U1 are isolated by Q1 device, and Q1 is disconnected or jointly controlled by Q2 and R4, Q2 is disconnected or jointly controlled by Q3, R6 and VDD (PIN 1) of U1, and Q3 is disconnected or jointly controlled by R5, VDD (PIN 1) of U1 and SW (PIN 5) of U3” of Kang does not mention the use of an RST signal to achieve inhibition of module U2. This confirms the Applicant's understanding that 'inhibition' of module U2 of Kang does not make use of an RST signal and that this inhibition is achieved only by cutting off module U2 from the data bus using transistor Q1.
Examiner respectfully disagrees with applicant’s argument. The cited paragraph of Kang describes the circuitry which continues the high-impedance state of the module U2’s I/O data pin initially generated by applying a reset signal to a reset pin of the module U2.
7. On pg. 14, par. 2 of Applicant’s Response, applicant argues that applicant as stated in response to the Final Office Action, RST signal management is not described by Kang - it is not even clear how processor U1 detects the presence of module U3, since no hardware connection is shown for this purpose that would communicate the information that module U3 is present to processor U1.
Examiner respectfully disagrees with applicant’s argument. Fig. 1 of Kang has a circuitry of a modem/processor reading from either of the two SIMs. modem/processor reading from a SIM is a standard process requiring a resetting step (RST signal management).
How the processor U1 detects the module U3 does not affect the function of the processor U1 applying a reset signal to the module U3. Kang’s Fig. 1 describes a circuit for the processor U1 detecting the module U3, but does not explicitly disclose what method it uses among many available methods currently in practice (such as probing, polling, commands, and etc.).
8. On pg. 14, par. 3 of Applicant’s Response, applicant argues that there is no factual basis in Kang to support that the speed at which processor U1 would generate an RST signal would be greater than the speed at which the circuits (highlighted in red in the drawing) cut off the Data I/O pin from the data bus. U1 would first need to become aware of the presence of U3, execute the appropriate software code and generate an RST signal. Rather, U1 is likely to take more time to generate an RST signal than the time required to switch three FETs, given that executing software requires activating many thousands of transistors and other components within processor U1.
Examiner respectfully disagrees with applicant’s argument. A time delay of a 5-pin mechanical switch alone is around 5-20 ms. Just taking into account the delay from the 5-pin mechanical switch makes a switch signal via the discreet transistors path lot longer than a reset signal sent from the processor U1.
9. On pg. 14, par. 4 of Applicant’s Response, applicant argues that resetting module U2 and U3 simultaneously without the circuits in red having first disconnected the Data I/O pin of module U2 from the data bus may lead to conflicts on the data bus and that U1 would not know whether 'registration information' of module U2 or U3 is to be read and used. The circuits highlighted in red do not have this disadvantage, by avoiding such conflict by cutting off access of module U2 to the data bus - only the registration information of module U3 may then be read by processor U1.
Examiner respectfully disagrees with applicant’s argument. Even if both SIMs (U2 and U3) are reset simultaneously, the modem communicates with them sequentially. The modem polls each SIM's I/O line, asking for their Answer To Reset (ATR) message, which is a standardized handshake.
10. On pg. 15, par. 1 of Applicant’s Response, applicant argues that moreover, an RST signal applied to module U2 would only have a temporary effect during the short time of the reset, and not inhibit module U2 in a way that would enable processor U1 to communicate with module U3 (which, in addition, would be reset at the same time as module U2 if one followed the Advisory Action's reasoning). Claim 1 is amended herein as follows to dispel any doubt about that inhibition of the second module cannot be based on a spurious reset: an inhibiting circuit for inhibiting the first module according to the presence signal, the device being configured to operate with the second
module as long as the first module is inhibited [...]
Examiner respectfully disagrees with applicant’s argument. An inhibiting circuit includes both the processor U1 and the 5-pin switch-transistors-resistors connected circuitry. Therefore, when the reset from the processor U1 generating a high impedance on a data pin of the first module U2 ends, the high impedance on the data pin of the first module U2 is continued by the 5-pin switch-transistors-resistors connected circuitry. Furthermore, in Fig. 1 of Kang, the device is configured to operate with the second module U3 as long as the first module U2 is inhibited.
Claim Rejections - 35 USC § 102
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
12. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
13. Claims 1-5, 8-9, and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang ("SIM Card Automatic Switching Circuit for Internet-of-Things Gas Meter", CN108416928A, pub. date 2018-08-17).
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Regarding claim 1, Kang teaches a device (Fig. 1, entire Fig. 1 is a device) comprising:
an interface for a subscriber identification module (Fig. 1, SIM_VDD (18), SIM-RTS (17), SIM_CLK (16), and SIM DATA (15) of U1 (~processor));
a first subscriber identification module connected to said interface (Fig. 1, VDD (1), RST (2), CLK (3), and DATA (4) of U2 (eSIM) (~first subscriber identification module) connected to said interface (~SIM DATA (15), SIM_CLK (16), SIM-RTS (17), SIM_VDD (18) of U1));
a connector suitable for connecting a second subscriber identification module to said interface when the second module is present in the connector (Fig. 1, a connector suitable for connecting a second subscriber identification module (~U3) to said interface (~of U1) when the second module (~U3) is present in the connector (pg. 5, par. 4, “After inserting U3”, wherein the second subscriber identification module (U3) is inserted into the connector (~socket)));
a presence detector configured to generate a presence signal of the second module in the connector (pg. 5, par. 4, when plugged in, U3 generates and sends a presence signal (~pin 5 SW (~switch) signal) to Q3, turning on Q3); and
an inhibiting circuit for inhibiting the first module according to the presence signal, the device being configured to operate with the second module when as long as the first module is inhibited (Fig. 1, when U3 (~second subscriber identification module) is inserted, Q3 is turned on, Q2 is turned on, and Q1 is turned off, thus, U2 (~first subscriber identification module) data is disconnected (~inhibited) from U1 (~based on Q1 being off) according to the pin 5 switch signal (~presence signal); An inhibiting circuit includes both the processor U1 and the 5-pin switch-transistors-resistors connected circuitry. Therefore, when the reset from the processor U1 generating high impedance on data pin of U2 ends, the high impedance on the data pin of the U2 SIM module is continued by the 5-pin switch transistors connected circuitry. Therefore, in Fig. 1 of Kang, the device is configured to operate with the second SIM module U3 as long as the first SIM module U2 is inhibited),
wherein the inhibiting circuit is configured to inhibit a module by setting a data input/output of said module to a high impedance state, by applying a signal corresponding to an active state to an initialization signal input of the module to be inhibited (When U3 (~second SIM) is inserted, U1 (~processor) sends to U3 (~second SIM) a reset signal on RST pin to initialize the newly inserted U3 (~second SIM) and synchronize communication between the U1 (~processor) and U3 (~second SIM). This forces U3 (~second SIM) to restart, allowing it to switch to a powered-on ready to be read state; Since RST pin of U1 (~processor), U2 (~first SIM), and U3 (~second SIM) are all connected, the reset signal from U1 (~processor) also goes to RST pin of U2 (~first SIM), putting I/O data pin of U2 (~first SIM) into a high impedance state (inhibiting U2 (~first SIM) and to allow the U1 (~processor) to pull it high or low to initiate communication)).
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Regarding claim 2, Kang teaches the device according to claim 1, including:
a data bus interconnecting a data input/output of the interface, the input/output of the first module and an input/output of the connector which functionally cooperates with a data input/output of the second module when the second module is present in the connector (Fig. 1, bus comprising DATA interconnects U1 (~comprising interface), U3, and U2); and
a clock signal bus interconnecting a clock signal output of the interface, a clock signal input of the first module and an input of the connector which functionally cooperates with a clock signal input of the second module when the second module is present in the connector (Fig. 1, bus comprising CLK interconnects output of U1 (~comprising interface), input of U3 (~second module), and input of U2 (~first module)).
Regarding claim 3, Kang teaches the device according to claim 1,
wherein the inhibiting circuit comprises a circuit controlled by the presence signal to automatically inhibit the first module when the second module is present in the connector, the device then operating with the second module via said interface (Fig. 1, when U3 (~second module) is inserted into connector (~socket), SW (~pin 5) of U3 (~second module) sends a presence signal to Q3, turning on Q3, turning on Q2, and turning off Q1; Q1 turning off inhibits operation with U2 (~first module) and allows operation with U3 (~second module)).
Regarding claim 4, Kang teaches the device according to claim 3,
wherein the circuit is controlled by the presence signal to automatically disinhibit the first module when the second module is removed from the connector, the device then operating with the first module via said interface (Fig. 1, when U3 (~second module) is removed from the connector (~socket of U3), Q3 and Q2 are turned off, and Q1 is turned on, U1 (~processor) of the device then operates with U2 (~first module) via said interface of U1 (~processor)).
Regarding claim 5, Kang teaches the device according to claim 3,
wherein:
an initialization signal output of the interface is connected to a first input of the connector, the connector being suitable for connecting the first input to an initialization signal input of the second module when the second module is present in the connector (Fig. 1, initialization signal output of the interface (~RST (pin 17) of U1) is connected to an input of the connector (~RST (pin 2) of U3), the connector being suitable for connecting the first input to an initialization signal input of the second module (~RST (pin 2) of U3) when the second module (~U3) is present in the connector (~when U3 (~second module) is plugged into the connector (~socket)));
a resistor is connected between the initialization signal input of the second module and the initialization signal output of the interface (Fig. 1, resistor R1 is connected between the initialization signal input of the second module (~RST (pin 2) of U3) and the initialization signal output of the interface (~RST (pin 17) of U1 (~processor))),
the resistor being suitable for allowing said interface (Fig. 1, resistor R1 is connected between the initialization signal input of the second module (~RST (pin 2) of U3) and the initialization signal output of the interface (~RST (pin 17) of U1 (~processor))) to
control an initialization of the second module when it is present in the connector and the first module is inhibited (Fig. 1, resistor R1 controls an initialization (~rst (reset)) of the second module (~U3) when it (~U3) is present in the connector (~socket of U3) and the first module (~U2) is inhibited (~due to Q1 being off)); and
control an initialization of the first module when the second module is not present in the connector and the first module is not inhibited (Fig. 1, controls an initialization (~rst (reset)) of the first module (U2) when the second module is not present in the connector (~U3 not inserted into the connector (~socket)) and the first module (~U2) is not inhibited (~due to Q1 being on)).
Regarding claim 8, Kang teaches a method performed by a device (Fig. 1, entire Fig. 1 is a device) comprising
an interface for subscriber identification module (Fig. 1, SIM_VDD (18), SIM-RTS (17), SIM_CLK (16), and SIM DATA (15) of U1 (~processor));
a first subscriber identification module connected to said interface (Fig. 1, VDD (1), RST (2), CLK (3), and DATA (4) of U2 (eSIM) (~first subscriber identification module) connected to said interface (~SIM DATA (15), SIM_CLK (16), SIM-RTS (17), SIM_VDD (18) of U1));
a connector suitable for connecting a second subscriber identification module to said interface when the second module is present in the connector (Fig. 1, a connector suitable for connecting a second subscriber identification module (~U3) to said interface (~of U1) when the second module (~U3) is present in the connector (~pg. 5, par. 4, “After inserting U3”, wherein the second subscriber identification module (U3) is inserted into the connector (~socket)));
a processor and a memory including software code which, when it is executed by the processor, causes the device to carry out the method (Fig. 1, U1 comprises a processor and a memory including software code which, when it is executed by the processor, causes the device to carry out the method), the method comprising:
detecting the presence of the second module in the connector (Fig. 1, pg. 5, par. 4, “When the device is in an abnormal working state and needs to use the SIM card, insert the SIM card. The micro switch of the SIM card module U3 disconnects the 5-pin SW, Q3 is turned on, Q2 is turned on, Q1 is turned off, and U1 is read. It is the registration information of U3”, wherein U1 (processor) needs to detect an inserted SIM (~U3) prior to performing read of the registration information from the SIM (~U3));
inhibiting the first module according to the presence signal (Fig. 1, U1 (~processor) via data signal (~pin 15) to Q1 via resistor R3, produces a voltage at a connection point to Q1, allowing for turn off of Q1 inhibiting U2 (~first module) according to SW signal (~presence signal) from U3 (~second module)); and
as long as the first module is inhibited, operating the device with the second module (Fig. 1, as long as U3 (~second module) is inserted and U2 (~first module) is inhibited, U1 (~processor) operates the device with U3 (~second module));
wherein the inhibition comprises setting a data input/output of the module to be inhibited to a high impedance state, by applying a signal corresponding to an active state to an initialization signal input of the module to be inhibited (When U3 (~second SIM) is inserted, U1 (~processor) sends to U3 (~second SIM) a reset signal on RST pin to initialize the newly inserted U3 (~second SIM) and synchronize communication between the U1 (~processor) and U3 (~second SIM). This forces U3 (~second SIM) to restart, allowing it to switch to a powered-on ready to be read state; Since RST pin of U1 (~processor), U2 (~first SIM), and U3 (~second SIM) are all connected, the reset signal from U1 (~processor) also goes to RST pin of U2 (~first SIM), putting I/O data pin of U2 (~first SIM) into a high impedance state (inhibiting U2 (~first SIM) and to allow the U1 (~processor) to pull it high or low to initiate communication)).
Regarding claim 9, Kang teaches the method according to claim 8 comprising selectively inhibiting and disinhibiting, respectively, one of the first and second modules (Fig. 1, when U3 (~second module) is inserted into connector (~socket), SW (~pin 5) of U3 (~second module) sends a presence signal to Q3, turning on Q3, turning on Q2, and turning off Q1; Q1 turning off disallows (~inhibits) operation with U2 (~first module) and allows (~disinhibits) operation with U3 (~second module));
disinhibiting and inhibiting, respectively, the other one of the first and second modules (Fig. 1, when U3 (~second module) is removed from the connector (~socket of U3), Q3 and Q2 are turned off, and Q1 is turned on, U1 (~processor) of the device then stops operating (~inhibits) with U3 (~second module) and operates (~disinhibits) with U2 (~first module) via said interface of U1 (~processor)); and
operating with the disinhibited module (Fig. 1, when U3 (~second module) is removed from the connector (~socket of U3), Q3 and Q2 are turned off, and Q1 is turned on, U1 (~processor) of the device then stops operating (~inhibits) with U3 (~second module) and operates (~disinhibits) with U2 (~first module) via said interface of U1 (~processor)).
Regarding claim 11, Kang teaches a non-transitory storage medium readable by a device provided with a processor, said medium comprising instructions which, when the program is executed by a processor of a device, causes the device to carry out the method according to claim 8 (Fig. 1, device comprises U1 (~processor) with memory (~non-transitory storage medium) comprising instructions when executed causes the device to; Fig. 1, processor U1’s data signal generates a voltage at emitter of Q1 to turn off when SW (pin 5) signal of U3 turns on Q3 and Q2).
Regarding 12, Kang teaches a device (Fig. 1, entire Fig. 1 is a device) comprising:
an interface for a subscriber identification module (Fig. 1, SIM_VDD (18), SIM-RTS (17), SIM_CLK (16), and SIM DATA (15) of U1 (~processor));
a first subscriber identification module connected to said interface (Fig. 1, VDD (1), RST (2), CLK (3), and DATA (4) of U2 (eSIM) (~first subscriber identification module) connected to said interface (~SIM DATA (15), SIM_CLK (16), SIM-RTS (17), SIM_VDD (18) of U1));
a connector suitable for connecting a second subscriber identification module to said interface when the second module is present in the connector (Fig. 1, a connector suitable for connecting a second subscriber identification module (~U3) to said interface (~of U1) when the second module (~U3) is present in the connector (pg. 5, par. 4, “After inserting U3”, wherein the second subscriber identification module (U3) is inserted into the connector (~socket)));
a presence detector configured to generate a presence signal of the second module in the connector (pg. 5, par. 4, when plugged in, U3 generates and sends a presence signal (~pin 5 SW (~switch) signal) to Q3, turning on Q3); and
an inhibiting circuit for inhibiting the first module according to the presence signal, the device being configured to operate with the second module when the first module is inhibited (Fig. 1, when U3 (~second subscriber identification module) is inserted, Q3 is turned on, Q2 is turned on, and Q1 is turned off, thus, U2 (~first subscriber identification module) data is disconnected (~inhibited) from U1 (~based on Q1 being off) according to the pin 5 switch signal (~presence signal); An inhibiting circuit includes both the processor U1 and the 5-pin switch-transistors-resistors connected circuitry. Therefore, when the reset from the processor U1 generating high impedance on data pin of U2 ends, the high impedance on the data pin of the U2 SIM module is continued by the 5-pin switch transistors connected circuitry. Therefore, in Fig. 1 of Kang, the device is configured to operate with the second SIM module U3 when the first module is inhibited),
wherein the inhibiting circuit is configured to inhibit a module by setting a data input/output of said module to a high impedance state, by applying a signal corresponding to an active state to an initialization signal input of the module to be inhibited (When U3 (~second SIM) is inserted, U1 (~processor) sends to U3 (~second SIM) a reset signal on RST pin to initialize the newly inserted U3 (~second SIM) and synchronize communication between the U1 (~processor) and U3 (~second SIM). This forces U3 (~second SIM) to restart, allowing it to switch to a powered-on ready to be read state; Since RST pin of U1 (~processor), U2 (~first SIM), and U3 (~second SIM) are all connected, the reset signal from U1 (~processor) also goes to RST pin of U2 (~first SIM), putting I/O data pin of U2 (~first SIM) into a high impedance state (inhibiting U2 (~first SIM) and to allow the U1 (~processor) to pull it high or low to initiate communication)).
Regarding 13, Kang teaches the device according to claim 12, including:
a data bus interconnecting a data input/output of the interface, the input/output of the first module and an input/output of the connector which functionally cooperates with a data input/output of the second module when the second module is present in the connector (Fig. 1, bus comprising DATA interconnects U1 (~comprising interface), U3, and U2);
a clock signal bus interconnecting a clock signal output of the interface, a clock signal input of the first module and an input of the connector which functionally cooperates with a clock signal input of the second module when the second module is present in the connector (Fig. 1, bus comprising CLK interconnects output of U1 (~comprising interface), input of U3 (~second module), and input of U2 (~first module)).
Regarding 14, Kang teaches the device according to claim 12,
wherein the inhibiting circuit comprises a circuit controlled by the presence signal to automatically inhibit the first module when the second module is present in the connector, the device then operating with the second module via said interface (Fig. 1, when U3 (~second module) is inserted into connector (~socket), SW (~pin 5) of U3 (~second module) sends a presence signal to Q3, turning on Q3, turning on Q2, and turning off Q1; Q1 turning off inhibits operation with U2 (~first module) and allows operation with U3 (~second module)).
Regarding 15, Kang teaches the device according to claim 14,
wherein the circuit is controlled by the presence signal to automatically disinhibit the first module when the second module is removed from the connector, the device then operating with the first module via said interface (Fig. 1, when U3 (~second module) is removed from the connector (~socket of U3), Q3 and Q2 are turned off, and Q1 is turned on, U1 (~processor) of the device then operates with U2 (~first module) via said interface of U1 (~processor)).
Regarding 16, Kang teaches the device according to claim 14,
wherein:
an initialization signal output of the interface is connected to a first input of the connector, the connector being suitable for connecting the first input to an initialization signal input of the second module when the second module is present in the connector (Fig. 1, initialization signal output of the interface (~RST (pin 17) of U1) is connected to an input of the connector (~RST (pin 2) of U3), the connector being suitable for connecting the first input to an initialization signal input of the second module (~RST (pin 2) of U3) when the second module (~U3) is present in the connector (~when U3 (~second module) is plugged into the connector (~socket)));
a resistor is connected between the initialization signal input of the second module and the initialization signal output of the interface (Fig. 1, resistor R1 is connected between the initialization signal input of the second module (~RST (pin 2) of U3) and the initialization signal output of the interface (~RST (pin 17) of U1 (~processor))),
the resistor being suitable for allowing said interface (Fig. 1, resistor R1 is connected between the initialization signal input of the second module (~RST (pin 2) of U3) and the initialization signal output of the interface (~RST (pin 17) of U1 (~processor))) to
control an initialization of the second module when it is present in the connector and the first module is inhibited (Fig. 1, resistor R1 controls an initialization (~rst (reset)) of the second module (~U3) when it (~U3) is present in the connector (~socket of U3) and the first module (~U2) is inhibited (~due to Q1 being off)); and
control an initialization of the first module when the second module is not present in the connector and the first module is not inhibited (Fig. 1, controls an initialization (~rst (reset)) of the first module (U2) when the second module is not present in the connector (~U3 not inserted into the connector (~socket)) and the first module (~U2) is not inhibited (~due to Q1 being on)).
Claim Rejections - 35 USC § 103
14. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
15. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
16. Claims 6-7 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Lagnado (US 2008/0161049 A1).
Regarding claim 6, Kang teaches the device according to claim 1,
wherein the inhibiting circuit comprises a processor being configured to selectively inhibit and disinhibit, respectively, one of the first and second modules (Kang Fig. 1, when U3 (~second module) is inserted into connector (~socket), SW (~pin 5) of U3 (~second module) sends a presence signal to Q3, turning on Q3, turning on Q2, and turning off Q1; Q1 turning off disallows (~inhibits) operation with U2 (~first module) and allows (~disinhibits) operation with U3 (~second module); processor U1 generates voltage at the emitter of Q1, affecting turn on or off of Q1 according to U3’s SW signal (~presence signal)), and
to disinhibit and inhibit, respectively, the other one of the first and second modules, when the second module is present in the connector (Kang Fig. 1, when U3 (~second module) is removed from the connector (~socket of U3), Q3 and Q2 are turned off, and Q1 is turned on, U1 (~processor) of the device then stops operating (~inhibits) with U3 (~second module) and operates (~disinhibits) with U2 (~first module) via said interface of U1 (~processor); Q1 turning off disallows (~inhibits) operation with U2 (~first module) and allows (~disinhibits) operation with U3 (~second module); processor U1 generates voltage at the emitter of Q1, affecting turn on or off of Q1 according to U3’s SW signal (~presence signal)),
the device being configured to operate with the disinhibited module (Kang Fig. 1, when U3 (~second module) is removed from the connector (~socket of U3), Q3 and Q2 are turned off, and Q1 is turned on, U1 (~processor) of the device then stops operating (~inhibits) with U3 (~second module) and operates (~disinhibits) with U2 (~first module) via said interface of U1 (~processor)).
Kang does not explicitly teach that the processor receives the presence signal.
However, Lagnado teaches a processor receiving a presence signal ([0018], “cause the processor 104 to monitor the status of a SIM card presence signal. For example, the SIM card presence signal may be asserted whenever the SIM card 152 is present in the SIM card interface 150 and de-asserted whenever the SIM card 152 is absent from the SIM card interface 150”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lagnado with the teaching of Kang in order to detect whether a SIM has been inserted, removed, or is currently present in its slot, wherein this information is critical for managing the device's cellular functions and ensuring proper network connectivity.
Regarding claim 7, Kang in view of Lagnado teaches the device according to claim 6,
wherein the processor is configured to implement (Kang Fig. 1, processor U1’s data signal generates a voltage at emitter of Q1 to turn off when SW (~pin 5) signal of U3 turns on Q3 and Q2) at least one of:
a first mode wherein the first module is automatically inhibited in the case where the second module is present in the connector and automatically disinhibited in the case where the second module is removed from the connector (Kang Fig. 1, first module (~U2) is automatically inhibited in the case where the second module (~U3) is present in the connector (~U3 socket) (~when U3 is inserted into the connector (~U3 socket), a signal from SW (pin 5 of U3) turns on Q3 and Q2, and turns off Q1 (based on voltage generated on the emitter of Q1 by data signal pin 15 via resistor R3), wherein data pin of U1 and U2 are no longer connected) and automatically disinhibited in the case where the second module is removed from the connector (~when U3 is taken off connector/socket, a signal from SW (pin 5 of U3) turns off Q3 and Q2 and turns on Q1, wherein data pin of U1 and data pin of U2 are connected)); or
a second mode wherein, when the second module is present in the connector, the first module is inhibited following receipt of a confirmation from a user and disinhibited automatically in the case where the second module is removed from the connector, or on receipt of a command from a user.
Regarding 17, Kang teaches the device according to claim 12,
wherein the inhibiting circuit comprises a processor being configured to selectively inhibit and disinhibit, respectively, one of the first and second modules (Kang Fig. 1, when U3 (~second module) is inserted into connector (~socket), SW (~pin 5) of U3 (~second module) sends a presence signal to Q3, turning on Q3, turning on Q2, and turning off Q1; Q1 turning off disallows (~inhibits) operation with U2 (~first module) and allows (~disinhibits) operation with U3 (~second module); processor U1 generates voltage at the emitter of Q1, affecting turn on or off of Q1 according to U3’s SW signal (~presence signal)), and
to disinhibit and inhibit, respectively, the other one of the first and second modules, when the second module is present in the connector (Kang Fig. 1, when U3 (~second module) is removed from the connector (~socket of U3), Q3 and Q2 are turned off, and Q1 is turned on, U1 (~processor) of the device then stops operating (~inhibits) with U3 (~second module) and operates (~disinhibits) with U2 (~first module) via said interface of U1 (~processor); Q1 turning off disallows (~inhibits) operation with U2 (~first module) and allows (~disinhibits) operation with U3 (~second module); processor U1 generates voltage at the emitter of Q1, affecting turn on or off of Q1 according to U3’s SW signal (~presence signal)),
the device being configured to operate with the disinhibited module (Kang Fig. 1, when U3 (~second module) is removed from the connector (~socket of U3), Q3 and Q2 are turned off, and Q1 is turned on, U1 (~processor) of the device then stops operating (~inhibits) with U3 (~second module) and operates (~disinhibits) with U2 (~first module) via said interface of U1 (~processor)).
Kang does not explicitly teach that the processor receives the presence signal.
However, Lagnado teaches a processor receiving a presence signal ([0018], “cause the processor 104 to monitor the status of a SIM card presence signal. For example, the SIM card presence signal may be asserted whenever the SIM card 152 is present in the SIM card interface 150 and de-asserted whenever the SIM card 152 is absent from the SIM card interface 150”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lagnado with the teaching of Kang in order to detect whether a SIM has been inserted, removed, or is currently present in its slot, wherein this information is critical for managing the device's cellular functions and ensuring proper network connectivity.
Regarding 18, Kang in view of Lagnado teaches the device according to claim 17,
wherein the processor is configured to implement (Kang Fig. 1, processor U1’s data signal generates a voltage at emitter of Q1 to turn off when SW (~pin 5) signal of U3 turns on Q3 and Q2) at least one of:
a first mode wherein the first module is automatically inhibited in the case where the second module is present in the connector and automatically disinhibited in the case where the second module is removed from the connector (Kang Fig. 1, first module (~U2) is automatically inhibited in the case where the second module (~U3) is present in the connector (~U3 socket) (~when U3 is inserted into the connector (~U3 socket), a signal from SW (pin 5 of U3) turns on Q3 and Q2, and turns off Q1 (based on voltage generated on the emitter of Q1 by data signal pin 15 via resistor R3), wherein data pin of U1 and U2 are no longer connected) and automatically disinhibited in the case where the second module is removed from the connector (~when U3 is taken off connector/socket, a signal from SW (pin 5 of U3) turns off Q3 and Q2 and turns on Q1, wherein data pin of U1 and data pin of U2 are connected));
a second mode wherein, when the second module is present in the connector, the first module is inhibited following receipt of a confirmation from a user and disinhibited automatically in the case where the second module is removed from the connector, or on receipt of a command from a user.
Conclusion
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/ALEXANDER YI/
Examiner, Art Unit 2643
/JINSONG HU/ Supervisory Patent Examiner, Art Unit 2643