DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
This application claims priority to provisional U.S. Application No. 63/496,094 filed 04/14/2023.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the ground layer is between the at least one anode layer and the cathode electrode, and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer, and a second isolation layer between the ground layer and the cathode electrode” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4, 5, 7-9, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (US20220285909A1), hereafter Kimura, in view of Hegblom et al. (US20200321754A1), hereafter Hegblom.
Regarding claim 1, Kimura discloses an emitter assembly (Fig. 20), comprising: a carrier comprising a ground plane (Fig. 20 element 100, 108, line running from 108 to 201); a decoupling capacitor electrically connected to the ground plane (Fig. 20 element 109); and a vertical cavity surface emitting laser (VCSEL) device on the carrier (Fig. 20 element 300) and electrically connected to the ground plane (Fig. 20 element 300 is connected to the line by elements 101 and 201) and the decoupling capacitor (Fig. 20 element 300 is connected to element 109 by element 107), the VCSEL device comprising: a substrate (Fig. 20 element 310); a plurality of VCSELs on the substrate (Fig. 20 elements 341); at least one anode layer on the substrate and electrically connected to the plurality of VCSELs (Fig. 20 element 330; [0056]); one or more first interconnects that electrically connect the at least one anode layer and the carrier (Fig. 20 elements 107); a cathode electrode over at least a portion of one or more VCSELs, of the plurality of VCSELs, and electrically connected to the one or more VCSELs ([0057]); one or more second interconnects that electrically connect the cathode electrode and the carrier (Fig. 20 elements 101 and 106; [0057]). Kimura does not explicitly disclose a ground layer electrically connected to the ground plane and electrically isolated from the at least one anode layer and the cathode electrode by one or more isolation layers; and one or more third interconnects that electrically connect the ground layer and the carrier. However, Hegblom discloses a ground layer electrically connected to the ground plane (Fig. 26 element 122-3; [0112]) and electrically isolated from the at least one anode layer and the cathode electrode by one or more isolation layers (Fig. 26 element 122-3 is over element 124-3; [0112]); and one or more third interconnects that electrically connect the ground layer and the carrier ([0112]). An advantage is to reduce inductance when driving the array with shorter pulses ([0112]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kimura with a ground layer electrically connected to the ground plane and electrically isolated from the at least one anode layer and the cathode electrode by one or more isolation layers; and one or more third interconnects that electrically connect the ground layer and the carrier as disclosed by Hegblom in order to reduce inductance when driving the array with shorter pulses.
Regarding claim 2, Kimura in view of Hegblom do not explicitly disclose in the same embodiments the ground layer includes one or more openings and the one or more second interconnects extend respectively through the one or more openings. However, in a different embodiment Hegblom discloses forming openings in insulation and metal layers with interconnects extending therethrough ([0090]; See also Fig. 32.5 showing a hole in 122-3 and 124-3 over C1-C4). An advantage is to allow electrical connection to the cathode while flip chip bonding the VCSEL array ([0090]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to further modify Kimura in view of Hegblom with the ground layer includes one or more openings and the one or more second interconnects extend respectively through the one or more openings as suggested by Hegblom in order to allow electrical connection to the cathode while flip chip bonding the VCSEL array.
Regarding claim 4, Kimura further discloses the carrier comprises an integrated circuit chip ([0051]).
Regarding claim 5, Hegblom further discloses the ground layer is on the at least one anode layer and the cathode electrode (Fig. 26 element 122-3 is on elements A3, A4, C1, and C2), and wherein the one or more isolation layers include an isolation layer between: the ground layer, and the at least one anode layer and the cathode electrode (Fig. 26 element 124-3 is between element 122-3 and elements A3, A4, C1, and C2).
Regarding claim 7, Hegblom further discloses the ground layer is underneath the at least one anode layer, and wherein the one or more isolation layers include an isolation layer between the ground layer and the at least one anode layer (Fig. 26 element 122-3 is over element 124-3 in the figure but discusses flip chip bonding at [0099] which would result in layer 122-3 being under the anode while still being separated from the anode by 124-3).
Regarding claim 8, Kimura further discloses a conductive semiconductor layer on the substrate, wherein the plurality of VCSELs are on the conductive semiconductor layer (Fig. 20 element 320), and wherein the at least one anode layer is on the conductive semiconductor layer and electrically connected to the plurality of VCSELs via the conductive semiconductor layer (Fig. 20 element 330).
Regarding claim 9, Kimura further discloses the VCSEL device is in a flip chip configuration on the carrier (Fig. 20).
Regarding claim 17, Kimura discloses a vertical cavity surface emitting laser (VCSEL) device (Fig. 20), comprising: a substrate (Fig. 20 element 310); a plurality of VCSELs on the substrate (Fig. 20 elements 341); an anode layer on the substrate and electrically connected to the plurality of VCSELs (Fig. 20 element 320); a cathode electrode over at least a portion of one or more VCSELs, of the plurality of VCSELs, and electrically connected to the one or more VCSELs ([0057]). Kimura does not explicitly disclose a ground layer electrically isolated from the anode layer and the cathode electrode by one or more isolation layers, wherein the ground layer is on the anode layer and the cathode electrode, between the anode layer and the cathode electrode, or underneath the anode layer. However, Hegblom discloses a ground layer electrically isolated from the anode layer and the cathode electrode by one or more isolation layers (Fig. 26 element 124-3 is between element 122-3 and elements A3, A4, C1, and C2; [0112]), wherein the ground layer is on the anode layer and the cathode electrode, between the anode layer and the cathode electrode, or underneath the anode layer (Fig. 26 element 124-3 is between element 122-3 and elements A3, A4, C1, and C2; [0112]). An advantage is to reduce inductance when driving the array with shorter pulses ([0112]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kimura with a ground layer electrically isolated from the anode layer and the cathode electrode by one or more isolation layers, wherein the ground layer is on the anode layer and the cathode electrode, between the anode layer and the cathode electrode, or underneath the anode layer as disclosed by Hegbl1om in order to reduce inductance when driving the array with shorter pulses.
Regarding claim 19, Hegblom further discloses the anode layer is electrically connected to a respective bottom mirror of each of the plurality of VCSELs and the cathode electrode is electrically connected to a respective top mirror of each of the one or more VCSELs (Fig. 26 elements A3, C1, and A4 are electrically connected to elements 110 and 108 because current flows through elements 108 and 110; [0028])
Regarding claim 20, Kimura further discloses the cathode electrode is one of a plurality of cathode electrodes ([0057]).
Claims 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Hegblom, as applied to claims 1and 17 above, in further view of Takimoto et al. (US20210028158A1), hereafter Takimoto.
Regarding claims 3 and 18, Hegblom further discloses that inductance may be reduced by providing additional contacts to the ground plane ([0112]). Kimura in view of Hegblom do not explicitly disclose a current flow path through the at least one anode layer is in a first direction and a current looping path through the ground layer is in a second direction opposite the first direction. However, Takimoto discloses additional current loops that have currents flowing in opposite directions as the current flowing through the anode (Fig. 17). An advantage is that inductance may be reduced providing currents flowing in opposite directions ([0048]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kimura in view of Hegblom with a current flow path through the at least one anode layer is in a first direction and a current looping path through the ground layer is in a second direction opposite the first direction, since Takimoto discloses current loops with currents flowing in opposite directions as the current flowing through the anode in order to reduce inductance.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Hegblom, as applied to claim 1 above, in further view of Hegblom (US20190109436A1), hereafter Hegblom 436.
Regarding claim 6, Hegblom further discloses that the layers shown in Fig. 32.5 may have different arrangements ([0113]). Kimura in view of Hegblom do not explicitly disclose the ground layer is between the at least one anode layer and the cathode electrode, and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer, and a second isolation layer between the ground layer and the cathode electrode. However, Hegblom 436 discloses that a metal layer may be formed between at least one anode layer and the cathode electrode (Fig. 2G element 222-2b is formed between 222-3 and 203) and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer (Fig. 2G 224 above 222-2b), and a second isolation layer between the ground layer and the cathode electrode (Fig. 2G 224 below 222-2b). An advantage is to optimize the location of the ground layer based on its desired electrical and optical properties. Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kimura in view of Hegblom with the ground layer is between the at least one anode layer and the cathode electrode, and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer, and a second isolation layer between the ground layer and the cathode electrode, since Hegblom 436 discloses that metal layers may metal layer may be formed between at least one anode layer and the cathode electrode and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer, and a second isolation layer between the ground layer and the cathode electrode, Hegblom suggests the location of the layers may be optimized and it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claims 10-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Hegblom in further view of Takimoto.
Regarding claim 10, Kimura discloses an emitter assembly (Fig. 20), comprising: a carrier comprising a ground plane (Fig. 20 element 100, 108, line running from 108 to 201); a decoupling capacitor electrically connected to the ground plane (Fig. 20 element 109); and a vertical cavity surface emitting laser (VCSEL) device on the carrier (Fig. 20 element 300) and electrically connected to the ground plane (Fig. 20 element 300 is connected to the line by elements 101 and 201) and the decoupling capacitor (Fig. 20 element 300 is connected to element 109 by element 107), the VCSEL device comprising: a substrate (Fig. 20 element 310); a plurality of VCSELs on the substrate (Fig. 20 elements 341); at least one anode layer on the substrate and electrically connected to the plurality of VCSELs (Fig. 20 element 330; [0056]), wherein current to be discharged from the decoupling capacitor is to flow through the anode layer in a first direction ([0134]); wherein current is to flow from the anode layer through the one or more VCSELs to the cathode electrode ([0057]), and from the cathode electrode to the carrier (Fig. 20 and Fig. 21). Kimura does not explicitly disclose a ground layer electrically isolated from the anode layer and the cathode electrode by one or more isolation layers, wherein current returning from the carrier is to flow through the ground layer in a second direction opposite the first direction. However, Hegblom discloses a ground layer isolated from the at least one anode layer and the cathode electrode by one or more isolation layers (Fig. 26 element 122-3 is over element 124-3; [0112]); and one or more third interconnects that electrically connect the ground layer and the carrier ([0112]). An advantage is to reduce inductance when driving the array with shorter pulses ([0112]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kimura with a ground layer electrically isolated from the anode layer and the cathode electrode by one or more isolation layers as disclosed by Hegblom in order to reduce inductance when driving the array with shorter pulses. Kimura in view of Hegblom do not explicitly disclose current returning from the carrier is to flow through the ground layer in a second direction opposite the first direction. However, Takimoto discloses additional current loops that have currents flowing in opposite directions as the current flowing through the anode (Fig. 17). An advantage is that inductance may be reduced providing currents flowing in opposite directions ([0048]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kimura in view of Hegblom with current returning from the carrier is to flow through the ground layer in a second direction opposite the first direction, since Takimoto discloses current loops with currents flowing in opposite directions as the current flowing through the anode in order to reduce inductance.
Regarding claim 11, Takimoto further discloses current to flow through the ground layer in the second direction is to provide mutual inductance cancellation with current to flow through the anode layer in the first direction ([0049]).
Regarding claim 12, Hegblom further discloses the ground layer is on the at least one anode layer and the cathode electrode (Fig. 26 element 122-3 is on elements A3, A4, C1, and C2), and wherein the one or more isolation layers include an isolation layer between: the ground layer, and the at least one anode layer and the cathode electrode (Fig. 26 element 124-3 is between element 122-3 and elements A3, A4, C1, and C2).
Regarding claim 14, Hegblom further discloses the ground layer is underneath the at least one anode layer, and wherein the one or more isolation layers include an isolation layer between the ground layer and the at least one anode layer (Fig. 26 element 122-3 is over element 124-3 in the figure but discusses flip chip bonding at [0099] which would result in layer 122-3 being under the anode while still being separated from the anode by 124-3).
Regarding claim 15, Kimura further discloses the anode layer is electrically connected to the decoupling capacitor, and wherein the ground layer is electrically connected to the decoupling capacitor. (Fig. 20 element 109; [0132]).
Regarding claim 16, Kimura further discloses the plurality of VCSELs are in a bottom-emitting configuration (Fig. 20 element 300; [0056]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Hegblom in further view of Takimoto, as applied to claim 10 above, in further view of Hegblom 436.
Regarding claim 13, Hegblom further discloses that the layers shown in Fig. 32.5 may have different arrangements ([0113]). Kimura in view of Hegblom in further view of Takimoto do not explicitly disclose the ground layer is between the at least one anode layer and the cathode electrode, and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer, and a second isolation layer between the ground layer and the cathode electrode. However, Hegblom 436 discloses that a metal layer may be formed between at least one anode layer and the cathode electrode (Fig. 2G element 222-2b is formed between 222-3 and 203) and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer (Fig. 2G 224 above 222-2b), and a second isolation layer between the ground layer and the cathode electrode (Fig. 2G 224 below 222-2b). An advantage is to optimize the location of the ground layer based on its desired electrical and optical properties. Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kimura in view of Hegblom with the ground layer is between the at least one anode layer and the cathode electrode, and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer, and a second isolation layer between the ground layer and the cathode electrode, since Hegblom 436 discloses that metal layers may metal layer may be formed between at least one anode layer and the cathode electrode and wherein the one or more isolation layers include a first isolation layer between the at least one anode layer and the ground layer, and a second isolation layer between the ground layer and the cathode electrode, Hegblom suggests the location of the layers may be optimized and it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attached Notice of References Cited. See, e.g., WO202209376A1 Fig. 27; WO2022097390A1; WO2022109436A1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA KING whose telephone number is (571)270-1441. The examiner can normally be reached Monday to Friday 10am-5pm MT.
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/Joshua King/Primary Examiner, Art Unit 2828 05/07/2026
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