DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/14/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 recites “the second clock.” There is insufficient antecedent basis for this limitation in the claim.
Claim 5 depends from claim 4, and thus is rejected for same reasons.
Claims 6, 8 recite “the second clock,” and thus are rejected for the same reasons as in claim 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-9, 11-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Phadke et al., US 2024/0396551 A1, in view of Lachwani et al., US 8,612,786 B1, and further in view of Kuo et al., US 2007/0174649.
Regarding claim 1, Phadke discloses a method for saving power, used in a system power management interface (SPMI) slave device [par 44, a method for saving power used in SoC 302 (the PMIC 306 can control the power mode for the SoC, making the SoC function as a slave device that receives commands and responds accordingly”, see also par 43], comprising:
receiving a first switch request … from a system clock to an SPMI clock when the SPMI slave device enters sleep mode [Fig. 3, par 43, 47, the SoC 302 (slave device) receive a first switch request (DS_EN signal 322 triggers the deep sleep mode for the SoC) indicating to switch the clock signal from a first clock signal to a second clock signal when the slave device enters sleep mode (par 57, the SoC may cause a deep sleep clock signal to be provided to support certain functions and circuits during the deep sleep state, switching from a normal operations clock signal to a deep sleep clock signal)];
transmitting a system clock source signal indicating to switch the clock source from the system clock to the SPMI clock to SPMI-accessible registers [par 57, once the SoC receives the DS_EN signal from the PMIC, the SoC can transmit a first signal (DS_EN pre signal 512) indicating to switch from the first clock signal to the second clock signal to registers (the SoC configures a register, causing the DS_EN pre signal, which then provides a deep sleep clock signal so that the SoC can switch from a normal operations clock signal to a deep sleep clock signal)]; and
Phadke discloses switching clock signals when transitioning between power states, but does not explicitly disclose dynamically switching the claimed register domain from a normal system clock to a second clock before disabling the normal clock system clock. However, Lachwani teaches such a clock transition. Specifically, Lachwani Fig. 10 teaches at steps 1008 and 1010 switching components from root clock 302 to external clock 206, propagating the updated clock values at step 1012, and thereafter gating root clock 302 at step 1014, while the designated components continue to receive clocking from external clock 206.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to employ Lachwani’s known clock-switching technique in Phadke’s low-power SPMI system to permit selected SPIM-related circuitry to remain operation from a lower-power/alternate clock while the principal system clock is disabled, thereby reducing power consumption while retaining required low-power functionality.
Phadke and Lachwani do not expressly disclose that the clock-source switching is performed only when the SPMI bus is idle. However, Kuo teaches precisely the reason for performing a clock-source transition while the associated bus is inactive. Kuo par. 16 teaches a sleep condition in which the bus ceases operation; par. 18 teaches performing the clock switching while the bus has ceased operating so that the switching does not affect normal bus operation; and par. [0022] expressly performs the first-to-second-clock transition when the bus in a state of stopping transmission.
It would therefore have been obvious to one of ordinary skill in the art, before the effective filing date, to perform the clock-source switching of the Phadke/Lachwani system only while the SPMI bus is idle, as taught by Kuo, to avoid changing the clock source during an active bus transaction and thereby prevent disruption or corruption of the bus communications.
Regarding claim 2, Phadke/Lachwani/Kuo disclose the method as claimed in claim 1. Phadke further discloses the method further comprising:
transmitting the a system clock source signal to the registers in response to the SPMI bus being idle [par 58, the glitch filter transmits DS_EN_Sample signal 514 (par 57, which causes the SoC to configure a register that causes the deep sleep preset signal) in response to the SPMI bus being idle (par 58, the PMIC stops sending signals via the SPMI bus for a threshold number of clock cycles). Furthermore, Kuo par. 16 teaches control unit 16 receiving a first control signal that drives the CPU into a sleep state in which the front-side bus ceases to operate, and outputting the switch triggering signal. Par. 18 states that the switching is carried out when the bus has ceased operation so normal bus operation is unaffected, and par. 22 expressly transmits the switch triggering signal and performs the clock switch while the bus is in the state of stopping transmission].
Regarding claim 3, Phadke/Lachwani/Kuo disclose the method as claimed in claim 2. Phadke further discloses the method further comprising:
postponing transmitting the system clock source signal to the registers until the SPMI bus is idle in response to the SPMI bus not being idle [par 58, the glitch filter postpones the transmission of DS_EN_Sample signal 514 (sent when the SPMI bus is idle) in response to the SPMI bus not being idle (the SPMI bus must be idle for a certain number of clock cycles, meaning the DS_EN signal stays asserted with no other signals from the PMIC). If there are glitches (activity on the SPMI bus) the DS_EN_Sample signal will be delayed or postponed, see also par 68. Furthermore, Kuo par. 24 teaches that after a new clock adjustment is requested, output switch unit 18 continues transmitting the existing clock until the CPU enters the sleep state, in which the front-side bus ceases operation, and only then performs the clock change].
Regarding claim 4, Phadke/Lachwani/Kuo disclose the method as claimed in claim 1. Phadke further discloses the method further comprising:
receiving a second switch request indicating to switch the clock signal from the second clock signal to the system clock signal when the slave device enters wake-up mode [par 47, the SoC 302 can receive a second switch request (reset signal 324) from the PMIC indicating to switch the clock signal from the second clock signal to the first clock signal when the slave device (SoC 302) enters wake-up mode (exits deep sleep mode). See also par 77, when SoC exits deep sleep and enters a normal functioning state, the SoC will no longer use the deep sleep clock signal, as it’s only used during deep sleep mode, and will switch to a normal clock signal]; and
transmitting a second clock source signal indicating to switch the clock signal from the second clock signal to the system clock signal to the registers [par 47, in response to the reset signal from the PMIC, the SoC will transmit reset signals internally (including registers) indicating to switch the clock signal from the second clock signal to the first clock signal to the registers (par 77, exiting deep sleep state and entering a normal functioning state will remove the need for the deep sleep clock signal, making the SoC switch from the deep sleep clock signal to a normal clock signal)]. Lachwani further teaches switching a clock source from the second clock to the first clock [Col 8, ll. 31-35, the clock source for device 100 may be switched from the second clock (external clock, used for the idle (sleep) mode) to the first clock (root clock, used for normal operation), see also Fig. 7].
Regarding claim 5, Phadke and Lachwani disclose the method as claimed in claim 4. Phadke further discloses the method further comprising:
switching the clock signal from the second clock signal to the system clock signal to the registers according to the second clock source signal [par 47 and par 77, the clock signal is switched from the second clock signal (deep sleep clock signal) to the first clock signal (normal clock signal) to the registers according to the second signal (the SoC transmits reset signals internally, including the registers, after receiving the reset signal from the PMIC, and switches to a normal functioning state)]. Lachwani further discloses switching a clock source from the second clock to the first clock [Col 8, ll. 31-35, the clock source for device 100 may be switched from the second clock (external clock, used for the idle (sleep) mode) to the first clock (root clock, used for normal operation), see also Fig. 7].
Regarding claim 6, Phadke and Lachwani disclose the method as claimed in claim 1. Lachwani further teaches wherein the slave device is clocked by the second clock when the slave device is in the sleep mode [col 2, last par, the slave device (device 100) is clocked by the second clock (external clock) when the slave device is in the sleep mode (deep idle mode)].
Regarding claim 8, Phadke and Lachwani disclose the method as claimed in claim 1. Phadke further discloses the method further comprising:
allowing an external device to access the registers via a SPMI bus [par 43 and Fig. 3, allowing an external device (PMIC) to access the registers (within SoC) via a SPMI bus 310], wherein the registers are clocked by the second clock signal when the SPMI slave device is in the sleep mode [par 57, the registers are configured to cause a deep sleep preset signal. The SoC, including its internal registers are then clocked by the second clock signal (deep sleep clock signal) when the slave device (SoC) is in the deep sleep state]. Lachwani further teaches a second clock [col 2, last par, the slave device (device 100) is clocked by the second clock (external clock) when the slave device is in the sleep mode (deep idle mode)].
Regarding claim 9, Phadke and Lachwani disclose the method as claimed in claim 7. Phadke further discloses wherein the external device is a SPMI master device [Fig. 3 shows that the PMIC (master device) is a SPMI master device. Par 44, the PMIC 306 can control the power mode for the SoC, making the PMIC function as a master device that sends commands to the SoC].
Regarding claim 11, Phadke discloses a device for saving power [par 47, SoC 32 can manage power modes within itself], comprising:
a processor [Fig. 2, processor 212];
registers [Fig. 2, registers 206]; and
a dynamic clock source controller coupled to the processor and the registers [Fig. 2, processor and/or control logic 212, is also coupled to the registers].
The remainder of claim 11 recites the same limitations and features of claim 1, reciting no further limiting features or structure, and is rejected accordingly.
Regarding claims 12-16 and 18, these claims recite the same limitations and features of claims 2-8 and 10, respectively, reciting no further limiting features or structure, and are rejected accordingly.
Regarding claim 20, Lachwani discloses non-transitory computer-readable storage medium containing instructions [par 9, non-transitory computer-readable storage medium (processor-readable storage medium) containing instructions] that, when executed by a subsystem in a system power management interface (SPMI) slave device [processing circuit within SoC], cause the slave device to perform a method for saving power [cause the SoC to control and manage signals that indicate the power state]. Phadke further discloses the method comprising:
detecting whether a SPMI bus is idle [par 51 and 58, glitch filtering circuit 400 implemented in the SoC detects whether the SPMI bus 310 is idle (no signal transmission from the PMIC) by counting clock cycles to determine if a DS_EN signal is stable and valid]; and a system power management interface (SPMI) clock (SCLK) [Fig. 2 and Fig. 3, clock gen. 208 (within SPMI slave device SoC 302). Par 27, a PMIC may be configured by the SoC or host or by another managing PMIC using SPMI protocols].
The remainder of claim 20 recites the same limitations and features of claim 1, reciting no further limiting features or structure, and is rejected accordingly.
As per claim 21, Phadke teaches that the bus master device 202 generates clock signal 228 for transmission on clock line 218, par. 38. In par. 39, it teaches that the slave’s clock signal 248 may be derived from the signal received on clock line 218; and par. 40 expressly states that serial bus 220 may be operated according to SPMI. Thus, Phadke directly teaches an SPMI clock supplied to slave device by the external bus master.
Response to Arguments
Applicants’ arguments filed 05/14/2026 have been fully considered but they are not persuasive. Applicant argues that Phadke and Lachwani fail to teach or suggest that (1) the system clock is disabled during sleep, (2) SPMI-accessible registers remain accessible through the SPMI bus while being clocked by SCLK, and (3) switching from the system clock SCLK is performed only when the SPMI bus is idle. The arguments have been considered but are not persuasive with respect to the presently applied combination.
Phadke teaches an SPMI master/slave environment including slave configuration registers and a bus-master-provided serial-bus clock. Phadke further teaches maintaining selected communication-interface circuitry in an always-on state during deep sleep. Lachwani teaches switching designated circuitry from a normal/root clock to an external clock and thereafter gating the root clock while the designated circuitry continues receiving the external clock. Thus, Lachwani is relied upon for the clock-source switching and system-clock-gating teaches, while Phadke supplies the SPMI environment; Applicant’s argument that Lachwani itself does not disclose SPMI therefore does not address the combined teaches of the references.
Applicant additionally argues that Phadke’s glitch filtering does not teach performing the clock-source switching only when the SPMI bus is idle. This argument is moot in view of the newly cited Kuo.
Accordingly, Applicant’s arguments do not overcome the rejection of the independent claims or the claims dependent therefrom.
Conclusion
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/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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