Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-12, 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zetterman (US 20130339648 A1) in view of Hartog (US 20130155077 A1).
Regarding claim 1, Zetterman teaches:
A system comprising: (Claim 14. An apparatus, comprising: at least one processor; at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to: )
a scheduling circuit; and direct memory access circuitry configured to, responsive to generation of a preemption request by the scheduling circuit: ([0160] FIG. 1 illustrates an example embodiment of the invention that enables preemptive task context switching to be performed on a processor with one or more custom functional processors. The figure illustrates a system architecture of a processor comprising a plurality of components, referred to herein as the processor core 100. The processor core 100 maybe implemented as transport triggered architecture (TTA) processor 102 The transport triggered architecture processor 102 comprises one or more custom functional units FU1 and FU2 that may be parts of an application-specific instruction-set processor (ASIP). The transport triggered architecture processor 102 includes a global control unit (GCU) 108 that controls a direct memory access (DMA) memory controller 110. See also [0191-0194] and [0204-0206] E.N: the “preemptive task switch command” is the claimed preemption request. It is generated and sent by GCU 108 and the DMA performs its operations in response to receiving it)
save a first plurality of registers associated with a first task at a memory location transmitted by the scheduling circuit, without participation by the scheduling circuit; ([0160]The DMA memory controller 110 stores the first processing states S1 and S2 of a currently running first task T1 in the first process control block PCB1. The DMA controller 110 accesses from the second process control block PCB2, second processing states S1' and S2' of a second task T2 to be performed by the custom functional units FU1 and FU2, which the DMA memory controller 110 preemptively loads in the respective custom functional units FU1 and FU2. Preemptive task context switching of the processor, including custom functional units FU1 and FU2 is thereby enabled for real time multitasking, in accordance with an example embodiment of the invention. See also [0187] and [0207] E.N.: GCU 108 corresponds to the claimed scheduling circuit because it controls task execution and transmits the preemptive task switch command and PCB address to DMA controller 110. After initiation, DMA controller independently performs the register transfer without further participation by GCU 108.)
Zetterman does not appear to explicitly teach: and queue a second task for execution.
However, Hartog teaches: [0084] Each hardware queue descriptor HQD includes an associated queue of eight memory queues. As shown in FIG. 4, for example, CS P0 is associated with queues Q0-Q7. Similarly, CS P1 is associated with queue Q8-Q15, and so on through CS Pipe 7 queues Q56-Q63. A CP multithreaded microprocessor engine ME 301 and grid DCs Cntr0-Cntr3 are provided to process thread groups. See also [0091-0108]
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Zetterman and Hartog before them, to include Hartog’s queue descriptor and memory queue arrangement in Zetterman’s preemptive context switch system. One would have been motivated to make such a combination to improve processor utilization and context switch efficiency while predictably allowing Zetterman’s system to preserve task state while Hartog’s queue system select the next task.
Regarding claim 2, Zetterman teaches:
The system as claimed in claim 1, wherein the memory location is transmitted by the scheduling circuit as part of the preemption request. ([0192] [1] send preemptive task switch command to DMA memory controller 110 for PCB1 & PCB 2; [0195] Context switch information I1 in step [1] identifying PCB1 and PCB 2, task1 and task 2, is sent to the DMA memory controller over connection D. Context switch commands in steps [2] and [3] are sent to transport triggered architecture processor 102 components over the bus 14. E.N: the PCB 1 address is included in the transmitted preemption/context switch information, the memory location is transmitted as part of the request.)
Regarding claim 3, Hartog teaches:
The system as claimed in claim 2, wherein the memory location is transmitted by the scheduling circuit as a memory queue descriptor (MQD) address pointer. ([0089] Each of the hardware queue descriptors HQD0-HQD7 can include a memory queue descriptor address MQDA of the OS allotted memory queue descriptor MQD. The OS can use the MQD to store the permanent status of the queue and provide the MQDA address to the HQD so the hardware can update to select fields of the memory queue descriptor. When the memory queue descriptor is disconnected from a HQD, the hardware will use a portion of the MQD to store necessary persistent data temporarily during any pre-emption. A subset of the space can also be used for synchronization coordination between the OS and the HQD.; see also [0085])
Regarding claim 4, Zetterman teaches:
The system as claimed in claim 1, wherein the first plurality of registers at least comprises a dequeue request register, and wherein responsive to the preemption request, the direct memory access circuitry is further configured to: clear the dequeue request register; and transmit an interrupt signal to the scheduling circuit. ([0248] In the flow chart 700 of FIG. 7, the MA memory controller 110 may carry out the following steps in detecting that functional unit has triggered a new instruction when its state is possibly invalid See [0249-0256]. [0263] In an example embodiment of the invention, Table 2 illustrates how the lazy on-demand state storing concept works in practice. Table 2 shows the state of tasks' FU storage in PCB, DMA bookkeeping (FU Context table), and the "context switched" and "busy" state flags/wires after the events in example have processed. In the example shown in Table 2, three tasks use the custom FUs and they executed concurrently using preemptive multitasking. The "start_use" wire is not shown because it is always de-asserted after each event. When processing the event, "start use" is temporarily asserted according to the flowchart 6 to control the behavior of DMA unit flowchart of FIG. 7. The execution is started at the initial state shown in Table 2 at the beginning The following events take place: See [0264-0274]. E.N: The flag stores the task/context switch status that the DMA checks and then clears after handling the context operation)
Regarding claim 5, Zetterman teaches:
The system as claimed in claim 4, wherein the scheduling circuit is configured to map a second plurality of registers associated with the second task to the direct memory access circuitry, in response to receiving the interrupt signal. ([0207] Context switch command in step [1] identifying T1, T2, PCB1 and PCB2, is received from GCU 108 over connection D. In accordance with an example embodiment of the invention, if an address translation technique is used, the PCB1 and PCB2 addresses may be generated from a task ID. The processing state S1 received from FU1 over connection B1 may include, for example, the state of the pipeline register (if pipelined computation is used), the state of any intermediate results (if hardware looping is used), or the state of some internal registers that may hold their values between the execution of separate instructions. Similarly, the processing state S2 from FU2 is received over connection B2. The current processing states S1 and S2 are transmitted to the memory 184 over the connection C and stored at the address of PCB1 in step [2]. The new processing states S1' and S2' may be accessed over the same connection C from the memory 184 at the address of PCB2 and loaded in FU1 and FU2 in step [3]. See also [0212])
Regarding claim 7, Hartog teaches:
The system as claimed in claim 1, wherein the first task is associated with an application, and wherein the system further comprises a kernel driver configured to map one or more command queues, associated with the first task, to the scheduling circuit. ([0085] As discussed above, hardware scheduler HWS 128 is configured to select a scheduled process from RLC 150 for execution on the APD. For example, HWS 128 supports scheduling techniques applied to RLC 150, based upon priority level, or based on other arbitration scheduling criteria. Additionally, KMD 110, together with SWS 112, can perform scheduling of processes to be executed on the APD. The OS SWS 112, for example, can include logic to maintain a prioritized list of processes to be executed on APD 200 as a result of arbitration. See also [0069-0070]. E.N: kernel mode driver (KMD) queues application commands into process command buffer.)
Regarding claim 8, it is a method claim having similar limitations cited in claim 1. Thus, claim 8 is also rejected under the same rationales as cited in the rejection of claim 1.
Regarding claim 14, it is a system claim having similar limitations cited in claim 1. Thus, claim 14 is also rejected under the same rationales as cited in the rejection of claim 1.
Regarding claim 9, it is a method claim having similar limitations cited in claim 2. Thus, claim 9 is also rejected under the same rationales as cited in the rejection of claim 2.
Regarding claim 15, it is a system claim having similar limitations cited in claim 2. Thus, claim 15 is also rejected under the same rationales as cited in the rejection of claim 2.
Regarding claim 10, it is a method claim having similar limitations cited in claim 3. Thus, claim 10 is also rejected under the same rationales as cited in the rejection of claim 3.
Regarding claim 16, it is a system claim having similar limitations cited in claim 3. Thus, claim 16 is also rejected under the same rationales as cited in the rejection of claim 3.
Regarding claim 11, it is a system claim having similar limitations cited in claim 4. Thus, claim 11 is also rejected under the same rationales as cited in the rejection of claim 4.
Regarding claim 17, it is a system claim having similar limitations cited in claim 4. Thus, claim 17 is also rejected under the same rationales as cited in the rejection of claim 4.
Regarding claim 12, it is a system claim having similar limitations cited in claim 5. Thus, claim 12 is also rejected under the same rationales as cited in the rejection of claim 5.
Regarding claim 18, it is a system claim having similar limitations cited in claim 5. Thus, claim 18 is also rejected under the same rationales as cited in the rejection of claim 5.
Regarding claim 20, it is a system claim having similar limitations cited in claim 7. Thus, claim 20 is also rejected under the same rationales as cited in the rejection of claim 7.
Claims 6, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zetterman (US 20130339648 A1) in view of Hartog (US 20130155077 A1) and further view of Nalluri (US 20150002522 A1).
Regarding claim 6, Zetterman and Hartog does not appear to explicitly teach:
The system as claimed in claim 1, wherein the first plurality of registers comprises one or more of a ring buffer write pointer register, a ring buffer read pointer register, a ring buffer control register, a ring buffer base address, and a doorbell register.
However, Nalluri teaches: [0027] FIG. 3 is a process flow diagram of batch buffer execution and preemption using a ring buffer. At 302 a start command is executed by the GPU and the GPU first determines whether there are any commands in the ring buffer. At 304, the GPU determines whether the head offset is equal to the tail offset. If so, then the ring buffer is empty and the process stops 320. It begins again with another start command 302. If the tail offset is distanced from the head offset, then there are instructions to execute at addresses between the head offset pointer and the tail offset pointer. At 306 the GPU starts to execute those instructions. See [0030], [0040], [0076]
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Zetterman and Hartog before them, to include Nalluri’s ring buffer head-read pointer register . Doing so would preserve the task command fetch position and permit the preempted task to resume without restarting or reexecuting previously completed commands as taught by Nalluri [0028][0051].
Regarding claim 13, it is a method claim having similar limitations cited in claim 6. Thus, claim 13 is also rejected under the same rationales as cited in the rejection of claim 6.
Regarding claim 19, it is a system claim having similar limitations cited in claim 6. Thus, claim 19 is also rejected under the same rationales as cited in the rejection of claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Otsuka (US 20230090585 A1) – Relates to urgency based preemption, context saving and scheduling a second process for execution on accelerated processing device.
Metz (US 20140022266 A1) – Relates to GPU state saving and GPU context switch
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/C.A.E./Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199
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