DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (Kim, KR 20010039220 A).
Regarding Claim 1, Kim teaches:
A sensor emulation system, comprising: a first memory device (Kim, Figure 1)
configured to receive a signal at an input of the first memory device (Kim, Figure 1)
and provide a first voltage output to a first voltage controlled current source (Kim, Figure 1)
a second memory device (Kim, Figure 1)
configured to receive an inverse of the signal at an input of the second memory device (Kim, Figure 1)
and provide a second voltage output to a second voltage controlled current source. (Kim, Figure 1)
Regarding Claim 2, Kim teaches:
The sensor emulation system of claim 1 (Kim, Figure 1)
where the first memory device and the second memory device are D flip-flops (Kim, Figure 1)
where the input of the first memory device is a clock input, (Kim, Figure 1)
and where the input to the second memory device is a clock input. (Kim, Figure 1)
Regarding Claim 3, Kim teaches:
The sensor emulation system of claim 1 (Kim, Figure 1)
where the first memory device includes a first D input and a first Q- output. (Kim, Figure 1)
Regarding Claim 4, Kim teaches:
The sensor emulation system of claim 3 (Kim)
where the second memory device includes a second D input and a second Q- output. (Kim, Figure 1)
Regarding Claim 5, Kim teaches:
The sensor emulation system of claim 4 (Kim, Figure 1)
where the first Q- output is electrically coupled to the first D input. (Kim, Figure 1)
Regarding Claim 6, Kim teaches:
The sensor emulation system of claim 5 (Kim)
where the second Q- output is electrically coupled to the second D input. (Kim, Figure 1)
Regarding Claim 9, Kim teaches:
A method for simulating a speed sensor with current output, comprising: providing a signal to a first memory device input (Kim, Figure 1)
and an inverse of the signal to a second memory device input; (Kim, Figure 1)
and supplying a first memory device first output to a first voltage controlled current source (Kim, Figure 1)
and a second memory device first output to a second voltage controlled current source. (Kim, Figure 1)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (Kim, KR 20010039220 A) in view of O’Brien (US 6356129 B1)
Regarding Claim 7:
Kim teaches:
The sensor emulation system of claim 1 (Kim, Figure 1)
on the first memory device (Kim, Figure 1)
on the second memory device. (Kim, Figure 1)
Kim does not teach in particular, but O’Brien teaches:
further comprising a first S input (O’Brien, Figure 8a)
and a first R input (O’Brien, Figure 8a)
and a second S input (O’Brien, Figure 8a)
and a second R input (O’Brien, Figure 8a)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of O’Brien, as Set and Reset signals can be used to keep the clock pulses in sync (O’Brien, Col. 6 Ln. 34-39 “The flip-flop “sets” in response to each rising edge of the input signal and “resets” in response to each falling edge. The flip-flop 810 therefore reproduces the timing of both of the edges of the input signal 710a, and therefore preserves the pulse-width and duty cycle of the input signal”)
Claims 10-12, 16, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Kim, KR 20010039220 A) in view of Wang (CN 207232757 U)
Regarding Claim 10:
Kim teaches:
where the first memory device input is a first clock input, (Kim, Figure 1)
and where the second memory device input is a second clock input. (Kim, Figure 1)
Kim does not teach in particular, but Wang teaches:
where the signal is supplied via a hardware-in-the-loop system, (Wang [0080], “The FPGA 200 also configures the preset pulse signals inside the FPGA 200 according to the sensor status parameter configuration instructions and the sensor type configuration instructions”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 11:
Kim does not teach in particular, but Wang teaches:
where the first voltage controlled current source and the second voltage controlled current source are coupled to a device under test. (Wang [0080])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 12:
Kim does not teach in particular, but Wang teaches:
generating the signal via the hardware-in-the loop system. (Wang [0080], “the output unit 400 processes the isolated wheel speed signals according to the control signals to obtain the wheel speed sensor simulation signal corresponding to the sensor type configuration instructions, and outputs it to the controller of the HIL device”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 16:
Kim teaches:
a first flip-flop (Kim, Figure 1)
at a clock input of the first flip-flop (Kim, Figure 1)
and provide a first voltage output to a first voltage controlled current source; (Kim, Figure 1)
and a second flip-flop (Kim, Figure 1)
configured to receive an inverse of the signal at a clock input of the second flip-flop (Kim, Figure 1)
and provide a second voltage output to a second voltage controlled current source. (Kim, Figure 1)
Kim does not teach in particular, but Wang teaches:
A hardware-in-the-loop (HIL) system with sensor emulation, comprising: a HIL system coupled to a device under test; (Wang [0015], “The output terminal of the output unit outputs a wheel speed sensor simulation signal corresponding to the sensor type configuration instruction to the controller of the hardware-in-the-loop (HIL) device in the automated semi-physical simulation test.”)
configured to receive a signal from the HIL system (Wang [0080], “The FPGA 200 generates control signals according to the sensor type configuration instructions and sends the control signals to the output unit”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 17:
Kim does not teach in particular, but Wang teaches:
a device under test coupled to the system. (Wang [0015], “The output terminal of the output unit outputs a wheel speed sensor simulation signal corresponding to the sensor type configuration instruction to the controller of the hardware-in-the-loop (HIL) device in the automated semi-physical simulation test.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Claims 8, 13-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Kim, KR 20010039220 A) in view of O’Brien (US 6356129 B1) and Wang (CN 207232757 U)
Regarding Claim 8:
Kim does not teach in particular, but O’Brien teaches:
coupled to the first S input, (O’Brien, Figure 7, 8a)
the first R input, (O’Brien, Figure 7, 8a)
the second S input, (O’Brien, Figure 7, 8a)
and the second R input. (O’Brien, Figure 7, 8a)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of O’Brien, as Set and Reset signals can be used to keep the clock pulses in sync (O’Brien, Col. 6 Ln. 34-39 “The flip-flop “sets” in response to each rising edge of the input signal and “resets” in response to each falling edge. The flip-flop 810 therefore reproduces the timing of both of the edges of the input signal 710a, and therefore preserves the pulse-width and duty cycle of the input signal”)
Kim does not teach in particular, but Wang teaches:
where a hardware-in-the-loop system generates the signal (Wang [0080], “the FPGA 200 according to the sensor status parameter configuration instructions and the sensor type configuration instructions to generate current-type wheel speed signals or sinusoidal voltage-type wheel speed signals, and outputs them”)
and includes outputs (Wang [0080], “the output unit 400 processes the isolated wheel speed signals according to the control signals to obtain the wheel speed sensor simulation signal corresponding to the sensor type configuration instructions, and outputs it to the controller of the HIL device”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 13:
Kim does not teach in particular, but O’Brien teaches:
electrically coupling a S input of a first memory device (O’Brien, Figure 7, 8a)
and a R input of the first flip-flop (O’Brien, Figure 7, 8a)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of O’Brien, as Set and Reset signals can be used to keep the clock pulses in sync (O’Brien, Col. 6 Ln. 34-39 “The flip-flop “sets” in response to each rising edge of the input signal and “resets” in response to each falling edge. The flip-flop 810 therefore reproduces the timing of both of the edges of the input signal 710a, and therefore preserves the pulse-width and duty cycle of the input signal”)
Kim does not teach in particular, but Wang teaches:
to the hardware-in-the-loop system. (Wang [0080], “The FPGA 200 generates control signals according to the sensor type configuration instructions and sends the control signals to the output unit”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 14:
Kim does not teach in particular, but O’Brien teaches:
electrically coupling a S input of a second memory device (O’Brien, Figure 7, 8a)
and a R input of the second memory device (O’Brien, Figure 7, 8a)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of O’Brien, as Set and Reset signals can be used to keep the clock pulses in sync (O’Brien, Col. 6 Ln. 34-39 “The flip-flop “sets” in response to each rising edge of the input signal and “resets” in response to each falling edge. The flip-flop 810 therefore reproduces the timing of both of the edges of the input signal 710a, and therefore preserves the pulse-width and duty cycle of the input signal”)
Kim does not teach in particular, but Wang teaches:
to the hardware-in-the-loop system. (Wang [0080], “The FPGA 200 generates control signals according to the sensor type configuration instructions and sends the control signals to the output unit”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 15:
Kim does not teach in particular, but O’Brien teaches:
simulating a change in direction of a device via applying a logical true input to the S input of the first memory device and the R input of the second memory device. (O’Brien, Figure 8b)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of O’Brien, as Set and Reset signals can be used to keep the clock pulses in sync (O’Brien, Col. 6 Ln. 34-39 “The flip-flop “sets” in response to each rising edge of the input signal and “resets” in response to each falling edge. The flip-flop 810 therefore reproduces the timing of both of the edges of the input signal 710a, and therefore preserves the pulse-width and duty cycle of the input signal”)
Regarding Claim 18:
Kim does not teach in particular, but O’Brien teaches:
generating output to a first flip-flop S input, (O’Brien, Figure 7, 8a)
a first flip-flop R input, (O’Brien, Figure 7, 8a)
a second flip-flop S input, (O’Brien, Figure 7, 8a)
and a second flip-flop R input. (O’Brien, Figure 7, 8a)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of O’Brien, as Set and Reset signals can be used to keep the clock pulses in sync (O’Brien, Col. 6 Ln. 34-39 “The flip-flop “sets” in response to each rising edge of the input signal and “resets” in response to each falling edge. The flip-flop 810 therefore reproduces the timing of both of the edges of the input signal 710a, and therefore preserves the pulse-width and duty cycle of the input signal”)
Kim does not teach in particular, but Wang teaches:
a first digital output of the HIL system generating the signal (Wang [0080], “The FPGA 200 generates control signals”)
and additional digital outputs of the HIL system (Wang [0080], “The configuration instructions include sensor status parameter configuration instructions and sensor type configuration instructions”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 19:
Kim does not teach in particular, but Wang teaches:
where the first voltage controlled current source is coupled to the device under test. (Wang [0080], “Finally, the output unit 400 processes the isolated wheel speed signals according to the control signals to obtain the wheel speed sensor simulation signal corresponding to the sensor type configuration instructions, and outputs it to the controller of the HIL device”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Regarding Claim 20:
Kim does not teach in particular, but Wang teaches:
where the second voltage controlled current source is coupled to the device under test. (Wang [0080], “Finally, the output unit 400 processes the isolated wheel speed signals according to the control signals to obtain the wheel speed sensor simulation signal corresponding to the sensor type configuration instructions, and outputs it to the controller of the HIL device”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teachings of Wang, as the circuit of Kim can be implemented in or replace the FPGA and output unit of Wang to simulate a specific type of speed sensor, the motivation being that it enables hardware-in-the-loop testing applications for a specific type of sensor (Wang [0008], “This invention provides a wheel speed sensor simulation board to solve the problems in the prior art that it is difficult to simulate abnormal condition testing under wheel speed sensor fault modes”).
Conclusion
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/BIJAN MAPAR/ Primary Examiner, Art Unit 2189
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