Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is in response to the amendment filed on 19th December, 2025. Claims 1, 8, 15, and 17 have been amended. The amended claims limitations have been fully considered, but are not persuasive. Claims 1-20 remain rejected in the application.
Response to Arguments
In response to applicant’s arguments regarding Hammerstone failing to disclose “during a rendering pass, discarding or ignoring the state packets”, applicant’s arguments have been fully considered but are not persuasive. Hammerstone discloses (Hammerstone; pg. 10 col 7, lines 55 – col 8 lines 1-2) the rendering pass is where the command buffer is re-processed and only visible draw commands are executed, indicating non-visible draw commands and their respective state packets are ignored and, (Hammerstone; col 8 lines 21-26) explicitly states that unprocessed constant updates may be discarded.
The newly amended claimed features are still met by the applied prior art references, thus, the rejections for claims 1 and 8, 15, and 17 are maintained.
In response to applicant’s arguments regarding dependent claims 3-4, 10-12, and 18-19, applicant’s arguments have been fully considered but are not persuasive. Since the rejection for the independent claims 1, 8, and 15, which claims 3-4, 10-12, and 18-19 depend on is maintained, claims 3-4, 10-12, and 18-19 remain rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-9, 13-17, and 20 are rejected under 35 U.S.C. 102 as being unpatentable over Hammerstone (US10157443B1).
Regarding claim 8, Hammerstone discloses a graphics processing device (col. 3 lines 9-16 describe the processes performed by a GPU) configured to render primitives in a frame (col. 3 lines 9-16 determining and rendering primitives) the graphics processing device comprising: circuitry configured to (col. 4 lines 38-42 describes the GPU including circuitry), during a visibility pass, process state packets to determine a register state, and store the register state in a memory device (col. 7 lines 3–54 discloses the steps for processing state packets, determining a register state, and storing it to memory and col. 7 line 55-col 8 line 2 describe said steps occurring during a visibility pass. Specifically, lines 32-35 describe a command processor determines a command (state packet) in the buffer is configured to update one or more values (register state) and lines 29-32 receives and stores (in a memory device) a copy of the state of the constants and the updates. Col. 7 lines 58-63 describe this happening during a visibility pass) and, during a rendering pass, discard or ignore the state packets, and read the register state from the memory device (col. 7 line 55 - col. 8 line 20 describe reading the register state from memory during a rendering pass. Col. 7 line 64 – col 8 line 2, after the visibility pass, the rendering commands are sent again (during the render pass) and reads (from memory) the visibility stream as it processes the command buffer and that only visible draw commands are executed (non-visible draw commands and their respective state packets are ignored). Col 8 lines 21-26, disclose that unprocessed constant updates may be discarded or overwritten.)
Claim 1, has similar limitations as of claim(s) 8, therefore it is rejected under the same rationale as claim(s) 8.
Claim 15, has similar limitations as of claim(s) 8, therefore it is rejected under the same rationale as claim(s) 8.
Regarding Claim 9, Hammerstone discloses circuitry (col. 4 lines 38-42 describes the GPU including circuitry) configure a graphics pipeline during the visibility pass based on the register state determined by processing the state packets. As previously discussed, Hammerstone discloses circuitry configured to determine and store a register state to memory from state packets (see claim 8). Hammerstone describes, col. 7 lines 3–54 the steps for processing state packets, determining a register state, and storing it to memory, specifically col. 7 lines 15-18, the state buffer is comprised of commands to write registers or descriptors (for textures, samplers, shaders, etc.) and to set the current state of the hardware (state commands). Setting the current state of the hardware (including shaders, texture, and samplers) describes configuring a graphics pipeline from the register state. Hammerstone describes this happening during a visibility pass (col. 7 line 60, see claim 8), and configure the graphics pipeline during the rendering pass based on the register state read from the memory device. Hammerstone describes (col. 7 line 64 – col. 8 line 20) during the rendering pass, the steps for configuring the graphics pipeline, specifically, (col. 8 lines 8-11) reading the register file (state, from memory) and loading the updates to a hardware state (configuring the graphics pipeline).
Claim 2, has similar limitations as of claim(s) 9, therefore it is rejected under the same rationale as claim(s) 9.
Claim 16, has similar limitations as of claim(s) 9, therefore it is rejected under the same rationale as claim(s) 9.
Regarding claim 13, Hammerstone discloses the graphics processing device of claim 8, further comprising circuitry configured to store the register state in a cache memory or random-access memory (RAM). As previously discussed, Hammerstone describes storing the register state in memory (see claim 8). Specifically, in col. 7 lines 3-5, the constant, state, and command buffers, which store the register state, are contained in graphics memory (RAM/VRAM).
Claim 6, has similar limitations as of claim(s) 13, therefore it is rejected under the same rationale as claim(s) 13.
Claim 20, has similar limitations as of claim(s) 13, therefore it is rejected under the same rationale as claim(s) 13.
Regarding claim 14, Hammerstone discloses the graphics processing device of claim 8, further comprising circuitry configured to process the state packets to determine the register state (col. 7 lines 32-35 the command processor determines a command (state packet) in the buffer is configured to update one or more values (register state), see claim 8), and that the circuitry is configured to send the register state to acceleration hardware for storage in the memory device (col. 7 lines 29-35 the command and state buffers receive and store a copy of the constants and updates (register state) and, col. 7 lines 3-4, the GPU includes graphics memory which contains said buffers).
Claim 7, has similar limitations as of claim(s) 14, therefore it is rejected under the same rationale as claim(s) 14.
Regarding claim 17, Hammerstone teaches the acceleration device of claim 15, further comprising: circuitry (col. 4 lines 38-42 describes the GPU including circuitry) configured to send register state received from the packet processor to a graphics pipeline during the visibility pass. As previously discussed, Hammerstone describes, col. 7 lines 3–54 the steps for processing state packets, determining a register state, and storing it to memory, specifically col. 7 lines 15-18, the state buffer is comprised of commands to write registers or descriptors (for textures, samplers, shaders, etc.) and to set the current state of the hardware (state commands). Setting the current state of the hardware (including shaders, texture, and samplers) describes configuring a graphics pipeline from the register state (sending register state). Hammerstone describes this happening during a visibility pass (col. 7 line 60, see claim 8). Hammerstone also teaches to send the register state read from the memory device to the graphics pipeline during the rendering pass (col. 7 line 64 - col. 8 line 11, after the visibility pass, the render commands are sent again (render pass), reading from the stored visibility information (register state), executing the draw commands and triangles that are visible, and loading the processed updates to a hardware state (configure the pipeline).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over
Hammerstone (US10157443B1) and Akenine-Moller (US20180082464A1).
Regarding claim 10, Hammerstone describes the graphics processing device of claim 8, further comprising: circuitry configured to process draw packets, and the state packets, from a packet stream, during the visibility pass; As previously discussed, Hammerstone discloses circuitry configured to process and store a register state to memory from state packets and these steps occurring during the visibility pass (see claim 8). Hammerstone describes, col. 7 lines 3–54 the steps for processing the commands (sent from a packet stream), specifically col. 7 lines 6-9, describing draw commands (draw packets) and col. 7 lines 32-35 describing update commands (sate packets); commands coming from the buffer read on packet stream. Hammerstone also discloses to modify the draw packets based on visibility information determined during the visibility pass, (col. 7 line 60-col. 8 line 2, during the visibility pass compute visible draw commands and triangles and store in memory (modified), then during the render pass only execute the visible draw) and process modified draw packets and the replay control packets, during the rendering pass (col. 8 lines 3-5 process all of the updates (during the render pass)). However, Hammerstone does not explicitly disclose processing replay control packets during the visibility and render pass.
Akenine-Moller teaches ¶0129-0130 from Z-prepass, depth-only, (visibility pass) using a “repeat token” (replay control packet) storing the information and, during a render pass, the information from the repeat token is read so as not to be processed twice. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to apply the repeat token as taught by Akenine-Moller to the device as taught by Hammerstone in order to increase efficiency by not repeatedly processing the same information.
Claim 3, has similar limitations as of claim(s) 10, therefore it is rejected under the same rationale as claim(s) 10.
Claims 4-5, 11-12, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hammerstone (US10157443B1) and Favela (US20200193703A1).
Regarding claim 11, Hammerstone teaches the graphics processing device of claim 8, circuitry determining the register state and storing it to memory (see claim 8), but does not explicitly disclose that the circuitry is to do so in an encoded format. Examiner interprets “encode” to mean transforming or converting data into a specific or structured format.
Favela discloses (¶0023) compressing the graphics pipeline state (compressing reduces size and/or redundancy in a repeatable and decodable way; a type of encoding) to provide a more efficient representation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to apply the compression (encoding) as taught by Favela to the device storing as taught by Hammerstone in order to increase efficiency and reduce size in memory.
Claim 4, has similar limitations as of claim(s) 11, therefore it is rejected under the same rationale as claim(s) 11.
Claim 18, has similar limitations as of claim(s) 11, therefore it is rejected under the same rationale as claim(s) 11.
Regarding claim 12, Hammerstone teaches the graphics processing device of claim 8, of determining the register state and storing it to memory, but does not explicitly disclose to do so in a compressed format.
Favela discloses (¶0023) compressing the graphics pipeline state (compressing reduces size and/or redundancy in a repeatable and decodable way; a type of encoding) to provide a more efficient representation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to apply the compression (encoding) as taught by Favela to the device storing as taught by Hammerstone in order to increase efficiency and reduce size in memory.
Claim 5, has similar limitations as of claim(s) 12, therefore it is rejected under the same rationale as claim(s) 12.
Claim 19, has similar limitations as of claim(s) 12, therefore it is rejected under the same rationale as claim(s) 12.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAN F KALHORI whose telephone number is (571)272-5475. The examiner can normally be reached Mon-Fri 8:30-5:30 ET.
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/DAN F KALHORI/Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618
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