DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the Application filed on June 20, 2023. Claims 1-20 are pending in the case. Claims 1, 8, and 15 are the independent claims.
This action is non-final.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102€, (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Riga et al. (US 20160124644 A1) in view of Kim et al. (US 20240330665 A1).
With respect to claim 1, Riga teaches a memory device, the memory device comprising:
a plurality of bank groups, a bank group comprising one or more memory banks in the memory device (e.g. paragraph 0021, multiple banks for storing data arranged into multiple bank groups; paragraph 0048, Fig. 8, banks 100-106 grouped into first and second bank groups);
a plurality of buffers, each buffer associated with a different bank group of the plurality of bank groups (e.g. paragraph 0049, Fig. 8, buffers 140, 142 (forming allocation queue for bank group 0) and 144, 146 (forming allocation queue for bank group 1));
a group selection module (e.g. paragraph 0049, Fig. 8, buffer/bank group selection demultiplexer 138 of allocation circuitry 126) configured to:
receive one or more data transfer requests, select one or more bank groups from the plurality of bank groups, and write the one or more data transfer requests in one or more buffers associated with the one or more bank groups (e.g. paragraph 0026, data block received by data storage apparatus; paragraph 0027, allocation circuitry for allocating data items for storage comprising independent allocation queue for each bank group; paragraph 0028, allocation circuitry comprises more than one data buffer for each bank group, wherein each data buffer is capable of buffering the data block; storing data into each bank group; paragraph 0049, data block (chunk) received from write control circuitry 110 at input of allocation circuitry 126 of instruction cache/memory of Fig. 8; buffer/bank group selection demultiplexer 138 of allocation circuitry 126 determines whether the data block should be stored in bank group 0 or bank group 1; determining which of buffers 140, 142 (forming allocation queue for bank group 0) and 144, 146 (forming allocation queue for bank group 1) the data block should be temporarily stored); and
a plurality of bank selection modules, a bank selection module associated with a bank group and configured to:
receive a memory address of a data transfer request stored in a buffer associated with the bank group, and select a memory bank from the bank group based on the memory address (e.g. paragraph 0024, storage circuitry selecting bank within bank group; paragraph 0039, Fig. 2A, discussing usage of memory address in administering storage of data items in location indicated by the address; paragraph 0047, Fig. 8, determining whether or not content of particular memory address currently stored in cache or not, returning data items or signaling the content of the memory address is not currently stored in the cache; paragraph 0049, multiplexers 148, 150 selecting which of the respective input buffers should be connected to the write port of each bank at each cycle; paragraph 0051, mapping each memory address and data bank entry to corresponding way number; paragraph 0052, Fig. 11, bank 184 includes address input 186; in dependence on the bank required for the request, the address is passed to the address input of the bank or to another bank in the same group; i.e. the memory address is transferred to at least one bank within the bank group, such that the address is transmitted to the bank group; paragraph 0052, Fig. 11, showing arbitration and allocation circuitry for given bank; selector 180 selecting between request from source 1, source 2, and allocation and passing output of this selection; bank required for the request selected by the multiplexer, and passing address to address input 186 of the bank or to another bank in the same bank group; multiplexer 194 selecting between data chunk to allocate and data chunk from another source, and providing output to write port 190 of the bank 184).
Riga does not explicitly that the device is for a deep learning operation, that the data transfer requests are associated with the deep learning operation. However, Kim teaches that the device is for a deep learning operation, that the data transfer requests are associated with the deep learning operation (e.g. paragraph 0088, device specialized for performing deep learning computational work; paragraph 0103, neural core SoC performing computations for deep learning reasoning and training; paragraph 0299, allocating data to memory banks; paragraph 0360, shared memory controlled by controllers, including on a memory bank basis; paragraph 0361, shared memory enabling fast and efficient deep learning work).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Riga and Kim in front of him to have modified the teachings of Riga (directed to data storage organization techniques), to incorporate the teachings of Kim (directed to an apparatus comprising neural processors, a command processor, and a shared memory) to include the capability to utilize the system and method (i.e. of Riga) for performing deep learning operations, including associated data transfer requests. One of ordinary skill would have been motivated to perform such a modification in order to enable fast and efficient deep learning work as described in Kim (paragraph 0361).
With respect to claim 8, Riga teaches an apparatus, the apparatus comprising:
one or more processing elements (e.g. paragraph 0047, Fig. 8, write control circuitry 110, read control circuitry 108); and
a memory comprising: a plurality of bank groups, a bank group comprising one or more memory banks in the memory, a plurality of buffers, each buffer associated with a different bank group of the plurality of bank groups ((e.g. paragraph 0021, multiple banks for storing data arranged into multiple bank groups; paragraph 0048, Fig. 8, banks 100-106 grouped into first and second bank groups); paragraph 0049, Fig. 8, buffers 140, 142 (forming allocation queue for bank group 0) and 144, 146 (forming allocation queue for bank group 1));
a group selection module (e.g. paragraph 0049, Fig. 8, buffer/bank group selection demultiplexer 138 of allocation circuitry 126) configured to receive one or more data transfer requests from the one or more processing elements, select one or more bank groups from the plurality of bank groups, and write the one or more data transfer requests in one or more buffers associated with the one or more bank groups (e.g. paragraph 0026, data block received by data storage apparatus; paragraph 0027, allocation circuitry for allocating data items for storage comprising independent allocation queue for each bank group; paragraph 0028, allocation circuitry comprises more than one data buffer for each bank group, wherein each data buffer is capable of buffering the data block; storing data into each bank group; paragraph 0049, data block (chunk) received from write control circuitry 110 at input of allocation circuitry 126 of instruction cache/memory of Fig. 8; buffer/bank group selection demultiplexer 138 of allocation circuitry 126 determines whether the data block should be stored in bank group 0 or bank group 1; determining which of buffers 140, 142 (forming allocation queue for bank group 0) and 144, 146 (forming allocation queue for bank group 1) the data block should be temporarily stored), and
a plurality of bank selection modules (), a bank selection module associated with a bank group and configured to receive a memory address of a data transfer request stored in a buffer associated with the bank group and to select a memory bank from the bank group based on the memory address (e.g. paragraph 0024, storage circuitry selecting bank within bank group; paragraph 0039, Fig. 2A, discussing usage of memory address in administering storage of data items in location indicated by the address; paragraph 0047, Fig. 8, determining whether or not content of particular memory address currently stored in cache or not, returning data items or signaling the content of the memory address is not currently stored in the cache; paragraph 0049, multiplexers 148, 150 selecting which of the respective input buffers should be connected to the write port of each bank at each cycle; paragraph 0051, mapping each memory address and data bank entry to corresponding way number; paragraph 0052, Fig. 11, bank 184 includes address input 186; in dependence on the bank required for the request, the address is passed to the address input of the bank or to another bank in the same group; i.e. the memory address is transferred to at least one bank within the bank group, such that the address is transmitted to the bank group; paragraph 0052, Fig. 11, showing arbitration and allocation circuitry for given bank; selector 180 selecting between request from source 1, source 2, and allocation and passing output of this selection; bank required for the request selected by the multiplexer, and passing address to address input 186 of the bank or to another bank in the same bank group; multiplexer 194 selecting between data chunk to allocate and data chunk from another source, and providing output to write port 190 of the bank 184).
Riga does not explicitly disclose that the apparatus is for a deep learning operation, that the one or more processing elements are configured to perform the deep learning operation. However, Kim teaches that the apparatus is for a deep learning operation, that the one or more processing elements are configured to perform (e.g. paragraph 0088, device specialized for performing deep learning computational work; paragraph 0103, neural core SoC performing computations for deep learning reasoning and training; paragraph 0299, allocating data to memory banks; paragraph 0360, shared memory controlled by controllers, including on a memory bank basis; paragraph 0361, shared memory enabling fast and efficient deep learning work).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Riga and Kim in front of him to have modified the teachings of Riga (directed to data storage organization techniques), to incorporate the teachings of Kim (directed to an apparatus comprising neural processors, a command processor, and a shared memory) to include the capability to utilize the system and method (i.e. of Riga) for performing deep learning operations, including associated data transfer requests. One of ordinary skill would have been motivated to perform such a modification in order to enable fast and efficient deep learning work as described in Kim (paragraph 0361).
With respect to claim 15, Riga teaches a method, comprising:
receiving, by a memory from one or more processing elements, one or more data transfer requests, the memory comprising a plurality of bank groups, a bank group comprising one or more memory banks (e.g. paragraph 0021, multiple banks for storing data arranged into multiple bank groups; paragraph 0026, data block received by data storage apparatus; paragraph 0048, Fig. 8, banks 100-106 grouped into first and second bank groups; paragraph 0049, data block (chunk) received from write control circuitry 110 at input of allocation circuitry 126 of instruction cache/memory of Fig. 8);
selecting one or more bank groups from the plurality of bank groups (e.g. paragraph 0027, allocation circuitry for allocating data items for storage comprising independent allocation queue for each bank group; paragraph 0049, Fig. 8, buffer/bank group selection demultiplexer 138 of allocation circuitry 126 determines whether the data block should be stored in bank group 0 or bank group 1);
writing the one or more data transfer requests in one or more buffers associated with the one or more bank groups (e.g. paragraph 0028, allocation circuitry comprises more than one data buffer for each bank group, wherein each data buffer is capable of buffering the data block; storing data into each bank group; paragraph 0049, Fig. 8, determining which of buffers 140, 142 (forming allocation queue for bank group 0) and 144, 146 (forming allocation queue for bank group 1) the data block should be temporarily stored);
transmitting one or more memory addresses of the one or more data transfer requests from the one or more buffers to the one or more bank groups (e.g. paragraph 0039, Fig. 2A, discussing usage of memory address in administering storage of data items in location indicated by the address; paragraph 0047, Fig. 8, determining whether or not content of particular memory address currently stored in cache or not, returning data items or signaling the content of the memory address is not currently stored in the cache; paragraph 0051, mapping each memory address and data bank entry to corresponding way number; paragraph 0052, Fig. 11, bank 184 includes address input 186; in dependence on the bank required for the request, the address is passed to the address input of the bank or to another bank in the same group; i.e. the memory address is transferred to at least one bank within the bank group, such that the address is transmitted to the bank group);
selecting one or more memory banks from the one or more bank groups based on the one or more memory addresses (e.g. paragraph 0024, storage circuitry selecting bank within bank group; paragraph 0049, multiplexers 148, 150 selecting which of the respective input buffers should be connected to the write port of each bank at each cycle; paragraph 0052, Fig. 11, showing arbitration and allocation circuitry for given bank; selector 180 selecting between request from source 1, source 2, and allocation and passing output of this selection; bank required for the request selected by the multiplexer, and passing address to address input 186 of the bank or to another bank in the same bank group; multiplexer 194 selecting between data chunk to allocate and data chunk from another source, and providing output to write port 190 of the bank 184); and
transferring data between the one or more memory banks and the one or more processing elements (e.g. paragraph 0021, circuitry associated with banks directing data items to be stored to selected bank; paragraph 0049, data block (chunk) received from write control circuitry 110 at input of allocation circuitry 126 of instruction cache/memory of Fig. 8; paragraph 0049, multiplexers 148, 150 selecting which of the respective input buffers should be connected to the write port of each bank at each cycle; determining which of buffers 140, 142 (forming allocation queue for bank group 0) and 144, 146 (forming allocation queue for bank group 1) the data block should be temporarily stored; paragraph 0052, Fig. 11, showing arbitration and allocation circuitry for given bank; selector 180 selecting between request from source 1, source 2, and allocation and passing output of this selection; bank required for the request selected by the multiplexer, and passing address to address input 186 of the bank or to another bank in the same bank group; multiplexer 194 selecting between data chunk to allocate and data chunk from another source, and providing output to write port 190 of the bank 184; i.e. data is transferred between the selected memory bank and the processing element (write control circuitry) by receiving the data from the write control circuitry, passing it to the corresponding buffer/cache for the selected bank group, and the writing the data to the corresponding portions of the selected bank).
Riga does not explicitly disclose that the method is for a deep learning operation, that the data transfer requests are associated with the deep learning operation. However, Kim teaches that the method is for a deep learning operation, that the data transfer requests are associated with the deep learning operation (e.g. paragraph 0088, device specialized for performing deep learning computational work; paragraph 0103, neural core SoC performing computations for deep learning reasoning and training; paragraph 0299, allocating data to memory banks; paragraph 0360, shared memory controlled by controllers, including on a memory bank basis; paragraph 0361, shared memory enabling fast and efficient deep learning work).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Riga and Kim in front of him to have modified the teachings of Riga (directed to data storage organization techniques), to incorporate the teachings of Kim (directed to an apparatus comprising neural processors, a command processor, and a shared memory) to include the capability to utilize the system and method (i.e. of Riga) for performing deep learning operations, including associated data transfer requests. One of ordinary skill would have been motivated to perform such a modification in order to enable fast and efficient deep learning work as described in Kim (paragraph 0361).
With respect to claims 2, 10, and 17, Riga in view of Kim teaches all of the limitations of claims 1, 8, and 15 as previously discussed, and Kim further teaches wherein the one or more processing elements (in claims 10 and 17) and the group selection module are in a first clock domain, the plurality of bank selection modules is in a second clock domain that is slower than the first clock domain (in claim 2)/the first clock domain is faster than the second clock domain (in claims 10 and 17) (e.g. paragraph 0377, second path unit (P2) configuring async-path; the operating clock frequency of the second path unit (P2) may the same as that of the global interconnection 6000; the second path unit (P2) may also operate at the same clock frequency as the operating clock frequency of the global interconnection 6000; paragraph 0378, operating clock frequency of second path unit (P2) not synchronized with the operating clock frequency of the bank controller (Bc)).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Riga and Kim in front of him to have modified the teachings of Riga (directed to data storage organization techniques), to incorporate the teachings of Kim (directed to an apparatus comprising neural processors, a command processor, and a shared memory) to include the capability to implement the system and method (i.e. of Riga) such that the processing elements and group selection module are in a first clock domain and the bank selection modules are in a second, slower clock domain. One of ordinary skill would have been motivated to perform such a modification in order to enable fast and efficient deep learning work as described in Kim (paragraph 0361).
With respect to claims 3, 11, and 18, Riga in view of Kim teaches all of the limitations of claims 2, 10, and 17 as previously discussed, and Kim further teaches wherein the plurality of buffers includes a clock domain crossing buffer (e.g. paragraph 0378, operating clock frequency of second path unit (P2) not synchronized with the operating clock frequency of the bank controller (Bc); clock domain crossing (CDC) work required to synchronize the clocks between the bank controller (Bc) and the second path unit (P2)).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Riga and Kim in front of him to have modified the teachings of Riga (directed to data storage organization techniques), to incorporate the teachings of Kim (directed to an apparatus comprising neural processors, a command processor, and a shared memory) to include the capability to implement the system and method (i.e. of Riga) to include a clock domain crossing buffer. One of ordinary skill would have been motivated to perform such a modification in order to enable fast and efficient deep learning work as described in Kim (paragraph 0361).
With respect to claims 4 and 12, Riga in view of Kim teaches all of the limitations of claims 1 and 8 as previously discussed, and Riga further teaches the device/apparatus further comprising: a plurality of interconnects, each interconnect coupling a corresponding bank group to a corresponding buffer associated with the corresponding bank group for transferring data from the corresponding buffer to the corresponding bank group (e.g. paragraph 0049, Fig. 8; as shown in Fig. 8, each bank group is coupled to corresponding buffers for transferring data from the buffer to the bank group, i.e. via corresponding interconnects, such as in response to a write request; input buffers connected to the write port of each bank at each cycle).
With respect to claims 5 and 13, Riga in view of Kim teaches all of the limitations of claims 4 and 12 as previously discussed, and Kim teaches wherein: the group selection module is in a first clock domain, and the plurality of interconnects, the plurality of bank selection modules, or the plurality of bank groups is in a second clock domain that is slower than the first clock domain (e.g. paragraph 0377, second path unit (P2) configuring async-path; the operating clock frequency of the second path unit (P2) may the same as that of the global interconnection 6000; the second path unit (P2) may also operate at the same clock frequency as the operating clock frequency of the global interconnection 6000; paragraph 0378, operating clock frequency of second path unit (P2) not synchronized with the operating clock frequency of the bank controller (Bc)).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Riga and Kim in front of him to have modified the teachings of Riga (directed to data storage organization techniques), to incorporate the teachings of Kim (directed to an apparatus comprising neural processors, a command processor, and a shared memory) to include the capability to implement the system and method (i.e. of Riga) such that the group selection module are in a first clock domain and the interconnects, bank selection modules, or the bank groups are in a second, slower clock domain. One of ordinary skill would have been motivated to perform such a modification in order to enable fast and efficient deep learning work as described in Kim (paragraph 0361).
With respect to claims 6 and 14, Riga in view of Kim teaches all of the limitations of claims 1 and 8 as previously discussed, and further teaches wherein: a first bank selection module is configured to receive an address of a first data transfer task in a first clock cycle, a second bank selection module is configured to receive an address of a second data transfer task in a second clock cycle, and the second clock cycle is immediately after the first clock cycle (e.g. paragraph 0005, storing data items of data blocks according to a sequence of banks which respects a hierarchical pattern, wherein a coarser granularity of the hierarchical pattern comprises the given bank group followed by a different bank group to the given bank group; paragraph 0042, Fig. 3, sequence of banks used for storing sequential data items follows hierarchical pattern; at a coarser level of granularity, considering boxes 40-46 as individual units and observing the pattern of those units, the hierarchical pattern progresses diagonally upwards and rightwards through box 40 (i.e. in bank group 0) and the diagonally upwards and rightwards through dashed box 42 (i.e. in bank group 1), then returns to bank group 0 and proceeds diagonally upwards and rightwards through box 44, and finally proceeds upwards and rightwards through dashed box 46 (bank group 1); paragraph 0043, storing data items in given storage location indicated by index of corresponding memory address for the cache line; paragraph 0047, for read operation, determining if content of particular memory address stored in cache; paragraph 0048, Fig. 8, banks divided into first bank group 0 and second bank group 1; providing a single bank address and enable signal to each bank group determining which data items will be accessed at any given cycle; paragraph 0049, buffer/bank group selection demultiplexer determining whether the data block should be stored in bank group 0 or bank group 1 in accordance with the sequence of banks/bank groups defined in the hierarchical pattern of the present techniques; further multiplexers 148 and 150 select which of their respective input buffers connected to the write port of each bank at each cycle, forming allocation queue for bank group 0 and for bank group 1; i.e. when using a coarser hierarchical storage pattern which alternates between different bank groups for each sequential data item/block/chunk, and where the data transfer task includes a corresponding address, at a first time/clock cycle, a first bank group (e.g. bank group 0) is selected and the corresponding bank selection module for that bank group (e.g. multiplexer 148) receives the corresponding data/address, and at a second (next/immediately sequential) time/clock cycle, the second bank group (e.g. bank group 1) is selected and its corresponding bank selection module (e.g. multiplexer 150) would receive the corresponding data/address).
With respect to claim 7, Riga in view of Kim teaches all of the limitations of claim 6 as previously discussed, and Riga further teaches wherein the group selection module or a bank selection module comprises a demultiplexer (e.g. paragraph 0049, Fig. 8, buffer/bank group selection demultiplexer 138).
With respect to claims 9 and 19, Riga in view of Kim teaches all of the limitations of claims 8 and 15 as previously discussed, and Riga further teaches wherein the data transfer request comprises a request to read input data operation from the memory or a request to write output data of the operation into the memory (e.g. paragraphs 0047-0049, Fig. 8, control of/access to bank groups controlled by read control circuitry 108 and write control circuitry 110; read control circuitry performing look-up procedure to return either corresponding data or signal that content not currently stored in the cache and must be retrieved from further in the memory; input data received from write control circuitry for allocation into cache storage provided by the banks).
With respect to claim 16, Riga in view of Kim teaches all of the limitations of claim 15 as previously discussed, and Riga further teaches wherein selecting one or more bank groups from the plurality of bank groups comprises: selecting two different bank groups for two data transfer requests received by the memory consecutively (e.g. paragraph 0005, storing data items of data blocks according to a sequence of banks which respects a hierarchical pattern, wherein a coarser granularity of the hierarchical pattern comprises the given bank group followed by a different bank group to the given bank group; paragraph 0042, Fig. 3, sequence of banks used for storing sequential data items follows hierarchical pattern; at a coarser level of granularity, considering boxes 40-46 as individual units and observing the pattern of those units, the hierarchical pattern progresses diagonally upwards and rightwards through box 40 (i.e. in bank group 0) and the diagonally upwards and rightwards through dashed box 42 (i.e. in bank group 1), then returns to bank group 0 and proceeds diagonally upwards and rightwards through box 44, and finally proceeds upwards and rightwards through dashed box 46 (bank group 1); paragraph 0049, buffer/bank group selection demultiplexer determining whether the data block should be stored in bank group 0 or bank group 1 in accordance with the sequence of banks/bank groups defined in the hierarchical pattern of the present techniques; i.e. where each input data item may correspond to a respective data transfer request, for a first request out of multiple requests/data items, a corresponding first bank group is selected and, for a second sequential/consecutive request out of the multiple requests/data items, a corresponding second different bank group is selected, resulting in selecting at least two different bank groups for at least two data transfer requests received consecutively).
With respect to claim 20, Riga in view of Kim teaches all of the limitations of claim 15 as previously discussed, and Riga further teaches wherein transmitting the one or more memory addresses of the one or more data transfer requests from the one or more buffers to the one or more bank groups comprises: transmitting the one or more memory addresses through one or more interconnects, each interconnect coupling one of the one or more buffers to one of the one or more bank groups (e.g. paragraph 0049, Fig. 8; as shown in Fig. 8, each bank group is coupled to corresponding buffers for transferring data from the buffer to the bank group, i.e. via corresponding interconnects, such as in response to a write request; input buffers connected to the write port of each bank at each cycle; in addition, as shown in Fig. 11, memory address data is written to the address input 186 of the bank 184 or another bank in the group, where this transfer would occur via the corresponding illustrated connection/interconnect between the bank group and buffer).
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain,” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting in re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (GCPA 1968)). Further, a reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill the art, including nonpreferred embodiments. Merck & Co, v. Biocraft Laboratories, 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert, denied, 493 U.S. 975 (1989). See also Upsher-Smith Labs. v. Pamlab, LLC, 412 F,3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir, 2005): Celeritas Technologies Ltd. v. Rockwell International Corp., 150 F.3d 1354, 1361, 47 USPQ2d 1516, 1522-23 (Fed. Cir. 1998).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY L STANLEY whose telephone number is (469)295-9105. The examiner can normally be reached on Monday-Friday from 9:00 AM to 5:00 PM CST.
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/JEREMY L STANLEY/
Primary Examiner, Art Unit 2127
Prosecution Insights