Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-15) in the reply filed on 01/20/2026 is acknowledged. The traversal is on the ground(s) that the restriction requirement is traversed because “examination of Groups I, II, and III would not be onerous and that in the present case, as indicated in the restriction requirement, the examiner would only have to search three class/subclasses in order to search and examine the pending claims. Applicants respectfully submits that searching three class/subclasses would not present a serious burden on the examiner”. This is not found persuasive because restriction for examination purposes as indicated is proper because all the inventions listed in previous action are independent or distinct for the reasons given in previous action and there would be a serious search and/or examiner burden if restriction were not required because one or more of the following reasons apply: the search of each of the inventions require a different search query, i.e. three different class/subclasses.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: claim 1 recites “a method comprising: storing a plurality of models…receiving…and applying…” which is a process.
Step 2A, Prong 1: claim 1 recites an abstract idea as follows:
Claim 1 recites a judicial exception, a mental process that may be carried out in the human mind or with the aid of pencil and paper in simple situations, or by a monitoring system, or hardware processors, for more complicated situations (see limitations “receiving a plurality of parameters…selecting at least one model from a plurality of models…and applying…thereby defining a virtual slice of the automated test equipment architecture that provides one or more electrical signals that meet the predetermined test requirements at the one or more pins”).
At Step 2A, Prong 2, the abstract idea is not integrated into a practical application. There is no particular machine recited.
The claim recites “pins”, “physical hardware”, and “automated test equipment architecture” are not particular devices. They are field of use devices.
Limitation “applying the selected at least one model to configure physical hardware of the automated test equipment architecture thereby defining a virtual slice of the automated test equipment architecture that provides one or more electrical signals that meet the predetermined test requirements at the one or more pins” when viewed as individual or in combination, does not apply the abstract idea with, or by use of, any particular machine, nor does it affect a real-world transformation or reduction of a particular article to a different state or thing.
Instead, the claim appears to monopolize the abstract idea itself for any purpose or in any practical application where it might conceivably be used. It can cover anything that could be done in the field of automatic test equipment.
The “(provided) one or more electrical signals that meet the predetermined test requirements at the one or more pins” are data and insignificant and the use is unlimited.
At Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, for reasons that are analogous to the discussion of additional elements at Prong 2.
Therefore, claim 1 is ineligible.
Claim 10 recites a computer readable medium which does not offer a meaningful limitation beyond generally linking the medium claim to a particular technological environment, that is, implementation via a computer processor. The medium claim is no different from the method claim 1 in substance; the method claim recites the abstract idea while the medium claim, recite generic components configured to implement the same abstract idea. The claim does not amount to significantly more than the underlying abstract idea.
Dependent claim 2 adds a limitation which is data merely extending the abstract idea without adding any additional elements.
Dependent claim 3 adds a limitation, “the computer is coupled to the virtualized automated test equipment architecture using a serial or parallel bus” which is not a particular device. It is a tool to perform the method.
Dependent claim 4 adds a limitation, “the computer is coupled to…using a wireless interface” which is not a particular device. It is a tool to perform the method.
Dependent claim 5 adds a limitation, “the computer is coupled to…over an ethernet connection” which is not a particular device. It is a tool to perform the method. It is merely extending the abstract idea without adding any additional elements.
Dependent claim 6 adds a limitation “generating a model from a pattern library” is data gathering and is data merely extending the abstract idea without adding any additional elements.
Dependent claims 6-9 add limitations which are data merely extending the abstract idea without adding any additional elements.
Dependent claim 11 adds a limitation which is data gathering merely extending the abstract idea without adding any additional elements.
Dependent claim 12 adds a limitation which is data gathering merely extending the abstract idea without adding any additional elements. The “(generated) model” is data and insignificant. Its use is unlimited.
Dependent claims 13 and 14 add limitations which are data merely extending the abstract idea without adding any additional elements.
Dependent claim 15 adds a limitation which is data gathering merely extending the abstract idea without adding any additional elements. The “(stored) generate model” is data and insignificant. Its use is unlimited.
Further, claims 10-15 are also rejected under 35 U.S.C. 101 as the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to a set of application program interfaces embodied on a computer readable medium which are drawn to a "computer readable medium". The broadest reasonable interpretation of a claim drawn to a computer readable medium covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, particularly when the specification is silent (see MPEP 2111.01). Because the broadest reasonable interpretation covers a signal per se, a rejection under 35 USC 101 is appropriate as covering non-statutory subject matter. See 351 OG 212, Feb 23 2010.
Computer-readable medium which covers both non-transitory tangible media and transitory propagating signals. As such, these claims are drawn to signals per se and are not directed to one of the statutory categories of invention (See MPEP 2106.01).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 10, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Birurakis et al. (hereinafter ‘Birurakis)(USPAP. 20170276725).
Regarding claims 1 and 10, Birurakis discloses a method comprising:
storing a plurality of models (software, test executive and configuration of test programs) associated with the configuration of a slice in a virtual automated test equipment architecture (Pars. 1, 25, 47: see storage of the programs at Par. 47);
receiving a plurality of parameters associated with one or more electrical signals associated with one or more pins (cabling or wires to the unit deter test. Par. 48: physical contact with wire connections from the ATE through a connecting device to cabling or wires to the unit under test (UTT)) wherein the parameters are associated with predetermined test requirements related to a unit under test (Par. 48: execution engine using stimulus signals directed to a unit under test, receiving response signals and analyzing those signals to determine faults);
selecting at least one model from the plurality of models based on the received parameters (Pars. 54 and 55: Engine requests reservation of one or more cores for the ATE execution engine)
and applying the selected at least one model to configure physical hardware of the automated test equipment architecture thereby defining a virtual slice of the automated test equipment architecture that provides one or more electrical signals that meet the predetermined test requirements at the one or more pins (Par. 55: ATE executes the test program using dedicated said cores. Par. 57: using dedicated cores for the instrument operations, the instrument operations are executed with deterministic timing where the start time of each instrument operation is guaranteed to be exactly on the configured time interval).
Regarding claims 2 and 11, Birurakis discloses wherein the plurality of parameters are received from a computer (computer at Par. 48) coupled to the virtualizable automated test equipment architecture (Par. 48: execution engine using stimulus signals directed to a unit under test, receiving response signals and analyzing those signals to determine faults).
Regarding claim 3, Birurakis discloses wherein the computer is coupled to the virtualizable automated test equipment architecture using a serial or parallel bus (buses at Par. 41).
Regarding claim 4, Birurakis discloses wherein the computer is coupled to the virtualizable automated test equipment architecture using a wireless interface (see network and interface in Figs. 6 and 9).
Regarding claim 5, Birurakis discloses wherein the computer is coupled to the virtualizable automated test equipment architecture over an ethernet connection (Pars. 43, 48: network communication Figs. 2, 6, and 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Birurakis and Ungar et al. (hereinafter “Ungar”)(USPAP. 2018/0205621).
Regarding claims 6 and 12, Birurakis does not explicitly disclose generating a model from a pattern library.
Ungar teaches generating a model from a pattern library (Ungar: Pars. 56 and 67: pattern generator that produces the bit sequences that are fed to the UUT’s data input port. Par. 60: the generator feeds the patterns to the ATE or derived from the test mechanism and applies it to low speed and high speed I/Os).
It would have been obvious to one of ordinary skilled in the art at the time of filling the Application to modify 's invention using 's invention to arrive at the claimed invention specified in claim to detect and diagnose failures (Ungar: Par. 60).
Regarding claims 7 and 13, Birurakis and Ungar disclose everything as applied above. In addition, Ungar teaches wherein the pattern library includes a plurality of input/output (I/O) patterns (Ungar: Par. 60: The Pat-Gen (pattern generator) 32 supplies the test patterns either directly from the ATE 20 or derived from the test mechanism and applies it to low speed and high speed I/Os).
Regarding claims 8 and 14, Birurakis and Ungar disclose everything as applied above. In addition, Ungar teaches wherein the I/O patterns are associated with I/O basic types, signal conditioning, and/or signal modes (Par. 56: Patterns of bit sequences, data input).
Regarding claims 9 and 15, Birurakis and Ungar disclose everything as applied above. In addition, Ungar teaches storing the model generated from the pattern library with the plurality of models (Par. 52: storage in the Test Database).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Klein et al. (USPAP. 20230315598) discloses an apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program (Abstract; Pars. 19-28).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG HUYNH whose telephone number is (571)272-2718. The examiner can normally be reached M-F: 9:00AM-5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew M Schechter can be reached at 571-272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHUONG HUYNH/ Primary Examiner, Art Unit 2857 February 20, 2026