DETAILED ACTION
This action is responsive to the request for consideration and arguments submitted by applicant filed on June 13, 2026.
Claims 1-15 remain pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20230282576) in view of Lee et al (US 20210193661) and Morishita et al (20080251860).
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Regarding Independent Claim 1, Yang teaches memory device (Fig. 7: 700) including a plurality of pages arranged in a column direction, each of the pages being constituted by a plurality of plurality of memory cells arranged in a row direction, each of the memory cells comprising:
a semiconductor body (Fig. 2: 210) formed on the substrate in a first direction vertical to the substrate or formed to extend (Fig. 2: 202) in a second direction orthogonal to the first direction, wherein the semiconductor body (Fig. 2: 210) is formed to have a length measured from a first end (Fig. 2: 234; this region is at one end of the semiconductor body.) of the semiconductor body through a second end (Fig. 2: 222; this region is at one end of the semiconductor body.) thereof and formed to have one type of carriers (Fig. 2: P+) charged throughout the length of the semiconductor body;
a first impurity region (Fig. 2: 234) that has a conductivity type (Fig. 2: N+) and is connected to the first end (Fig. 2: 234; this region is at one end of the semiconductor body.) of the semiconductor body (Fig. 2: 210) and a second impurity region (Fig. 2: 222) that has said conductivity type (Fig. 2: N+) and is connected to the second end Fig. 2: 222; this region is at one end of the semiconductor body.) of the semiconductor body (Fig. 2: 210);
a gate insulator layer (Fig. 2: 212) formed in contact with a side surface of the semiconductor body (Fig. 2: 212) between the first impurity region (Fig. 2: 234) and the second impurity region (Fig. 2: 222);
a first gate conductor layer (Fig. 2: 248) formed adjacent to the first end (Fig. 2: 234; this region is at one end of the semiconductor body.) of the semiconductor body (Fig. 2: 210) to at least partially cover the gate insulator layer (Fig. 2: 212), wherein no conductive layer is formed around the gate insulator layer (Fig. 2: 212) between the first gate conductor layer (Fig. 2: 248) and the first end (Fig. 2: 234; this region is at one end of the semiconductor body.) of the semiconductor body (Fig. 2: 210);
a second gate conductor layer (Fig. 2: 244) formed adjacent to the first gate conductor layer (Fig. 2: 248) and adjacent to the second end (Fig. 2: 222; this region is at one end of the semiconductor body.) of the semiconductor body (Fig. 2: 210) to at least partially cover the gate insulator layer (Fig. 2: 212), wherein no conductivity layer is formed around the gate insulator (Fig. 2: 212) layer between the first and second gate conductor layers (Fig. 2: 244, 248) or between the second conductor layer (Fig. 2: 244) and the second end (Fig. 2: 222; this region is at one end of the semiconductor body.) of the semiconductor body (Fig. 2: 210);
Although Yang mentions that their memory device utilizes a read, program (write), and erase operation, as would be expected for their DRAM, and it would have been well-understood in the memory art, by persons skilled in the memory art, that Yang’s DRAM, to be fully-functional, requires voltages to be applied to its bit line (e.g., Fig. 1: BL), word line (e.g., Fig. 1: WL), plate line (e.g., Fig. 1: PL), and source line (e.g., Fig. 1: SL) during its operations. The device would not operate without these voltages. Yang, however, does not mention any specifics (e.g., voltages, to what line they are applied) for their mentioned erase operation. Yang is silent with respect to the claim language relating to an erase operation where one of two conduction layers and one of two impurity has a positive voltage applied to it in order to reduce the number of holes in the body of the semiconductor and erase data written to it.
Lee, however, teaches, for a related DRAM device, and how to perform a page write operation (Fig. 9: “write 1”) and a page erase (Fig. 9: “write 0”) operation on respective memory cells arranged in the selected one of the pages, wherein the page write operation is performed to increase positive holes , by operation of an impact ionization phenomenon, in the respective memory cells, and wherein of collecting the page erase operation is performed to move a majority of a group of the positive holes in the semiconductor body (Fig. 1: 134) of a selected respective memory cells through in a part of the semiconductor body toward one end of the semiconductor body to erase the majority of the positive holes,
wherein the page erase operation is operated to apply “non-negative” voltages (Fig. 9: “write 0,” where writing “0” is equivalent to an erase, SOURCE REGION, GATE2, BIT LINE, SELECTION) to the first impurity region (see Fig. 9: “write 0”, SOURCE REGION), the second impurity region (Fig. 9: write 0, BIT LINE), the first gate conductor layer (Fig. 9: “write 0”, GATE2), and the second gate conductor layer (Fig. 9: “write 0”, SELECTION) of the respective memory cells, wherein a ground voltage (Fig. 9: “write 0”, SOURCE REGION) is applied to one of the first impurity region or the second impurity region, and a first positive voltage (Fig. 9: “write 0”, BIT LINE) is applied to the other of the first impurity region or the second impurity region, and wherein a second positive voltage (Fig. 9: “write 0”, SELECTION GATE) is applied to one of the first gate conductor layer or the second gate conductor layer, and the ground voltage is applied to the other of the first gate conductor layer or the second gate conductor layer on condition that the voltages are applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer such so that a current does not flow between the first impurity region and the second impurity region in a steady state.
Yang and Lee both fail to recite a Decoder Circuit.
Morishita teaches a decoder circuit (Fig. 1: 2) for the purpose of selecting rows of floating body memory cells (Fig. 2: MC) with a word line (Fig. 2: WL) and plate line (Fig. 2: GL) for the purpose of writing (Fig. 5: 1W) or erasing (Fig. 5: 0W) the cells.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Lee and Morishita to the teachings of Yang such that Yang’s memory device is erasable by applying a positive voltage to one of its impurity regions and ground to other impurity region while applying a positive voltage to one of the conduction layers, as taught by Lee, for the purpose of supplementing the teachings of Yang so its memory device can be operated using expected exemplary voltages from related devices during the related operations.
Regarding Claim 2, Yang, Lee, and Morishita teach the limitations of Claim 1.
Yang further teaches wherein in the page erase operation, at least one page is selected, and all of the memory cells included in the selected page are simultaneously erased (para 0047).
Regarding Claim 3, Yang, Lee and Morishita teach the limitations of claim 1.
Yang further teaches wherein the first impurity region (Fig. 2: 234) is connected to a source line (Fig. 2: 230, SL), the second impurity region (Fig. 2: 222) is connected to a bit line (Fig. 2: 230, BL), one of the first gate conductor layer (Fig. 2: 248) or the second gate conductor layer (Fig. 2: 244) is connected to a word line (Fig. 2: 242, WL), and the other of the first gate conductor layer (Fig. 2: 248) or the second gate conductor layer (Fig. 2: 244) is connected to a plate line (Fig. 2: 246, PL), and voltages applied to the source line (para 51), the bit line (para 50), the word line (para 52), and the plate line (para 53) are controlled to perform the page write operation and the page erase operation.
Regarding Claim 4, Yang, Lee and Morishita teach the limitations of claim 3.
Lee further teaches wherein in the page erase operation (Fig. 9: write0), a ground voltage is applied to the source line (Fig. 9: write0, SOURCE REGION), a positive voltage is applied to the bit line (Fig. 9: write0, BIT LINE), and a positive voltage is applied to one of the word line or the plate line (Fig. 9: write0, SELECTION GATE), and subsequently, a positive voltage is applied to the other of the word line or the plate line (Fig. 9: write0, GATE2) on condition that the voltages are applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer such that a current does not flow between the first impurity region and the second impurity region in a steady state.
Regarding Claim 5, Yang, Lee and Morishita teach the limitations of claim 3.
Yang further teaches the word line and the plate line are disposed in parallel (Fig. 9G: 945; para 8), and the bit line (Fig. 7: BL) is disposed in a direction perpendicular to the word line (Fig. 7: WL) and the plate line.
Regarding Claim 6, Yang, Lee and Morishita teach the limitations of claim 3.
Yang further teaches a first gate capacitance between the semiconductor body and the first gate conductor layer or the second gate conductor layer to which the plate line is connected is larger than a second gate capacitance between the semiconductor body and the first gate conductor layer or the second gate conductor layer to which the word line is connected (Fig. 4: 448, Lg, PL, WL; capacitance is a function of distance between the two conductors and area of the two conductors. Assuming the distance between the body, 210, and metal contact are equivalent for both the word line and plate line. And given that the height, Lg, of gate contacts is the same for each. Then the plate line having 5x contacts would therefore have a larger capacitance.).
Regarding Claim 8, Yang, Lee and Morishita teach the limitations of claim 3.
Lee further teaches a source line (Fig. 1: 102) is disposed so as to be connected in common to all of the memory cells in pages adjacent to each other.
Regarding Claim 9, Yang, Lee and Morishita teach the limitations of claim 3.
Yang teaches the plate line is disposed so as to be shared between at least two or more pages (para 22, 23) adjacent to each other.
Regarding Claim 10, Yang, Lee and Morishita teach the limitations of claim 1.
Yang further teaches the semiconductor body is a P-type semiconductor layer (Fig. 2: P+, 210), and the first impurity region (Fig. 2: 234, N+) and the second impurity region (Fig. 2: 222, N+) are N-type semiconductor layers.
Regarding Claim 11, Yang, Lee and Morishita teach the limitations of claim 1.
Yang further teaches the page erase operation wherein selective erasing is performed for the memory cells in at least two pages (para 47 and para 22-23).
Regarding Claim 12, Yang, Lee and Morishita teach the limitations of claim 1.
Yang further teaches the first gate conductor layer is constituted by two divided gate conductor layers (Fig. 4: 448, PL, Ls1) isolated from each other, and the divided gate conductor layers are positioned on respective sides of the second gate conductor layer (Fig. 4: 244), and the page write operation and the page erase operation are performed.
Regarding Claim 13, Yang, Lee and Morishita teach the limitations of claim 1.
Yang further teaches a gate conductor layer (Fig: 4: 448, Ls1) constituted by divided gate conductor layers isolated from each other (Fig. 4: , and the divided gate conductor layers are positioned on respective sides of the first gate conductor layer, and the page write operation and the page erase operation are performed.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20230282576), Lee et al (US 20210193661), and Morishita et al (20080251860), as applied to claim 3, in further view of Burnett et al. (US 6714436).
Regarding Claim 7, Yang, Lee and Morishita teach the limitations of claim 3.
However, they fail to teach isolated source lines.
Burnett, in teaching a related memory technology (i.e., floating body cell, or capacitorless DRAM), teaches that conventional memory array architectures employ a single source line, just like what Yang and Lee show in their Figures (see Burnett, col. 4, line 65-col. 5, line 3). Burnett further explain, that adding an additional source line, isolated from the other source line and separately controllable, is advantageous because it may minimize leakage current that might arise on unselected word lines (see Burnett col. 5, lines 19-34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Burnett to the combined teachings of Yang and Lee to produce a memory device where the source lines are isolated for each respective group of memory cells arranged in columns for the purpose of providing additional separately controllable source lines, instead of just one, to at least minimize current leakage from unselected word lines (see Burnett col. 4, line 65 to col. 5, lines 34).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20230282576), Lee et al (US 20210193661), and Morishita et al (20080251860), as applied to claim 3, in further view of Kang et al. ’751 (US 7701751) as supported by Kang et al. ’941 (US 8164941).
Regarding Claim 14, Yang, Lee and Morishita teach the limitations of claim 3.
However, neither reference shows the actual circuitry needed by the array to access the lines. Or as claimed, both references are silent to the necessary row decoder to be connected to the word line and plate line, and to select the page according to a row address it receives, as claimed.
Kang ’751 teach a related capacitorless DRAM that utilizes at least one access transistor. In Kang ’751, their word line controlling the floating body transistor (Fig. 6: WL0) is equivalent to the “plate line” of Yang and their “first port” word line (Fig. 6: WL0_P1) is equivalent to the “word line” of Yang. Both of these signal lines run in the row direction and both are controlled by a non-illustrated row decoder, as Kang ’751 explain in column 6, lines 20-24. Kang ’751 explains that this non-illustrated row decoder is the same as the row decoder disclosed in “Korean Patent Application no. 2007-0065033,” which corresponds to U.S. Patent 8164941 (“Kang ’941”). Kang ’941 show their row decoder (Fig. 5: 140) controlling the rows or pages in the memory array (Fig. 5: 140).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Kang ’751, as supported by Kang ’941, to the teachings of Yang and Lee, as combined, such that a necessary row decoder is included that would receive a row address and thereby control the word line and plate line of Yang for the purpose of providing the necessary circuitry to control the word line and plate line, so as to be able to expectedly control the standard operations of the memory.
Regarding Claim 15, Yang, Lee and Morishita teach the limitations of claim 3.
However, just like not disclosing any of the necessary peripheral circuitry for the memory array, Yang and Lee are silent to the specific provision of the necessary circuit to connect to the bit lines, including a sense amplifier circuit, a column decoder circuit, the input/output circuit, and the column address to control them.
Kang ’751 teach a related capacitorless DRAM that utilizes at least one access transistor that has at least a sense amplifier connected to its bit line. Kang ’751 does not show the column decoder or the column address, but Kang ’751 invokes peripheral circuitry features from one of their other patents, namely US 8164941 (col. 6, lines 20-24, which invokes “Korean Patent Application no. 2007-0065033,” corresponding to U.S. Patent 8164941 (“Kang ’941”)). Kang ’941 show not only their row decoder (Fig. 5: 140) controlling the rows or pages in the memory array (Fig. 5: 140), but also show the other expected peripheral circuitry for a memory array to operate, such as “a column decoder” (Fig. 5: 170), controllable by a “column address” (Fig. 5: “column address” received by column address register 180), the expected sense amplifier (Fig. 5: 210) to read out data from the memory array (Fig. 5: 150) and “input/output circuit” (e.g., Fig. 5: 240, 230, 220), all of which are necessary for proper functioning of a memory device under normal operation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Kang ’751, as supported by Kang ’941, to the teachings of Yang and Lee, as combined, such that a necessary column decoder, controllable by the column address, to access the bit lines of the memory array, along with the necessary sense amplifier to read data from the memory array, and the input/out circuitry is included with Yang’s memory device so as to be able to expectedly control the standard operations of the memory.
Response to Arguments
Applicant's arguments filed January 13, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments center solely on the method of operating the device as claimed but as stated in the previous office action applicant’s claims are directed to an apparatus rather than a method of operating an apparatus.
Lee is only combined with Yang and Morishita to address the method of operating limitations raised in Independent Claim 1. Yang teaches every structural limitation of Claim 1 with the exception of a decoder circuit, which Morishita teaches. Since the instant claims are apparatus claims and Lee treats the method of operating the apparatus it is unnecessary for forming a rejection of the disclosed invention. MPEP 2114(II) states “’[A]pparatus claims cover what a device is, not what a device does.’ Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a ‘recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus’ if the prior art apparatus teaches all the structural limitations of the claim.” Thus, the claims are still obvious solely by the combination of Yang and Morishita, which the applicant does not address in their remarks and is not overcome by the arguments.
Since the applicant can only differentiate their claims based on method of operation the rejections are maintained as the applicant has not made an argument that differentiates the apparatus they have claimed from the apparatuses described in the prior art.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825