DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Fast Field Programmable Gate Arrays (FPGAs) Compilation Through Bitstream Stitching”.
The disclosure is objected to because of the following informalities: it recites claims [see spec 0085 Example Embodiment page 26…]. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 10-12 and 15-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Weber et al USPN 11,101,804.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claims 1 and 15
Weber et al teaches
receive a design to be implemented onto a programmable fabric of an integrated circuit device (see abstract, an integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface);
determine that the design is implementable using two or more regional bitstreams from a library comprising a plurality of regional bitstreams (column 7, line 42, the designer may implement a circuit design to be programmed onto the programmable logic device 12 using a design description 14. The design description 14 may include a register-transfer level (RTL) design abstraction with constraints. Additionally or alternatively, the design description 14 may include high-level programming languages that may be converted to the a lower-level design description. For instance, the design description 12 may be specified using, OpenCL, C, data parallel C++ (DPC++), and the like. The design descriptions 14 may be submitted to a compiler 16, such as a version of INTEL® QUARTUS® by Intel Corporation of Santa Clara, Calif., to generate a low-level circuit-design defined by a bitstream 18, sometimes known as a program object file and/or configuration program, which programs the programmable logic device 12. Thus, the compiler 16 may provide machine-readable instructions representative of the circuit design to the programmable logic device 12. For example, the programmable logic device 12 may receive one or more configuration programs (bitstreams) 18 that describe the hardware implementations that should be stored in the programmable logic device 12. A configuration program (e.g., bitstream) 18 may be programmed into the programmable logic device 12 as a configuration program 20. The configuration program 20 may, in some cases, represent an accelerator function to perform machine learning functions, video processing functions, voice recognition functions, image recognition functions, networking functions, or other highly specialized task0;
stitch together the two or more regional bitstreams to generate a combined bitstream, wherein the two or more regional bitstreams are compiled at a different time than other portions of the design (column 23, 59, FIG. 29 illustrates the programmable logic device 12 having four portions (e.g., sectors). In some embodiments, the spatial fabric portions are stitched using configurable wires 532 (also referred to as fabric resources) to allow spatial fabric portions to communicate with each other. In some embodiments, the base portions are stitched together using an interconnect 534, such as the NOC 100. The interconnect 534 allows each FMIB 520 and BMIB 530 to access any of the base memory blocks 526. In some embodiments, the portions of the fabric die 22 and/or the base die 24 may have additional components or fewer components).
Regarding claim 2
Weber et al teaches
determining that at least one node of a first regional bitstream of the two or more regional bitstreams overlaps with at least one node of a second regional bitstream of the two or more regional bitstreams (column 34, line 42, a base die that vertically overlaps the fabric die, wherein the base die includes base memory, the programmable fabric and the base memory each include respective portions that have columnar alignment, and a capacity of the base memory and a bandwidth between the fabric die and the base die is selectively allocated to different granularity memory organizations) and (column 13, line 1, with the foregoing in mind, the NOC 100 may include the data or configuration pathways 99 that allow for efficient multi-dimensional (e.g., three-dimensional, two-dimensional) integration of the NOC 100 on the programmable logic device 12. Indeed, the NOC 100 may enable the fabric die 22 to connect to the peripheral circuitry 28 and other parts of the fabric without communicating via the fabric die 22 or the programmable logic sectors 48 of the fabric die 22. That is, by employing the NOC 100 in the base die 24, the programmable logic device 12 may increase the available bandwidth for communication across the programmable logic sectors 48 because the NOC 100 provides additional pathways to different parts of the programmable logic device 12);
stitching the first regional bitstream and the second regional bitstream together at the at least one overlapping node (column 13, line 56, Although FIGS. 6 and 7 illustrate two embodiments with different configurations for the NOC 100, it should be noted that the base die 24 may be configured to include a data or configuration pathways 99 in a variety of shapes, forms, positions, and the like. For example, the data or configuration pathways 99 of different sectors 90 may overlap each other, the entire sector 90 may incorporate the data or configuration pathway 99, or the like. In addition, microbumps may be used to facilitate communication between the NOC 100 and various sectors 80 of the fabric die 22 and the like).
Regarding claim 3
Weber et al teaches
determining routing through an interposer between a first regional bitstream of the two or more regional bitstreams and a second regional bitstream of the two or more regional bitstreams in response to determining the first regional bitstream does not overlap with the second regional bitstream (column 11, line 55, FIG. 6 provides an example complementary arrangement of the base die 24. The base die 24 may represent an active interposer with several sectors 90 surrounded by peripheral circuitry 28 and the silicon bridge interface 39. Although not shown in FIG. 6, each sector 90 may include a variety of fabric support circuitry, which may described in greater detail below. In any case, the base die 24, in some embodiments, may include data and/or configuration routers 98, and/or data or configuration pathways 99. In some embodiments, portions of the data or configuration pathways 99 may communicate data in one direction, while other portions may communicate data in the opposite direction. In other embodiments, the data or configuration pathways 99 may communicate data bi-directionally).
Regarding clam 4
Weber et al teaches
stitching a first regional bitstream of the two or more regional bitstreams to a first access point of a network-on-chip (column 14, line 33, referring back to FIG. 8, the memory control circuitry 93 may be used to program the sector-aligned memory 92, the CRAM of the fabric die 22, or both. The non-user input control circuitry 94 and non-user output control circuitry 95 may allow the circuitry of the sectors 90 to exchange data and/or control signals (e.g., via configurable data routing network-on-chip (NOC) or a configuration network on chip (CNOC)). In one example, the non-user input control circuitry 94 and non-user output control circuitry 95 may operate as the sector controller (SC) 58 for a corresponding fabric sector 80 (as shown in FIG. 5);
stitching a second regional bitstream of the two or more regional bitstreams to a second access point of the network-on-chip (column 6, line 51, In some embodiments, the programmable logic device may utilize one or more die, such as a programmable logic (or fabric) die having a fabric of programmable logic elements and a base die having fabric support circuitry, in a three-dimensional arrangement. In some systems, the programmable logic die may be sectorized, as detailed below. In such systems, the fabric support circuitry in the base die may include network on chip (NOC) circuitry to send or receive data (e.g., configuration data, user data) with systems external to the programmable logic device and/or between sectors in the programmable logic devices. The fabric support circuitry may also include sector-aligned memory. In some embodiments, the sector-aligned memory may operate as a temporary storage (e.g., cache) for the configuration data or user memory. By incorporating the NOC into the fabric support circuitry, the NOC may resolve periphery shoreline bandwidth issues of the fabric, while increasing the bandwidth of the fabric. In addition, the communication routes available via the NOC embedded in the fabric support circuitry may enable the fabric to implement design relocations or reconfigurations, provide alternate pathways around powered-down sectors of the fabric, and provide security isolation features. The NOC may be a source of configuration data or fabric data and may be integrated to access the multi-purpose high-speed interface. With the foregoing in mind, the embodiments described herein are related to the use of sector-aligned memory to increase the speed and the capacity of low-latency memory for programmable logic applications. Aggregation of bandwidth between the programmable die and the base die is also discussed).
Regarding claim 5
Weber et al teaches
determine that the combined bitstream comprises an unused area (column 27, line 11, the programmable logic device 12 may be used to perform a partial reconfiguration (PR) of the fabric where a portion of the fabric is reconfigured while one or more other portions of the fabric remain in use during the PR. The alignment of sectors or portions as of the fabric die 22 or base die 24 combined with sector alignment of PR enables an increase in the PR performance. The static compilation previously discussed focused on logic and memory placement of a single design. However, the concepts discussed related to the memory in the base die 24 may be extended beyond user data. For example, compilation may be used to store multiple partial reconfiguration personas. The separation of the memory for data and personas is part of the static compilation. A partial reconfiguration 630 is illustrated in FIG. 42. The partial reconfiguration 630 has PR regions 632 and are defined as part of a static compilation. The PR regions 632 and 634 have few restrictions on their size or shape and allow static routes 636 to go through the PR regions 632 and 634. The PR regions 632 and 634 may include inter-sector routes 638 that enable communication through the sectors 48 within a respective PR region 632 or 634. Each PR region 632 and 634 is capable of supporting any number of PR personas that have been compiled and/or relocated to the respective PR region 632 or 634 and use a subset of an input and output interface of the PR region 632 and 634.
power down a region of the integrated circuit device configured by the unused area (column 12, line 3, with the foregoing in mind, the data and/or configuration pathways 99 may make up a network on chip (NOC) 100. In the embodiment depicted in FIG. 6, the NOC 100 may be integrated between each sector 90 of the base die 24. As such, the NOC 100 may enable each of the sectors 90 disposed on the base die 24 to be accessible to each other. Indeed, the NOC 100 may provide communication paths between each sector 90 via routers 98 or the like. In certain embodiments, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like. Since the base die 24 is separate from the fabric die 22, the NOC 100 may be continuously powered on, even when various sectors 48 of the fabric die 22 are powered down. In this way, the NOC 100 of the base die 24 may provide an available route to different sectors 48 of the fabric die 22 regardless of the positions of powered down sectors 48).
Regarding claim 10
Weber et al teaches
receiving, via processing circuitry, a design to implement on an integrated circuit device (see abstract, an integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface);
mapping, via the processing circuitry, the design to two or more regional bitstreams stored in a library, wherein the two or more regional bitstreams are pre- compiled before compilation of other parts of the design (column 26, line 55, FIG. 41 is a flow diagram of a process 625 that may be deployed by the compiler 16 when organizing the programmable logic device 12. The compiler 16 maps implementations of designs (e.g., user logic 560, 562, and/or 564) to one or more FMIBs 520 (block 626). As previously noted, this mapping may be associated in the designs and/or inferred by placement of the designs. The compiler 16 then maps the FMIB(s) 520 to one or more memory arrays 570 of the base die 24 (block 627). The mapping may include a mapping from the FMIB(s) 520 to a corresponding BMIB 522. The mapping may include a forced direct access between an FMIB 520 and a corresponding memory array 570 when the latency and/or bandwidth between the designs and the array 570 is deterministic. The mapping may also include offsets in the FMIB 520 that provides a virtual starting address for the memory arrays 570. The compiler 16 may also map the one or more memory arrays 570 to memory in the fabric die 22 for bulk transfer and/or memory paging (block 628). As previously noted, the mapping between the memory array(s) 570 and the in-die memory may be based at least in part on associations set by a user and/or administrator. Store mapping in the ATU 223 and/or the MMU 2220;
stitching, via the processing circuitry, together the two or more regional bitstreams mapped to the design to generate a combined bitstream (column 23, 59, FIG. 29 illustrates the programmable logic device 12 having four portions (e.g., sectors). In some embodiments, the spatial fabric portions are stitched using configurable wires 532 (also referred to as fabric resources) to allow spatial fabric portions to communicate with each other. In some embodiments, the base portions are stitched together using an interconnect 534, such as the NOC 100. The interconnect 534 allows each FMIB 520 and BMIB 530 to access any of the base memory blocks 526. In some embodiments, the portions of the fabric die 22 and/or the base die 24 may have additional components or fewer components).
Regarding claim 11
Weber et al teaches
a programmable fabric of the integrated circuit device to implement a memory interface or an input/output interface (see abstract, an integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface).
Regarding claim 12
Weber et al teaches
determining placement for a first regional bitstream of the two or more regional bitstreams adjacent to a first access point of a network-on-chip (column 26, line 5, In some embodiments, the compiler 16 takes user input descriptions of the design and the definition of the architecture, physical address space 488, and ATU 223 restrictions to determine the placement of the user logic 560, 562, and 564 and the respective FMIBs 520 as shown in FIG. 38. FIG. 38 illustrates a depiction of the user logic 560, 562, and 564 mapped into the physical address space 488. Memory accesses that are labeled direct access in the designs are to be aligned within a defined proximity of the memory they access, such as the FMIB 520 and the array 570A. In some embodiments, memory access that are not defined as direct access are placed to minimize access latency and maximize bandwidth). In some embodiments, the compiler 16 takes the user input description of the design and the definition of the architecture, physical address space 488, and the ATU 223 restrictions to determine the placement of the user logic 560, 562, and 564, the respective FMIBs 520, base memory arrays 570, and spatial fabric memory 586 as shown in FIG. 39. Memory accesses that are labeled direct access in the designs are to be aligned within a defined proximity of the memory they access, such as the FMIB 520 and the array 570A. In some embodiments, memory accesses that are not defined as direct access are placed to minimize access latency and maximize bandwidth. In some embodiments, the MMU 222 may use the ATU 223 to translate the logical address space defined in the user's design to the physical address space 488 of the memory in the fabric die 22 or base die 24. In some embodiments, the MMU 222 may provide security to disable unauthorized access to memory. In some embodiments, the MMU 222 disables unauthorized access at the accessor. In some embodiments, the MMU 222 provides locking capabilities to isolate the read and/or write access of multiple accessors to a subset of addresses to enable memory consistency);
determining placement for a second regional bitstream of the two or more regional bitstreams adjacent to a second access point of the network-on-chip, wherein the first regional bitstream and the second regional bitstream are to communicate via the network-on-chip (column 26, line 55, FIG. 41 is a flow diagram of a process 625 that may be deployed by the compiler 16 when organizing the programmable logic device 12. The compiler 16 maps implementations of designs (e.g., user logic 560, 562, and/or 564) to one or more FMIBs 520 (block 626). As previously noted, this mapping may be associated in the designs and/or inferred by placement of the designs. The compiler 16 then maps the FMIB(s) 520 to one or more memory arrays 570 of the base die 24 (block 627). The mapping may include a mapping from the FMIB(s) 520 to a corresponding BMIB 522. The mapping may include a forced direct access between an FMIB 520 and a corresponding memory array 570 when the latency and/or bandwidth between the designs and the array 570 is deterministic. The mapping may also include offsets in the FMIB 520 that provides a virtual starting address for the memory arrays 570. The compiler 16 may also map the one or more memory arrays 570 to memory in the fabric die 22 for bulk transfer and/or memory paging (block 628). As previously noted, the mapping between the memory array(s) 570 and the in-die memory may be based at least in part on associations set by a user and/or administrator. Store mapping in the ATU 223 and/or the MMU 222) and (column 6, line 51, In some embodiments, the programmable logic device may utilize one or more die, such as a programmable logic (or fabric) die having a fabric of programmable logic elements and a base die having fabric support circuitry, in a three-dimensional arrangement. In some systems, the programmable logic die may be sectorized, as detailed below. In such systems, the fabric support circuitry in the base die may include network on chip (NOC) circuitry to send or receive data (e.g., configuration data, user data) with systems external to the programmable logic device and/or between sectors in the programmable logic devices. The fabric support circuitry may also include sector-aligned memory. In some embodiments, the sector-aligned memory may operate as a temporary storage (e.g., cache) for the configuration data or user memory. By incorporating the NOC into the fabric support circuitry, the NOC may resolve periphery shoreline bandwidth issues of the fabric, while increasing the bandwidth of the fabric. In addition, the communication routes available via the NOC embedded in the fabric support circuitry may enable the fabric to implement design relocations or reconfigurations, provide alternate pathways around powered-down sectors of the fabric, and provide security isolation features. The NOC may be a source of configuration data or fabric data and may be integrated to access the multi-purpose high-speed interface. With the foregoing in mind, the embodiments described herein are related to the use of sector-aligned memory to increase the speed and the capacity of low-latency memory for programmable logic applications. Aggregation of bandwidth between the programmable die and the base die is also discussed).
Regarding claim 16
Weber et al teaches
determining a first placement of a first regional bitstream of the at least two regional bitstreams adjacent to a first access point of a network-on-chip (column 12, line 3, with the foregoing in mind, the data and/or configuration pathways 99 may make up a network on chip (NOC) 100. In the embodiment depicted in FIG. 6, the NOC 100 may be integrated between each sector 90 of the base die 24. As such, the NOC 100 may enable each of the sectors 90 disposed on the base die 24 to be accessible to each other. Indeed, the NOC 100 may provide communication paths between each sector 90 via routers 98 or the like. In certain embodiments, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like. Since the base die 24 is separate from the fabric die 22, the NOC 100 may be continuously powered on, even when various sectors 48 of the fabric die 22 are powered down. In this way, the NOC 100 of the base die 24 may provide an available route to different sectors 48 of the fabric die 22 regardless of the positions of powered down sectors 48);
determining a second placement of a second regional bitstream of the at least two regional bitstreams adjacent to a second access point of the network-on-chip (column 14, line 32, With the foregoing in mind, the data and/or configuration pathways 99 may make up a network on chip (NOC) 100. In the embodiment depicted in FIG. 6, the NOC 100 may be integrated between each sector 90 of the base die 24. As such, the NOC 100 may enable each of the sectors 90 disposed on the base die 24 to be accessible to each other. Indeed, the NOC 100 may provide communication paths between each sector 90 via routers 98 or the like. In certain embodiments, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like. Since the base die 24 is separate from the fabric die 22, the NOC 100 may be continuously powered on, even when various sectors 48 of the fabric die 22 are powered down. In this way, the NOC 100 of the base die 24 may provide an available route to different sectors 48 of the fabric die 22 regardless of the positions of powered down sectors 48);
stitching the first regional bitstream to the first access point and the second regional bitstream to the second access point (column 23, 59, FIG. 29 illustrates the programmable logic device 12 having four portions (e.g., sectors). In some embodiments, the spatial fabric portions are stitched using configurable wires 532 (also referred to as fabric resources) to allow spatial fabric portions to communicate with each other. In some embodiments, the base portions are stitched together using an interconnect 534, such as the NOC 100. The interconnect 534 allows each FMIB 520 and BMIB 530 to access any of the base memory blocks 526. In some embodiments, the portions of the fabric die 22 and/or the base die 24 may have additional components or fewer components).
Regarding claim 17
Weber et al teaches
a size or a shape of the first regional bitstream is different from a size or a shape of the second regional bitstream (column 27, line 10, The programmable logic device 12 may be used to perform a partial reconfiguration (PR) of the fabric where a portion of the fabric is reconfigured while one or more other portions of the fabric remain in use during the PR. The alignment of sectors or portions as of the fabric die 22 or base die 24 combined with sector alignment of PR enables an increase in the PR performance. The static compilation previously discussed focused on logic and memory placement of a single design. However, the concepts discussed related to the memory in the base die 24 may be extended beyond user data. For example, compilation may be used to store multiple partial reconfiguration personas. The separation of the memory for data and personas is part of the static compilation. A partial reconfiguration 630 is illustrated in FIG. 42. The partial reconfiguration 630 has PR regions 632 and are defined as part of a static compilation. The PR regions 632 and 634 have few restrictions on their size or shape and allow static routes 636 to go through the PR regions 632 and 634. The PR regions 632 and 634 may include inter-sector routes 638 that enable communication through the sectors 48 within a respective PR region 632 or 634. Each PR region 632 and 634 is capable of supporting any number of PR personas that have been compiled and/or relocated to the respective PR region 632 or 634 and use a subset of an input and output interface of the PR region 632 and 634).
Regarding claim 18
Weber et al teaches
the network-on-chip spans from a first die of the integrated circuit device to a second die of the integrated circuit device, and wherein the first regional bitstream is to configure a first programmable fabric of the first die and the second regional bitstream is to configure a second programmable fabric of the second die (column 23, line 35, An embodiment of the programmable logic device 12 is provided in FIG. 28. As illustrated, a portion (e.g., a sector) of the fabric die 22 and the base die 24 are connected via the access ports 214 in a stacked-die architecture. The fabric die 22 contains a spatial compute fabric which contains one or more memories (e.g., M20Ks). The fabric die 22 has a local sector manager (LSM) 518 that controls the configuration of the fabric. In some embodiments, the LSM 518 coordinates the communication between the fabric die 22 and the base die 24. The fabric die 22 has a fabric multi-die interface bus (FMIB) 520 that is used to communicate with a base multi-die interface bus (BMIB) 522 in the base die 24 via the access ports 214. The base die 24 has a controller 524 that coordinates the communication between the fabric die 22 and the base die 24. As previously discussed, the base die 24 contains memory (e.g., memory block 526). In some embodiments, the base die 24 also contains compute units 528 (e.g., DPE or the like). Physically, the fabric and various memory sectors in the 3D columnar construction may have different sizes and/or use different technologies. Furthermore, even though the discussion related to two die in the programmable logic device 12, the programmable logic device 12 may contain more than two die).
Regarding claim 19
Weber et al teaches
determining a region of the programmable fabric not configured by the combined bitstream and powering down the region (column 13, line 30, as shown in FIG. 9, the NOC 100 may be integrated with the sector-aligned memory 92 of the base die 24, such that it spans across the entire base die 24. As such, the NOC 100 may access different fabric sectors 80 through various routes in the base die 24. In addition, the additional routes enable the NOC 100 to serve as functional bypass around powered down sectors 80 without affecting the performance of the programmable logic device 12 by avoiding blockages across the programmable logic sectors 48 of the programmable logic device 12. That is, in some situations, certain sectors 80 of the fabric die 22 may be powered down, thereby preventing communication across the powered down sectors 80. In this case, the NOC 100 may provide alternate communication pathways around the powered down sectors 80 to maintain communicative connectedness across the sectors 80 of the fabric die 22 regardless of whether certain sectors 80 are powered down).
Regarding claim 20
Weber et al teaches
determining a size of the combined bitstream is larger than a threshold; and dividing the combined bitstream into two or more separated bitstreams (column 31, line 42, In some embodiments, the compute 752 and the memory 750 are initially statically allocated, but the compute 752 (rather than the memory 750) is later dynamically allocated, re-allocated, and de-allocated. In some embodiments, moves (re-allocates) 770 of the compute 752 are performed as illustrated in FIG. 60. In some embodiments, the move (re-allocation) 770 of compute is performed using the NOC 100 of the base die 24 (or other memory interconnects). This move 770 of the compute 752 results in the memory 750 being close to the compute 752 to within a threshold distance to improve efficiency of the programmable logic device 12) and (column 11, line 15, As stated above, the logical arrangement of the FPGA 40 shown in FIG. 3 may result from a combination of the fabric die 22 and base die 24. The circuitry of the fabric die 22 and base die 24 may be divided in any suitable manner. In one example, shown in block diagram form in FIG. 4, the fabric die 22 contains primarily programmable logic fabric resources, such as the programmable logic elements 50, configuration memory 52, and user memory 53, and may be arranged in sectors such as sectors 65A and 65B. In some cases, this may also entail certain fabric control circuitry such as the sector controller (SC) 58 or device controller (DC) 60. The base die 24 may include supporting circuitry to operate the programmable logic elements 50, configuration memory 52, and user memory 53. As an example, the programmable logic elements 50 may exchange fabric data with the supporting circuitry in the base die 24 and configuration memory may exchange configuration data with the supporting circuitry in the base die 24. As shown here, the base die 24 includes support circuitry 70A, which may support fabric sector 65A, and support circuitry 70B, which may support fabric sector 65B. The base die 24 may also include support circuitry for other sectors of the fabric die 220).
Allowable Subject Matter
Claims 6-9 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Relevant Prior Art
US 6800884 B1 Feng et al teaches Inter-tile Buffer System For A Field Programmable Gate Array
US 9825635 B2 Munday et al teaches Programmable Logic Device Virtualization
US 7957208 B1 Tang et al teaches Flexible Memory Architectures For Programmable Logic Devices
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Anil Khatri whose telephone number is (571)272-3725. The examiner can normally be reached M-F 8:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wei Zhen can be reached at 571-272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANIL KHATRI/ Primary Examiner, Art Unit 2191
Prosecution Insights